JPH05313778A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the power consumption in the operating of a microcomputer. CONSTITUTION:When INTP0 becomes '1' in the STOP state, a clock generation circuit 3a starts clock oscillation. An ORAND gate 32 supplies clock 92 to a block 4a of a peripheral circuit 40 when INTP1 becomes 1, an ORAND gate 33 supplies clock 93 to a block 4b. When INTP2 becomes '1', the clock generation circuit 3a stops clock oscillation. With external input signals, the operation clock to the block of the peripheral circuit can be supplied or stopped. Thus, the reduction of the power consumption during operation is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a standby function for reducing power consumption.

[0002]

2. Description of the Related Art Generally, a microcomputer includes a microcomputer capable of taking a HALT state and a STOP state for controlling an operation clock as a standby function for reducing power consumption. By executing the HALT instruction, only the operation clock of the central processing unit (hereinafter referred to as CPU) of the microcomputer is stopped, only the CPU is stopped, and the other peripheral circuits are in the HALT state.

On the other hand, by executing the STOP instruction, the clock oscillation is stopped to stop all the clocks, and the CPU and the entire application system are stopped.
It is in the P state.

FIG. 5 is a block diagram showing a configuration example of a conventional microcomputer. The microcomputer shown in FIG. 5 includes a CPU 1 that controls the entire system, a standby control circuit 2 that controls a standby function, a peripheral circuit 4, and an interrupt control circuit 5 that controls an interrupt signal.
And a clock generation circuit 3 for generating an operation clock for the CPU 1 (hereinafter referred to as a CPU clock) and an operation clock for the peripheral circuit 4 and the interrupt control circuit 5 (hereinafter referred to as a system clock).

The CPU 1 outputs to the standby control circuit 2 a STOP order 62 indicating execution of a STOP instruction and a HALT order 63 indicating execution of a HALT instruction.

The standby control circuit 2 outputs to the clock generation circuit 3 a CPU clock stop signal 66 for stopping the CPU clock 90 and a system clock stop signal 64 for stopping the system clock 91.

The clock generation circuit 3 uses the CPU clock 9
0 is output to the CPU 1 and the system clock 91 is output to the peripheral circuit 4 and the interrupt control circuit 5, respectively. The interrupt control circuit 5 operates by using the system clock 91 as an input.

In the STOP state, the clock generation circuit 3
Stops the system clock 91, and the interrupt control circuit 5 does not accept an interrupt even if an interrupt signal is generated. In the HALT state, the clock generation circuit 3
When the interrupt signal is generated, the interrupt control circuit 5 accepts the interrupt signal and sets the HALT release signal 67 and the interrupt request signal 68 to "1".

When the microcomputer enters the HALT state, the CPU 1 decodes the HALT instruction and sets the HALT order 63 to "1". The standby control circuit 2 to which the HALT order 63 is input sets the CPU clock stop signal 66 to "1". The clock generation circuit 3 that has received the CPU clock stop signal 66 stops the CPU clock 90.

When the HALT state is released, the interrupt control circuit 5 inputs an interrupt signal to set the H
The ALT release signal 67 is set to "1". The standby control circuit 2 to which the HALT release signal 67 is input sets the CPU clock stop signal 66 to "0", and the clock generation circuit 3
The CPU clock 90 is supplied to the CPU 1.

When the microcomputer enters the STOP state, the CPU 1 decodes the STOP instruction and sets the STOP order 62 to "1". The standby control circuit 2 to which the STOP order 62 is input sets the system clock stop signal 64 and the CPU clock stop signal 66 to "1" respectively, and the clock generation circuit 2 sets the CPU clock 9
0 and the system clock 91 are stopped.

When releasing the STOP state, although not shown in FIG. 5, a reset signal is externally input to reset the entire microcomputer.

[0013]

In the above-mentioned conventional microcomputer, even if the standby function is used in order to reduce the power consumption, the STO is provided for each functional block.
In the P state, all operating clocks are stopped and H
In the ALT state, operation clocks other than the CPU are supplied.

As described above, there is no clock supply selecting means for supplying and operating the operation clock only to the necessary functional blocks. Therefore, there is a problem that it is difficult to reduce power consumption during operation.

An object of the present invention is to provide a microcomputer that realizes low power consumption during operation.

[0016]

To achieve the above object, a microcomputer according to the present invention comprises a clock generating circuit for supplying an operation clock to the entire system including a central processing unit, a clock oscillation starting means, and a clock oscillation. A microcomputer having a stopping means and a clock supplying means, wherein the clock oscillation starting means causes the clock generating circuit to start the clock oscillation by the first external input signal during the standby state in which the clock oscillation is stopped. The clock oscillation stopping means stops the clock oscillation started by the first external input signal in the standby state by the second external input signal, and the clock supply means is the first external input signal. The clock that started the clock oscillation by the input signal And supplies to the particular block only.

Further, the first external input signal for starting the clock oscillation is used for control of supplying a clock only to the specific block during the standby state in which the clock oscillation is stopped, and the standby It has means for utilizing it as an interrupt signal when it is not in the state.

[0018]

As shown in FIG. 1, in the STOP state, INTP
When 0 becomes "1", the clock generation circuit 3a starts clock oscillation. The ORAND gate 32 supplies the clock 92 to the block 4 a of the peripheral circuit 40. next,
When INTP1 becomes “1”, the ORAND gate 33
Supplies the clock 93 to the block 4b. further,
When INTP2 becomes "1", the clock generation circuit 3a
Stops clock oscillation.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of a microcomputer system according to Embodiment 1 of the present invention.

The microcomputer shown in FIG. 1 has a CPU 1a for controlling the entire system, a standby control circuit 2 for controlling a standby function, a clock controller 30 for generating a CPU clock 90 and a system clock 91.
A peripheral circuit 40, an interrupt control circuit 5, and external input terminals 52, 53, 54.

The microcomputer has an external input terminal 5
Signals INTP0, INTP1, and INTP2, which are also used as external interrupt input signals, are input from 2, 53, and 54.

The CPU 1a sends the standby control circuit 2
STOP order 6 indicating to execute a STOP instruction
2 and a HALT order 63 indicating that the HALT instruction has been executed, and the reset signal 10 is output to the OR gate 16.
Is output.

The OR gate 16 receives the reset signal 10 and I
The logical sum of NTP2 and SR flip-flop 12 and SR
It is output to the reset input of the flip-flop 13.
The OR gate 15 outputs the logical sum of the output of the SR flip-flop 12 and the output of the SR flip-flop 13 to the clock control unit 30.

When the system clock stop signal 64 is "1", the clock control section 30 starts clock oscillation by inputting the output "1" of the OR gate 15, and outputs the output "0" of the OR gate 15. A clock generating circuit 3a, which is a function added to the conventional clock generating circuit 3 to stop the clock oscillation upon input, an inverter 31, and an ORAN
It is composed of D gates 32 and 33 and an AND gate 34.

The clock generation circuit 3a, to which the system clock stop signal 64, the CPU clock stop signal 66 and the output of the OR gate 15 are input, is ORAND gates 32 and 3.
3 outputs the system clock 91 to the AND gate 34, and outputs the CPU clock 90 to the CPU 1a. Inverter 31 to which the system clock stop signal 64 is input
ORAND the inversion of the system clock stop signal 64
It outputs to the gates 32 and 33 and the AND gate 34.

The ORAND gate 32 is an inverter 31.
When the output of the SR flip-flop 12 is "1" or the output of the SR flip-flop 12 is "1", the clock 92 is supplied to the block 4a in the peripheral circuit 40, and the inverter 31
Is "0" and the output of the SR flip-flop 12 is "0", "0" is output. Similarly, ORA
The ND gate 33 supplies the clock 93 to the block 4b of the peripheral circuit 40 when the output of the inverter 31 is "1" or the output of the SR flip-flop 13 is "1". When the output of the inverter 31 is "1", the AND gate 34 outputs the clock 94 to the peripheral circuits other than the blocks 4a and 4b.

In the peripheral circuit 40, a part of the conventional peripheral circuit is divided into a block 4a and a block 4b. The peripheral circuits included in the block 4a operate on the clock 92. The peripheral circuits included in the block 4b operate on the clock 93. Peripheral circuits not included in any of the blocks 4a and 4b operate on the clock 94.

The interrupt control circuit 5 is a part of the peripheral circuit 40 and operates by inputting the clock 94. The interrupt control circuit 5 sends a HALT to the standby control circuit 2b.
The release signal 67 and the interrupt request signal 68 are output to the CPU 1b.

A method for releasing the HALT state and STOP
The method of canceling the state is the same as the conventional method. The interrupt control circuit 5 can input an interrupt signal to release the HALT state, and can input an external reset signal (not shown in FIG. 1) to release the STOP state.

FIG. 2 is a timing chart during the STOP state according to the first embodiment.

Referring to FIG. 1 and FIG. 2, the INTP0 signal and the INTP1 signal are input when the microcomputer is in the STOP state.
Signal, and supplies clocks 92 and 93 to the peripheral circuits of the block 4a and the block 4b, respectively.
The process until P2 is input and the supply of the clocks 92 and 93 is stopped will be described.

The CPU 1a uses the reset signal 10 in advance for SR
The flip-flop 12 and the SR flip-flop 13 are initialized to "0". CPU1a is STOP order 6
2 is set to "1", the standby control circuit 2 sets the system clock stop signal 64 to "1", and the CPU clock stop signal 6
Since 6 is set to "1", the clock generation circuit 3a is C
Both PU clock 90 and system clock 91 are "0"
Stopped at.

When INTP0 becomes "1", the output of the SR flip-flop 12 becomes "1", and the OR gate 15
Output is "1". The clock generation circuit 30 to which the output of the OR gate 15 is input starts clock oscillation.
When the clock oscillation becomes stable, the clock generation circuit 30
Starts supplying the system clock 91 to the ORAND gate 32. Since the output of the inverter 31 is "0" and the output of the SR flip-flop 12 is "1", the ORAND gate 32 supplies the system clock 91 to the block 4a as the clock 92.

On the other hand, in the ORAND gate 33, since the output 31 of the inverter is "0" and the INTP1 is "0", the output of the SR flip-flop 13 is "0", and the system clock 91 is sent to the block 4b. It cannot be output, and the clock 93 remains stopped at "0".

Then, when INTP1 becomes "1", SR
Since the output of the flip-flop 13 is "1" and the output of the OR gate 15 is "1", the ORAND gate 3
3 supplies the clock 93 to the block 4b.

Since the output of the inverter 31 is "0", the AND gate 34 keeps the clock 94 stopped at "0".

Further, when INTP2 becomes "1", S
Since both the R flip-flop 12 and the SR flip-flop 13 are reset to "0", the output of the OR gate 15 becomes "0" and the clock generation circuit 3a stops the clock oscillation.

When not in the STOP state, the system clock stop signal 64 is "0" and the output of the inverter 31 is "1", so that the ORAND gates 32, 33 and A are connected.
Each of the ND gates 34 can output the system clock 91 to the peripheral circuit 40.

(Second Embodiment) FIG. 3 is a block diagram showing a third embodiment of the present invention.

In the first embodiment, the external input signal I
Although NTP0 and INTP1 are used only for controlling which peripheral circuit block the operation clock is supplied to, in the present embodiment, whether an external input signal is used to supply the operation clock, a HALT state, or a normal use is used. It can be selected whether to handle it as an external interrupt signal.

The configuration of this embodiment has a CPU 1b, a standby control circuit 2, a clock control unit 30, and a peripheral circuit 4.
0, the interrupt control circuit 5, the external input terminals 52, 5
3, 54.

The CPU 1b has the function of the first embodiment, a function of starting an interrupt process when the interrupt request signal becomes "1", and a write signal 11 of "1" using the data bus 60 for the D latches 22 and 23. The function to write data at the timing of "is added.

The CPU 1b outputs the data bus 60, each bit of the bus is connected to the D latch 22 and the D latch 23, and the write signal 11 is output to the D latch 22 and the D latch 23.

When INTP0 is used to control the supply of the operation clock, the CPU 1b uses "1" for the D latch 22 and when INTP0 is used as an interrupt signal, "0" is applied to the D latch 22 and the write signal 11 Write at the timing of "1". Similarly, INTP1
Is used to control the supply of the operation clock, "1" is written in the D latch 23, and when INTP1 is used as an interrupt signal, "0" is written in the D latch 23.

The output of the D latch 22 is output to the AND gate 28 and the inverter 24. AND gate 26
Outputs the logical product of the SR flip-flop 12 and the inverter 24 to the interrupt control circuit 5. Similarly, D
The output of the latch 23 is the AND gate 29 and the inverter 25.
Is output to and. The AND gate 27 outputs the logical product of the SR flip-flop 13 and the inverter 25 to the interrupt control circuit 5.

The ANDOR gate 18 to which the reset signal 10, the system clock stop signal 64, and the INTP2 have been inputted receives the system clock stop signal 64 and the INTP2 both being "1" when the reset signal 10 is "1".
Then, the SR flip-flops 12 and 13 are reset to "0".

The AND gate 28 and the AND gate 29 output respective logical products to the clock control unit 30. The clock 94 is also output to the interrupt control circuit 5.

ORAND gate 3 of clock control unit 30
In the second embodiment, the output of the SR flip-flop 12 is input, but in the second embodiment, the AND gate 28 is used instead.
The output of is input. Similarly, the ANDOR gate 33
Is an AND gate 2 instead of the SR flip-flop 13.
9 outputs are input.

The microcomputer of this embodiment is STO.
In the P state, INTP0 is used to control the supply of the operation clock and INTP1 is used as an interrupt signal so that the CPU 1b previously sets the D latch 22 to “1”, D
The operation when the latch 23 is written to "0" will be described only in the part different from the first embodiment.

When INTP0 becomes "1", the output of the SR flip-flop 12 becomes "1" and the output of the D latch 22 becomes "1", so that the output of the AND gate 28 becomes "1". Since the output of the OR gate 17 becomes "1", the clock generation circuit 3a starts clock oscillation. Further, the ORAND gate 32 is the AND gate 28.
Becomes equivalent to that of the first embodiment, and the clock 92 is supplied to the block 4a.

When INTP1 becomes "1", the output of the SR flip-flop 13 becomes "1", but the D latch 23
The output of the AND gate 29 remains "0" because the output of the AND gate is "0". Since the output of the SR flip-flop 13 is "1", the output of the D latch 23 is "0", and the output of the inverter 25 is "1", the AND gate 2
The output of 7 becomes "1".

The interrupt control circuit 5 does not operate because the clock 94 is not supplied, and the HALT release signal 67
Both the interrupt request signal 68 and the interrupt request signal 68 are "0". That is, similarly to the conventional example, in the STOP state, the interrupt control circuit 5 cannot accept the interrupt even if the interrupt occurs.

FIG. 4 is a timing chart for the microcomputer of this embodiment to release the HALT state by an external input signal.

Referring to FIGS. 3 and 4, the microcomputers in the HALT state have INTP0, INTP1, INT.
Enter P2 to release the HALT status and C to CPU1b
The process up to supplying the PU clock 90 will be described.

The CPU 1b initializes the SR flip-flop 12 and the SR flip-flop 13 to "0" by a reset signal in advance. Since the CPU 1b sets the HALT order 63 to "1" and the standby control circuit 2 sets the CPU clock stop signal 66 to "1", the clock generation circuit 3a stops at the CPU clock 90 of "0". Since the output of the D latch 22 is "1" and the output of the inverter 24 is "0", the output of the AND gate 26 is "0".

When INTP0 becomes "1", the output of the SR flip-flop 12 becomes "1", and the AND gate 2
The output of 6 becomes "1". Although the output of the OR gate 17 becomes "1", the clock generating circuit 3a does not change its state because it is oscillating the clock.

Next, when INTP1 becomes "1", S
The output of the R flip-flop 13 becomes "1", but the output of the D latch 23 is "0", so that the output of the AND gate 29 remains "0". The output of the D latch 23 is "0"
And the output of the inverter 25 is "1", so A
The output of the ND gate 27 becomes "1". The interrupt control circuit 5 receives the HALT release signal 67 and the interrupt request signal 6
Set 8 and “1”.

The standby control circuit 2 sets the CPU clock stop signal 66 to "0", and the clock generation circuit 3a outputs C.
The supply of the PU clock 90 to the CPU 1b starts.

Since the CPU 1b is supplied with the CPU clock 90, the CPU 1b starts its operation, detects the interrupt request signal 68, sets the reset signal 10 to "1", and resets the SR flip-flops 12 and 13 to "0". To do. Subsequently, the CPU 1b starts an interrupt process corresponding to INTP1.

After reset, the SR flip-flop 12,
Since the output of 13 becomes "0", the AND gate 28,
The outputs of 29 are both "0", and the output of the OR gate 17 is also "0".

Even if INTP2 becomes "1", the system clock stop signal 64 is "0".
The output of the gate 18 remains "0" and does not affect the operation.

[0063]

As described above, according to the present invention, S
In the TOP state, the external input signal can supply the operation clock to the block of the peripheral circuit corresponding to the external input signal, and further, the external input signal can stop the supply of the operation clock to reduce the power consumption during the operation. realizable.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram of the first embodiment of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a timing diagram of the second embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional example.

[Explanation of symbols]

 1, 1a, 1b CPU 2 Standby control circuit 3, 3a Clock generation circuit 5 Interrupt control circuit 10 Reset signal 11 Write signal 12, 13 SR flip-flop 16, 17 OR gate 18 ANDOR gate 22, 23 D latch 24, 25, 31 Inverter 26, 27, 28, 29, 34 AND gate 30 Clock control unit 32, 33 ORAND gate 52, 53, 54 External input terminal 60 Data bus 62 STOP order 63 HALT order 64 System clock stop signal 66 CPU clock stop signal 67 HALT Release signal 68 Interrupt request signal 90 CPU clock 91 System clock 92, 93, 94 clock

Claims (2)

[Claims] 1. A microcomputer having a clock generation circuit for supplying an operation clock to the entire system including a central processing unit, a clock oscillation starting means, a clock oscillation stopping means, and a clock supplying means, the clock oscillation starting The means causes the clock generation circuit to start clock oscillation by the first external input signal during the standby state in which the clock oscillation is stopped, and the clock oscillation stopping means is the first external unit during the standby state. The clock oscillation started by the input signal is stopped by the second external input signal, and the clock supply means supplies the clock oscillation started by the first external input signal only to a specific block of the microcomputer. Microcomputers characterized by being Data. 2. The microcomputer according to claim 1, wherein the first external input signal for starting the clock oscillation is supplied to the specific block during a standby state in which the clock oscillation is stopped. A microcomputer, characterized in that it has means for utilizing it for control of supplying only a clock, and utilizing it as an interrupt signal when not in the standby state.