JPS62169560A - Duplexed clock signal generator - Google Patents

Abstract

PURPOSE:To avoid the omission of clock pulses in a system switching mode by using two signal source and using the selected signal source output clock to actuate two phase synchronizing oscillation circuits. CONSTITUTION:Selection indicating circuits 107 and 108 inform system selecting information to each other so that both clock switch circuits 103 and 104 select the outputs of the same signal sources 101 and 102. When the source 101 has a fault to cause an abnormal state where the output clock is cut off, both circuits 107 and 108 detect said abnormal state and output the switching signals to clock switching circuits 103 and 104. Both phase synchronizing oscillation circuits 105 and 106 absorb gradually the difference in phase between the input and output clocks and are finally synchronous with the A and B point clock signals II and III which are supplied from the source 102. Thus it is possible to avoid the ommision of pulses that are caused in a conventional clock signal source switching mode and then to absorb a large variation due to the operation of a processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a duplex clock signal generation device for supplying a duplex clock signal to a peripheral processor such as a distributed control type electronic exchange.

[Background of the invention]

The conventional duplex clock supply system is, for example, disclosed in Japanese Patent Application Laid-open No. 1983-
As described in Japanese Patent No. 23166B, an output clock switching control device controls a first clock generation circuit having a first clock signal source and a second clock generation circuit having a second clock signal source using a clock source selection lead. The clock signal is switched through the connection.

This conventional method has the problem of not being able to accurately and economically control the clock signal (pulse) supplied to the processor when switching the clock signal source, and that it is not possible to control the processor accurately and economically. There is a problem that the processor side cannot select one of the dual clocks.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a duplex clock signal generation device in which a clock signal can be selected on the processor side and no pulse loss occurs in clock pulses during system switching.

[Summary of the invention]

In order to achieve the above object, the duplex clock signal generation device of the present invention selects one of two signal sources, operates two phase synchronized oscillation circuits with the selected signal source output clock, and operates each phase synchronized oscillation circuit. Each output signal of the periodic oscillation circuit is supplied to an external device as a duplicated clock signal.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a complete duplex clock signal generation device according to an embodiment of the present invention. The fully duplexed clock signal generation device consists of a first clock signal generation circuit 109 and a second clock signal generation circuit 110 that have the same internal configuration, and each output of each clock signal generation circuit 109, 110 is connected to a peripheral processor 1"17. ,119...11n
Each of the processors 117 to 11n can select and use the clock supplied from either one of the clock signal generators 109 or 110.

The first clock signal generation circuit 109 includes a clock signal source 1
01, a clock switching circuit 103, a phase synchronized oscillation circuit 105, and a system selection instruction circuit 107, and the second clock signal generation circuit 110 includes a clock signal source 102,
It consists of a clock switching circuit 104, a phase synchronized oscillation circuit 106, and a system selection instruction circuit 108. Both signal sources 101 and 102 are connected to the clock switching circuit 106 and 104.
The output clock from the clock switching circuit 103 is inputted to the clock switching circuit 103.
．． 104 sends the clock from either one of the signal sources 101, 102 to the subsequent phase synchronized oscillation circuits 105, 106 according to instructions from the system selection instruction circuits 107, 108, respectively. Output signals are supplied to each of the processors 117-11n as outputs of the first and second clock signal generation circuits 109, 11Q, respectively. Both systems selection instruction circuits 107 and 108 notify each other of system selection information so that both clock switching circuits 105 and 104 select the output of the same signal source 101 and 102.

In the initial state when the power is turned on, the system selection instruction circuit 107.1
08 switches the clock switching circuits 103 and 104 to select the signal source 101, and outputs the output signal I (FIG. 2) from the clock signal source 101 to the phase synchronized oscillation circuit 105, respectively.
, 106. At the input points A and B of the phase synchronized oscillation circuits 105 and 106 that receive the same signal source clock signal I, the waveform delay operation of the same signal I is performed, so it is easy to make the pulse rising edge the same phase. (A point lock signal [, B point lock signal ■ in Figure 2)
.

The phase synchronized oscillator 105 is phase synchronized with the A-point lock signal 1 and outputs its output clock to the distributed processor 117.
...Supplied to 11n. In addition, the phase synchronized oscillator 106
supplies its output clock to the distributed processors 117° . . . 11Q in phase synchronization with the B-point lock signal ■. That is, the output clock signal of the first clock signal supply circuit 109 and the output clock signal of the second clock signal supply circuit 110 are apparently bit synchronized and have the same phase.

The distributed processor group can select and use either of the duplicated input clock signals,
Even if one of the clock supply circuits fails, the same clock is supplied from the other.

In that case, the clock signal supplied to the distributed processor group is supplied from the same clock signal oscillation source as the output clock of the first clock signal supply circuit 109 and the output clock of the second clock signal supply circuit 110. Therefore, the secular frequency fluctuation values are also the same.

When a failure occurs in the signal source 101 and an abnormal state occurs such as an interruption of the output clock, the system selection instruction circuits 107 and 108 detect the abnormality and transfer the switching signal to the clock switching circuits 103 and 104.
Output to. As a result, the clock switching circuits 103, 10
The clock signal supplied to the phase synchronized oscillation circuits 105 and 106 through the signal source 102 becomes the output clock (2) of the signal source 102. The clock signals at points A and B of the phase synchronized oscillator circuits 105 and 106 are changed to the signals ■ and ■ by switching the signal source.
to signal V (FIG. 2). However, the phase-locked oscillation circuit 105 and the phase-locked oscillation circuit 106 gradually absorb the difference between the phase of the input clock and the phase of the output clock, and finally the point A, where the clock signal source 102 is the supply source,
Synchronize with B point clock signals ■ and ■. As a result, pulse dropouts and the like that occur when switching the conventional clock signal source do not occur, and large fluctuations related to processor operation are absorbed.

In this way, the first and second clock signal generation circuits 10
9.11 The clock signal ■ shown in FIG. 2 is output from Q.

Similarly, the duplex clock signal generation device according to the present invention can be applied to a control device other than a distributed processor, which has a clock supply circuit that requires duplication of the supply clock circuit (for example, a control device of a network section of an electronic exchange, etc.). ) is also applicable.

〔Effect of the invention〕

According to the present invention, the supplied clock signal can be completely duplicated, and at the same time, each distributed processor can freely select the duplicated supplied clock signal without worrying about slip failure in inter-processor communication due to frequency fluctuation. It is possible to absorb fluctuations in the supplied clock signal due to switching of the supplied clock signal source, and to realize a highly reliable and stable clock signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a duplex clock signal generation device according to an embodiment of the present invention, and FIG. 2 is a signal time chart illustrating the operation of the device shown in FIG. 101.102... Signal source 103.104... Clock switching circuit 105
, 106...Face phase synchronous oscillation circuit 107.108
...System selection instruction circuit 109...First clock signal generation circuit 110...Second clock signal generation circuit 117, 118, 11n...Peripheral processor.

Claims (1)

[Claims] Two signal sources that generate clocks, and one that selects one of the output clocks from both signal sources and supplies it to the subsequent stage.
a system selection instruction circuit that instructs both clock switching circuits to select the same signal source at the same time and sends a switching signal to both clock switching circuits when an abnormality occurs; A duplex clock signal generation device comprising two phase-locked oscillation circuits arranged respectively, and supplying an output signal of each phase-locked oscillation circuit to an external circuit.