JPS5553956A - Clock distribution system - Google Patents

Clock distribution system

Info

Publication number
JPS5553956A
JPS5553956A JP12729878A JP12729878A JPS5553956A JP S5553956 A JPS5553956 A JP S5553956A JP 12729878 A JP12729878 A JP 12729878A JP 12729878 A JP12729878 A JP 12729878A JP S5553956 A JPS5553956 A JP S5553956A
Authority
JP
Japan
Prior art keywords
clock
clock distribution
distribution system
control
spe1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12729878A
Other languages
Japanese (ja)
Other versions
JPS5841023B2 (en
Inventor
Tatsuro Miyoshi
Kazuo Hamasato
Akira Kawada
Toshikatsu Yasuda
Tsuneo Katsuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP53127298A priority Critical patent/JPS5841023B2/en
Publication of JPS5553956A publication Critical patent/JPS5553956A/en
Publication of JPS5841023B2 publication Critical patent/JPS5841023B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Abstract

PURPOSE:To ensure the rational control for the clock distribution system by providing the clock system switching circuit after the master clock circuit. CONSTITUTION:Clock system switching circuits SW1 and SW2 are provided after master clock circuits MCLK(N) and MCLK(E). As a result, an isolation is secured between the clock distribution system control of clock supply sources DCS(N) and DCS(E) and the clock distribution system control within digital exchange TDX. Thus the interface is made clear. Furthermore, the clock distribution to channel system devices SPE1-SPEn is carried out from the single clock supply source and in two systems at all times, and as a result the control of the clock distribution system can be performed independently among devices SPE1-SPEn. Accordingly, the system control can be facilitated for the clock distribution.
JP53127298A 1978-10-18 1978-10-18 Clock distribution method Expired JPS5841023B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53127298A JPS5841023B2 (en) 1978-10-18 1978-10-18 Clock distribution method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53127298A JPS5841023B2 (en) 1978-10-18 1978-10-18 Clock distribution method

Publications (2)

Publication Number Publication Date
JPS5553956A true JPS5553956A (en) 1980-04-19
JPS5841023B2 JPS5841023B2 (en) 1983-09-09

Family

ID=14956495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53127298A Expired JPS5841023B2 (en) 1978-10-18 1978-10-18 Clock distribution method

Country Status (1)

Country Link
JP (1) JPS5841023B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169560A (en) * 1986-01-22 1987-07-25 Hitachi Ltd Duplexed clock signal generator
JPS6373754A (en) * 1986-09-17 1988-04-04 Fujitsu Ltd System clock distributing system
JPH086854A (en) * 1993-12-23 1996-01-12 Unisys Corp Outboard-file-cache external processing complex
JP2005531221A (en) * 2002-06-21 2005-10-13 トムソン ライセンシング Broadcast router configured to alternately receive multiple reference inputs or redundant reference inputs
JP2021016091A (en) * 2019-07-12 2021-02-12 Ｎｅｃプラットフォームズ株式会社 Transmission device, reception device, communication system, transmission method, and reception method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169560A (en) * 1986-01-22 1987-07-25 Hitachi Ltd Duplexed clock signal generator
JPS6373754A (en) * 1986-09-17 1988-04-04 Fujitsu Ltd System clock distributing system
JPH086854A (en) * 1993-12-23 1996-01-12 Unisys Corp Outboard-file-cache external processing complex
JP2005531221A (en) * 2002-06-21 2005-10-13 トムソン ライセンシング Broadcast router configured to alternately receive multiple reference inputs or redundant reference inputs
US7778155B2 (en) 2002-06-21 2010-08-17 Thomson Licensing Broadcast router configured for alternately receiving multiple or redundant reference inputs
JP2021016091A (en) * 2019-07-12 2021-02-12 Ｎｅｃプラットフォームズ株式会社 Transmission device, reception device, communication system, transmission method, and reception method

Also Published As

Publication number Publication date
JPS5841023B2 (en) 1983-09-09

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