KR0141292B1 - Circuit for controlling the duplexing in the full electronic switching system - Google Patents

Abstract

The redundancy control circuit is for efficiently controlling the redundancy between processors by controlling the generation of the active state control signal for the redundant processor in the all-electronic exchange. To this end, the circuit includes a first state transition controller for controlling an active / standby state transition of the own processor using a reset signal and a signal from which a malfunction of the own processor is detected; A second state transition controller and a first state transition controller for controlling an active / standby state transition of the counterpart processor based on a signal of detecting a malfunction of the counterpart processor, an active request signal of the own processor, and an active state control signal fed back; An active state control signal generation unit for generating an active state control signal to its own processor and the counterpart processor according to an output signal of the second state conversion controller; And a synchronization controller for selectively outputting the clock signal of the own processor and the clock signal of the counterpart processor to adjust the generation synchronization of the active state control signal.

Description

Redundancy Control Circuit in Electronic Switching System

1 is a diagram illustrating a relationship between redundant processors in an electronic switch having a redundant control circuit according to the present invention.

2 is a detailed circuit diagram of the redundancy control circuit shown in FIG.

3 is an operating waveform diagram of FIG. 2 at power on,

4 is an operating waveform diagram of FIG.

5 is an operation waveform diagram of FIG. 2 when a counterpart processor malfunctions.

* Explanation of symbols for main parts of the drawings

100: self processor 110: opponent processor

101: hardware unit 102: redundancy control circuit

20: first state conversion control unit 21: second state conversion control unit

22: active state control signal generator 23: synchronization control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundancy control circuit in an all-electronic exchange, and more particularly, to a redundancy control circuit for controlling the active state switching between redundant processors in the event of a failure.

In general, the electronic switchboard is provided with dual processors that perform the same function for stable operation of the system. That is, the electronic switchboard includes two processors performing the same function and becomes active at power-on. Slave that has been set to standby state when the master processor is set as a master processor and a processor that is in standby state is set as a slave processor when the master processor fails (Fail or abnormal state). By switching the processor to the active state and simultaneously switching the master processor to the standby state, the corresponding functions are controlled.

However, in such a redundant structure, even when the master processor is in an abnormal state at power-on, an attempt is made to set it to an active state unconditionally by the set default value. If such an abnormal state is detected, the active state of the slave processor is detected. There was a problem in starting the operation after power-on by performing state switching. In addition, there is a problem that the standby / active state is switched due to the glitches generated during operation.

Accordingly, an object of the present invention is to provide a redundancy control circuit for efficiently controlling redundancy between processors by controlling generation of an active state control signal for a redundant processor in order to solve the above-mentioned problems in an all-electronic exchange.

In order to achieve the above object, a circuit according to the present invention includes a redundant control circuit of an all-electronic exchanger provided with a plurality of processors performing the same function; A first state transition controller for controlling an active / standby state transition of the own processor using the reset signal and a signal detecting whether a malfunction of the own processor occurs; A second state conversion controller for controlling an active / standby state transition of the counterpart processor based on a signal detecting whether a counterpart processor has malfunctioned, an active request signal of the own processor, and an active state control signal fed back; An active state control signal generation unit for generating an active state control signal to its own processor and the counterpart processor according to the output signals of the first state conversion control unit and the second state conversion control unit; And a synchronization controller for selectively outputting the clock signal of the own processor and the clock signal of the counterpart processor to adjust the generation synchronization of the active state control signal.

Next, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a relationship between a redundant processor in an electronic switch having a redundancy control circuit according to the present invention, and the two redundant processors are referred to as their own processors (commonly referred to as local processors or master processors for convenience of description). ) And the other processor (commonly called a remote processor or slave processor), but when viewed from the other processor side shown in FIG. 1, the other processor becomes its own processor and the part shown as its own processor is the other processor. May be referred to.

The self processor 100 and the counterpart processor 110 having the same function and structure, as shown in the self processor 100 of FIG. 1, have no unit for the hardware unit 101, the counterpart processor 110 of the corresponding processor. Remote Active Identification Flag (RAIF), RECLK (REmote Clock) signal, and REQAIF (REQuests Active Identification Flag) and FFAIL (Function) applied from the corresponding processor unit 110 And a redundancy control circuit 102 for generating an active identification flag (AIF), which is an active state control signal, by the FAIL) and LOCLK (Local Clock) signals to control redundancy. Here, the RAIF signal is an AIF signal generated from the counterpart processor 110, the RECLK signal is a clock signal from the counterpart processor 110, and the REQAIF is an AIF received from the redundancy control circuit 102 in software in its processor 100. The signal is an active response signal, and FFAIL is a signal generated by monitoring a hardware and software failure in the processor 100, and LOCLK is a clock signal of the processor 100.

FIG. 2 is a detailed circuit diagram of the redundancy control circuit shown in FIG. 1, and includes a first state transition control unit for controlling an active / standby state transition to the counterpart processor 110 by a system reset signal RESET and a FFAIL signal. 20, the second state transition control section 21 for controlling the active / standby state transition to the own processor 100 by the RAIF signal, the REQAIF signal and the AIF signal, and the FFAIL signal as the selection control signal and the LOCLK signal. Preset (PRESET or PRN) by a signal output from the first state conversion control unit 20 and the synchronization control unit 23 configured as a multiplexer for selectively outputting the RECLK signal to adjust the synchronization of the active state control signal to be hushed And an AIF signal for controlling the active state in synchronization with a clock signal output from the multiplexer 23 as a signal output from the second state conversion controller 21 as an input signal. It consists of a castle active state control signal generating section 22 consisting of D flip peulreup to. The generated AIF signal is transmitted to the hardware unit 101 of its own processor and the redundancy control circuit (not shown) of the counterpart processor 110. When transmitted to the counterpart processor 110, it is named as a RAIF signal and transmitted through a backplane.

In particular, the first state conversion control unit 20 performs an AND operation on the inverter IN1 for reversing the logic state of the FFAIL signal, a reset signal RESET, and an AND logic gate G1 for ANDing the signal output from the inverter IN1. Is made of. In addition, the second state transition control unit 21 includes an inverter IN2 for inverting the logic state of the RAIF signal, a gate G2 for integrating the REQAIF signal and the AIF signal fed back, the inverter IN2 and the gate G2. Gate G3 for ANDing the output signal.

The redundant control circuit 102 in the self processor 100 and the counterpart processor 110 configured as described above (the redundancy control circuit of the counterpart processor 110 is not shown) is simultaneously powered on for each processor and simultaneously FFAIL, RAIF, and LOCLK. It accepts the signal and generates an AIF signal. At this time, when the function of the own processor is normal, since the FFAIL signal is in a low logic state as in the third (D), the signals applied to the gate G1 are all in the high logic state, so that the first state transition controller 20 The signal output from is in high logic state. The signal output from the first state conversion control unit 20 is applied to the preset terminal PRN of the active state control signal generation unit 22 (hereinafter referred to as D flip flop) composed of the D flip flops. However, since the preset terminal PRN becomes an active state in the low logic state, the output of the first state conversion controller 20 is not affected. In addition, since the processor 100 is not yet set to the active state, the REQAIF signal is converted to low logic at the same time as the third (E) degree to request the setting of the active state.

The gate G2 in the second state conversion controller 21 is applied in high logic at a point where the feedback AIF signal applied to the other input terminal is converted to low logic as shown in FIG. 3 (H). This is because the processor 100 has not yet been set to the active state. The high logic level is output regardless of the logic change of the REQAIF signal. The output signal is applied to one input terminal of the gate G3.

On the other hand, since the RAIF signal provided from the counterpart processor 110 is applied in a high logic state as shown in FIG. 3 (F) (since the counterpart processor 110 is not yet set to an active state). It is converted into a low logic state through the inverter IN2 and applied to the other input terminal of the gate G3. As a result, the gate G3 outputs low logic. The output of the gate G3 is applied to the D input terminal of the D flip-flop portion 22.

When the FFAIL signal, which is applied to the selection signal input terminal SEL, is applied in low logic as shown in FIG. 3D, the multiplexer 23, which is a synchronization controller, receives a LOCLK signal, which is a clock signal of its own processor 100. Choose to print. At this time, the output signal C1 has the same period as that of the third (G) diagram. The reason why the clock signal of FIG. 3 (B) does not coincide with the edge portion is a delay due to the processing time of the multiplexer 23. The output of the multiplexer 23 is applied to the clock terminal of the D flip-flop 33.

The D flip-flop 22 is synchronized with the clock signal applied from the multiplexer 23, and the time point as shown in FIG. 3 (H) by the input signal applied from the second active state control signal generator 21 is shown. Outputs the AIF signal converted to low logic. As a result, the processor 100 itself is set to an active state.

When the active state of the processor 100 is set to the active state of the counterpart processor 110, since the RAIF signal is applied in the low logic state, the logic of the signal output from the second state conversion controller 21 is in the high logic state. Then, the AIF signal, which is the output signal of the D flip-flop 22, is output in a high logic state to set the own processor 100 in the standby state.

When power is simultaneously applied to the two processors at the time of power-on by the redundant control circuit according to the present invention as described above, the side to which the power is applied first becomes active.

When the processor 100 is set to the active state, if a functional failure occurs during operation, the redundancy control circuit 102 is operated as shown in the timing diagram of FIG. 4.

That is, when an abnormal state is generated by the internal monitor processing unit (not shown) during the active operation, the FFAIL signal is converted into a high logic state as shown in the fourth (D) diagram and applied to the first state conversion control unit 20. Accordingly, since the FFAIL signal applied through the inverter IN1 is converted into a low logic signal, the first state conversion controller 20 outputs the gate G1 output signal as a low logic signal. The output signal is applied to the preset terminal PRN of the D flip-flop 22, so that the D flip-flop 22 is preset to output the output signal AIR regardless of the signal and the clock signal applied to the D input terminal. As shown in the fourth diagram (H), the transition to the high logic state is performed. The output AIR signal is transmitted to the counterpart processor 110 and the REQAIF signal generator (not shown) in the processor 100 so that the processor 100 switches from the active state to the standby state, and the counterpart processor 110. Allows the switch from the standby state to the active state.

In addition, when a functional failure occurs in the counterpart processor 110 while the counterpart processor 110 is set to operate in an active state, the operation of the redundancy control circuit 102 operates as shown in FIG. 5.

That is, when a failure occurs in the counterpart processor 110, the RAIF signal is converted into a high logic state as shown in the fifth (E) degree and applied to the inverter IN2 in the second state conversion controller 21, so that the gate G3 is different. Low logic is output regardless of the signal and logic state applied to one input terminal. The output signal is applied to the D input terminal of the D flip flop 22.

The D flip-flop 22 outputs an AIF signal converted to low logic as shown in the fifth (H) diagram by synchronizing the signal applied to the D input terminal with the clock signal C1 applied from the multiplexer 23. Accordingly, the own processor 100 is transferred from the standby state to the active state, and the counterpart processor 110 is transferred from the active state to the standby state.

As described above, the present invention includes a redundancy control circuit in a redundant structure in an all-electronic exchange to control active / standby state switching, so that the active state can be efficiently set as compared to the active setting by default at power-on. Also, it can prevent active / standby switching by glitch during operation, which makes stable redundancy control effective.

Claims (4)

A redundancy control circuit of an all-electronic exchanger provided with a plurality of processors for performing the same function, the redundant; A first state transition controller for controlling an active / standby state transition of the own processor using the reset signal and a signal detecting whether a malfunction of the own processor occurs; A second state conversion controller for controlling an active / standby state transition of the counterpart processor by a signal detecting whether a counterpart processor has malfunctioned, an active request signal of the own processor, and an active state control signal fed back; An active state control signal generation unit for generating the active state control signal to the own processor and the counterpart processor according to the output signals of the first state conversion control unit and the second state conversion control unit; And a registration control unit for selectively outputting a clock signal of the own processor and a clock signal of the counterpart processor to adjust the generation motive of the active state control signal. The synchronization state control unit of claim 1, wherein the active state control signal generation unit uses an output signal of the second state conversion control unit as an input signal, and a preset state is controlled by an output signal of the first state conversion control unit. A redundancy control circuit in an all-electronic exchange comprising a D flip flop whose output signal is a clock signal. 3. The system of claim 2, wherein the redundancy control circuit outputs the active state control signal so that the self processor is set to an active state by presetting the D flip-flop when the self processor is normal at power on. Redundancy control circuit in electronic exchanger. The redundant circuit of claim 1 or 2, wherein the synchronization controller comprises a multiplexer configured to control the selection of the clock signal based on a signal that detects whether a function failure of the own processor occurs. .