KR200157689Y1 - Network synchronizing clock receiving circuit - Google Patents

Abstract

The present invention relates to a network synchronizer clock receiving circuit of an exchanger installed in the exchanger to receive a network synchronizer clock. In a redundant network synchronizer clock receiving circuit, an operation state signal and a hardware state signal are exchanged between the redundant circuit boards. The present invention relates to a network synchronizer clock reception circuit of an exchange to prevent malfunction by chattering.

In the conventional network synchronizer clock receiving circuit, chattering occurs when the circuit board is mounted due to insufficient capacity of the capacitor connected to the signal input terminal of the counter board state detection unit. The operating status signal and hardware status signal applied from the circuit board are changed so that the mounted circuit board is operated as a master board even though it must be operated as a slave board due to the misunderstanding of the operating situation of the other circuit board. . In addition, in order to solve such a problem, when the capacity of the capacitor is increased, the capacitor absorbs the corresponding operating switching information output in the form of an instantaneous pulp signal from the software switching unit when the operation is switched by the software switching unit. There was a problem that makes it impossible to change the operation.

The present invention prevents malfunction due to chattering when the operation state signal and the hardware state signal are exchanged between the redundant circuit boards in the redundant network synchronizer clock receiving circuit, so that the network synchronizer clock receiving circuit can perform stable duplication operation. .

Description

Network synchronizer clock reception circuit

1 is a block diagram of a network synchronizer clock receiving circuit of a conventional exchange.

2 is a block diagram of a network synchronizer clock receiving circuit according to the present invention.

3 is a detailed block diagram of the pulse width control unit shown in FIG.

* Explanation of symbols for main parts of the drawings

10: counter board state detection unit 11: redundancy control unit

12: reset switch switching unit 13: hardware failure detection unit

14: software switching unit 20: pulse width control unit

21: Multivibrator

The present invention relates to a network synchronizer clock receiving circuit of a switch installed at the exchange receiving the network synchronizer clock. In particular, in a redundant network synchronizer clock receiving circuit, an operation state signal and a hardware state signal are transmitted between the redundant circuit boards. The present invention relates to a network synchronizer clock reception circuit of an exchange to prevent malfunction due to chattering.

In general, in order to operate a plurality of exchanges in a synchronous manner, the exchanger clocks are exchanged during the exchange period, and the exchanges are operated in accordance with the timing of the corresponding synchronizer clocks. In addition, in order to stably perform the operation of receiving the synchronizer clock at the exchange, two identical synchronizer clock receiver circuits are provided and operated in a redundant manner so that when one of the synchronizer clock receiver circuits fails, the other synchronizer clock receiver circuits are used. It transfers to and receives the network synchronizer clock. One network synchronizer clock receiving circuit operates as a master board and performs the network synchronizer clock receiving operation normally, and the other network synchronizer clock receiving circuit is a slave board. It operates as a stand-by state, and when the master board fails and does not operate normally, the slave board switches to the master board and performs normal operation.

As shown in FIG. 1, the network synchronizer clock receiving circuit provided in the conventional exchange includes the counter board state detection unit 10, the redundancy control unit 11, the reset switch switching unit 12, the hardware failure detection unit 13, and the software. It is provided with a switch 14 and the capacitor (C1, C2). The network synchronizer clock receiver circuit is provided in a redundant manner in the exchange. The network synchronizer clock receiver circuit shown in FIG. 1 shows only one of the redundant circuits. The counter board state detection unit 10 detects a counterpart operation state signal and a counterpart hardware state signal applied from the counterpart circuit board and outputs the corresponding detection information to the duplication control unit 11. Is used to indicate whether or not the master board is operating, and the relative hardware status signal is used to indicate whether or not the other circuit board is mounted. The reset switch switching unit 12 outputs the corresponding information to the redundancy control unit 11 when a reset switch for instructing to operate the corresponding synchronizer clock receiving circuit as a slave board is input. The hardware failure detection unit 13 detects whether a failure occurs in each circuit unit (not shown) provided in the network synchronizer clock receiving circuit and outputs the corresponding information to the duplication control unit 11 side. The software switching unit 14 is for operating switching to the master synchronizer clock receiving circuit master board or slave board according to the operating switching information applied through a terminal (not shown in the drawing), and duplicates the applied operating switching information. Output to the control part 11 side. The redundancy control unit 11 performs redundancy operation of the network synchronizer clock receiving circuit in accordance with information applied from the counter board state detection unit 10, the reset switch switching unit 12, the hardware failure detection unit 13, and the software switching unit 14. When the information indicating that the relative operation status signal is detected from the counter board state detection unit 10 is applied and the information indicating that the counter hardware status signal is detected is applied, the network synchronizer clock reception circuit controlled by the counter board state detection unit 10 is controlled. If it operates as a slave board, and reset switch switching information is applied from the reset switch switching unit 12, it operates the slave synchronizer clock receiving circuit controlled by itself as a slave board and operates the slave synchronizer clock receiving circuit controlled by itself. If hardware failure detection information is applied from the hardware failure detection unit 13 during operation as a master board, When the operation of the network synchronization clock receiving circuit to be controlled by the slave board, and the operating switching information is applied from the software switching unit 14, the master synchronization or slave slave clock clock circuit controlled by the master according to the operation switching information. Operate to the board. On the other hand, the redundancy control unit 11 determines whether its own operation state signal for informing whether or not the network synchronizer clock receiving circuit that it controls operates as a master board, and whether the network synchronizer clock receiving circuit that it controls is installed. It outputs its own hardware status signal to the opposing circuit board to indicate whether or not.

In such a conventional synchronizer clock receiving circuit, chattering is performed when the circuit board is mounted due to insufficient capacitance values of the capacitors C1 and C2 connected to the signal input terminal of the counter board state detection unit 10. In this case, due to chattering, the operation status signal and hardware status signal applied from the opposing circuit board are fluctuated. Nevertheless, there is a problem of operating as a master board. In addition, in order to solve such a problem, when the capacity of the capacitors C1 and C2 is increased, the corresponding output is output from the software switching unit 14 in the form of an instantaneous pulse signal during the operation switching by the software switching unit 14. There is a problem in that the operation switching information is absorbed by the capacitors C1 and C2, so that the operation switching by software is impossible.

The present invention has been made to solve the problems described above, and stable duplication by preventing malfunction due to chattering when the operation state signal and the hardware state signal are exchanged between the redundant circuit boards in the redundant network synchronization clock receiving circuit. It is an object of the present invention to provide a synchronizer clock receiving circuit of an exchange which is operated.

In order to achieve the above object, a network synchronizer clock receiving circuit of the switch according to the present invention includes a counter board state detection unit for detecting a counter operating state signal and a counter hardware state signal applied from a counter circuit board and outputting corresponding detection information. ; A reset switch switching unit for outputting corresponding reset switch switching information when a reset switch for instructing to operate the network synchronizer clock receiving circuit as a slave board is input; A hardware failure detection unit for detecting whether a failure occurs in each circuit unit provided in the network synchronizer clock receiving circuit and outputting corresponding failure detection information; A software switching unit for outputting operation switching information applied through the terminal; According to the information from the counter board state detection unit, reset switch switching unit, hardware failure detection unit and software switching unit, the duplex operation of the network synchronizer clock receiving circuit is controlled, and whether the circuit board controlled by itself is operated as a master board. A switch having a redundancy control unit for outputting its operating status signal for indicating whether or not and its own hardware status signal for indicating whether or not a network-synchronized clock receiving circuit that it controls is mounted on the opposite circuit board side. 1. A network synchronizer clock receiving circuit, comprising: a pulse width control section for outputting a long pulse width signal corresponding to a pulse signal applied from said software switching section to said duplication control section; A first capacitor having a first terminal connected to a first signal input terminal of the counter board state detection unit and a second terminal grounded to absorb chattering which is mixed with an operation state signal applied from a counter circuit board; A first capacitor connected to a second signal input terminal of the counter board state detection unit and a second terminal grounded to absorb a chattering signal mixed with a hardware state signal applied from a counter circuit board; It is characterized by.

According to a preferred embodiment of the present invention, the pulse width control unit includes a multivibrator for outputting a long pulse width signal to the redundancy control unit by performing an oscillation operation when a signal is applied from the software switching unit. do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the network synchronizer clock receiving circuit of the switch according to the present invention has a counter board state detection unit 10, a redundancy control unit 11, a reset switch switching unit 12, a hardware failure detection unit 13, and a pulse. Width control section 20, software switching section 14 and the condenser (C3, C4) is made. The network synchronizer clock receiving circuit is provided redundantly in the exchange, and the network synchronizer clock receiving circuit shown in FIG. 2 shows only one of the circuits that is redundant. The partner board state detector 10 detects a partner operating state signal and a partner hardware state signal applied from the partner circuit board and outputs the corresponding detection information to the duplication control unit 11. The reset switch switching unit 12 outputs the corresponding information to the redundancy control unit 11 when a reset switch for instructing to operate the corresponding synchronizer clock receiving circuit as a slave board is input. The hardware failure detection unit 13 detects whether a failure occurs in each circuit unit (not shown) provided in the network synchronizer clock receiving circuit and outputs the corresponding information to the duplication control unit 11 side. The software switching unit 14 is for operating switching a network synchronizer clock receiving circuit to a master board or a slave board according to operating switching information applied through a terminal (not shown in the drawing), and pulses the applied operating switching information. Output to the width control part 20 side.

The pulse width control unit 20 adjusts the signal pulse width of the operation switching information applied from the software switching unit 14 and outputs it to the redundancy control unit 11 side. The duplication control unit 11 performs a duplex operation of the network synchronizer clock receiving circuit according to information applied from the counter board state detection unit 10, the reset switch switching unit 12, the hardware failure detection unit 13, and the software switching unit 14. When the information indicating that the relative operation status signal is detected from the counter board state detection unit 10 is applied and the information indicating that the counter hardware status signal is detected is applied, the network synchronizer clock reception circuit controlled by the counter board state detection unit 10 is controlled. If it operates as a slave board, and reset switch switching information is applied from the reset switch switching unit 12, it operates the slave synchronizer clock receiving circuit controlled by itself as a slave board and operates the slave synchronizer clock receiving circuit controlled by itself. If hardware failure detection information is applied from the hardware failure detection unit 13 during operation as a master board, When the operation of the network synchronizer clock receiving circuit to be controlled by the slave board, and the operating switching information is applied from the software switching unit 14 via the pulse width control unit 20, the control unit itself controls according to the operating switching information. Operate the master clock slave circuit as master or slave board. On the other hand, the redundancy control unit 11 determines whether its own operation state signal for informing whether or not the network synchronizer clock receiving circuit that it controls operates as a master board, and whether the network synchronizer clock receiving circuit that it controls is installed. It outputs its own hardware status signal to the opposing circuit board to indicate whether or not. The capacitors C3 and C4 connected to the signal input terminal of the counter board state detection unit 10 have a capacitance value large enough to prevent chattering.

On the other hand, the pulse width control unit 24 is composed of a multivibrator 21, resistors (R1, R2) and a capacitor (C5) as shown in FIG. The signal applied from the software switching unit 14 is input to the input terminal A of the multivibrator 21, the input terminal B is grounded, and the power supply Vcc is provided to the clear terminal CL via a resistor R1. ) Is connected, the power supply Vcc is connected to the input terminal C via the capacitor C5 and the resistor R2, and the connection point of the capacitor C5 and the resistor R2 is connected to the input terminal RC. , Output ( ) Outputs a signal to the redundant control unit 11 side. When the multivibrator 21 receives a signal from the software switching unit 14 to the input terminal A, the multivibrator 21 performs an oscillation operation to output a signal having a long pulse width. ) Is output to the duplication control unit 11 side.

When a circuit board is mounted on an exchanger in this manner, when the circuit board is mounted on the exchanger, when the chattering occurs, the large capacity capacitors C3 and C4 absorb the chattering so that the operation state signal and the hardware state signal are not changed. Therefore, since the operation state signal and the hardware state signal are stably applied to the corresponding circuit board to be mounted, it is possible to solve the problem that the mounted circuit board operates as a master board due to the misunderstanding of the operating situation of the opposite circuit board. have. In addition, when the operation switching information is output from the software switching unit 14 in the form of an instantaneous pulse signal during the operation switching by the software switching unit 14, the multivibrator 21 of the pulse width control unit 20 switches the software. Since the long pulse width signal corresponding to the pulse signal applied from the unit 14 is output to the redundancy control section 11, the redundancy control section 11 even though the capacitors C3 and C4 absorb a part of the corresponding pulse signal. The pulse signal can be sufficiently input to the side, and the software can be switched over.

As described above, the present invention prevents malfunction due to chattering when an operation state signal and a hardware state signal are exchanged between the redundant circuit boards in the redundant network synchronizer clock receiving circuit, so that the network synchronizer clock receiving circuit has a stable duplication operation. Will be

Claims (2)

A relative board state detection unit 10 for detecting a relative operation state signal and a relative hardware state signal applied from the opposite circuit board and outputting corresponding detection information; A reset switch switching unit 12 for outputting corresponding reset switch switching information when a reset switch for instructing to operate the network synchronizer clock receiving circuit as a slave board is input; A hardware failure detection unit 13 for detecting whether a failure occurs in each circuit unit provided in the network synchronizer clock receiving circuit and outputting corresponding failure detection information; A software switching unit 14 for outputting operation switching information applied through the terminal; The duplex operation of the network synchronizer clock receiving circuit is controlled in accordance with information supplied from the counter board state detection unit 10, the reset switch switching unit 12, the hardware failure detection unit 13, and the software switching unit 14. Its counterpart is used with its own hardware status signal to indicate whether its own control status signal is installed or not, and whether or not its controlled synchronism clock receiver circuit is installed. In a network synchronizer clock receiving circuit having a redundancy control (part 1) outputted to the circuit board side, the long pulse width signal corresponding to the pulse signal applied from the software switching unit 14 is duplicated. A pulse width control unit 20 outputting to the control unit side 11; A first capacitor connected to a first signal input terminal of the counter board state detection unit 10 and a second terminal grounded to absorb a chattering signal mixed with an operation state signal applied from the counter circuit board (C3); A second capacitor connected to a second signal input terminal of the counter board state detection unit 10 and a second terminal grounded to absorb a chattering signal mixed with a hardware state signal applied from the counter circuit board; And (C4). A network synchronizer clock receiving circuit comprising a switch. According to claim 1, wherein the pulse width control unit 20 performs the oscillation operation when a signal is applied from the software switching unit 14 to output a long pulse width signal to the redundancy control unit 11 side A synchronizer clock receiving circuit of an exchanger comprising a vibrator (21).