JPH08263436A - Data transfer device - Google Patents

Abstract

PURPOSE: To prevent a data error by preventing crosstalk from being superimposed at the timing of latch by driving the operation clock of a data transfer circuit part and the system clock of a CPU control part corresponding to the same clock signal. CONSTITUTION: This device is provided with a data transfer circuit part 1 for inputting a clock for transfer data and transferring data based on this clock signal and a CPU control part 2 for controlling the data transfer of this data transfer circuit 1. Then, the operation clock of the data transfer circuit part 1 and the system clock of the CPU control part 2 are driven by using the same clock signal. Therefore, the crosstalk exerted from the system bus of a CPU onto the transfer data is synchronously superimposed. Thus, the latch error of transfer data can be suppressed at a minimum and the influence of crosstalk at the latch timing of transfer data can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device composed of a CPU.

[0002]

2. Description of the Related Art Conventionally, a microcomputer (CPU)
In the data transfer device that controls the data transfer circuit section using the, the system clock of the CPU is supplied from the clock oscillator in the CPU board. On the other hand, the data transfer section operates by a clock supplied from the outside.
Therefore, the system bus in the CPU and the transfer data bus operate completely asynchronously.

[0003]

However, as the CPU speed has increased in recent years, crosstalk may occur from the system bus of the CPU to the transfer data bus. This crosstalk has a drawback that it may cause a data error when it is superimposed on the transfer data at the timing of latching the transfer data.

An object of the present invention is to provide a data transfer device for preventing the data error by preventing the superposition of the crosstalk at the latch timing in order to solve the above conventional problems. It is in.

[0005]

According to the invention of claim 1 of the present application, as shown in the block diagram of the principle of the invention of FIG. 1, a data transfer clock is input and data transfer is performed based on the clock signal. The circuit unit 1 and the CPU control unit 2 that controls the data transfer of the data transfer circuit unit 1 are included. The operation clock of the data transfer circuit unit 1 and the system clock of the CPU control unit 2 are driven by using the same clock signal.

According to a second aspect of the present invention, a plurality of clock signals, for example, a transfer data clock 0, a transfer data clock 1 and a clock switching signal are input as shown in the block diagram of the principle of the invention of FIG. It is characterized by having a clock switching unit 3 for selecting a clock signal for driving the data transfer circuit unit 1 and the CPU control unit 2 from a plurality of clock signals.

Further, according to the invention of claim 3 of the present application, as shown in the block diagram of the principle of the invention of FIG. 3, the clock switching unit 3 inputs the input clocks, that is, the transfer data clock 0 and the clock 1 from the outside. A masking unit for masking based on the switching signal and a selecting unit (S
EL) and. Further, it has a clock switching control unit 4 for masking the clock signal by the masking unit for a predetermined time based on the clock switching signal and thereafter switching the clock signal by the selecting unit.

According to the invention of claim 4 of the present application, as shown in the block diagram of the principle of the invention of FIG. 4, when the clock switching signal is input in addition to the clock switching portion 3, the C of the CPU control portion 2 is inputted.
It has a halt control unit 5 that suspends the PU and outputs a clock switching signal to the clock switching unit 3 after confirming the suspension.

Further, the invention of claim 5 of the present application, as shown in the block diagram of the principle of the invention of FIG. 5, has a clock loss detecting section 6 for detecting interruption of the clock signal switched by the clock switching section 3, When the disconnection detection unit 6 detects the interruption of the clock, a switching signal is output to the clock switching unit 3 to switch to the other clock signal.

Further, as shown in the block diagram of the principle of the invention of FIG. 6, the invention of claim 6 of the present application has the individual clock breakage detecting section 7 for detecting the breakage for each input clock, and is not cut off. The clock signal or the clock signal in the device is selected by the clock switching unit 3.

According to the invention of claim 7 of the present application, as shown in the block diagram of the principle of the invention of FIG. 7, the clock signal selected by the clock switching unit 3 is input as a reference signal, and the phase lock is performed based on the reference signal. And a clock signal is supplied from the phase control oscillator 8 to the data transfer circuit unit 1 and the CPU control unit 2.

[0012]

According to the invention of claim 1 of the present application having such a feature, since the CPU control unit 2 and the data transfer circuit unit 1 use the same clock, the cross effect of the system bus of the CPU on the transfer data. The talk is synchronized and superimposed. Therefore, the influence of crosstalk at the latch timing of transfer data can be avoided. In the invention of claim 2, the transfer data clock has a plurality of systems, and the clock selected from the clocks is input to the data transfer circuit unit 1 and the CPU control unit 2. Further, in the invention of claim 3, at the time of clock switching, the transfer data clock is masked once in synchronization with the clock,
The switching signal is output in synchronization with the switched clock signal so that the masking of the switched clock signal is released. In this way, the clocks can be switched without any disturbance of the clock waveform or whiskers. Further, in the invention of claim 4, the CPU is temporarily stopped by the clock switching signal, and the clock is switched after the stop is confirmed. According to the fifth aspect of the present invention, it is detected whether or not the selected clock is cut off, and if cut off, a clock signal different from that clock is selected. Therefore, it is possible to autonomously select and change the clock of another system, and the operation of the CPU can be restarted in the shortest time. According to the invention of claim 6, whether or not each clock is individually cut off is detected, and when the clock is cut off, the clock which is not cut off or the internal clock is automatically selected so that the operation of the CPU is not stopped. I have to. According to the invention of claim 7, the phase control oscillator 8 using the selected clock as the reference signal is used, and this oscillation signal is used as the clock signal.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a specific embodiment of the data transfer device according to the present invention will be described with reference to the drawings. FIG. 8 is a block diagram showing a detailed configuration of a first embodiment embodying the inventions of claims 1, 2, and 3 of the present invention. In this embodiment, 2
4M data transfer device, that is, a data transfer device for receiving and transmitting 24 MHz serial data. In the figure, the data transfer circuit unit 1 comprises an S / P conversion unit 1a and a P / S conversion unit 1b. This S / P converter 1a
Receives the received 24MHz serial reception transfer data as an input, converts it to a parallel signal, and outputs 8bit 3MHz
It is an S / P converter that receives the received signal. Further, the S / P converter 1a has a function of extracting alarm information multiplexed on the data and transferring it to the system bus of the CPU. In addition, the transmission data to be transmitted from the data transfer device is 3M.
If the parallel data of Hz and 8 bits is used, this data is input to the P / S conversion unit 1b. This P / S converter 1
In b, the input signal is converted into a serial signal based on the input clock signal, and is output as 24 MHz transmission transfer data. It also has a function of inserting an alarm applied from the CPU system bus into the transfer data. By the way, the CPU 2a, the memory 2b, and the hard register 2c are connected to the CPU system bus as the CPU control unit 2 for controlling them.

Next, the clock switching unit 3 and the clock switching control unit 4 for switching the clock will be described. This data transfer device selects clock 0 and clock 1 for data transfer according to the transfer rate. The clock 0 and the clock 1 are input to the AND circuits 3a and 3b of the clock switching unit 3, respectively. The clock switching unit 3 selects either one of the clocks based on the switching signal, and the switching signal is input to the AND circuits 3a and 3b. The AND circuits 3a and 3b form a mask unit that masks one clock, and the output of the AND circuit 3a and 3b is transmitted through the OR circuit 3c, which is a selection unit, to the S / P converter 1a,
It is input as a clock to the P / S conversion unit 1b and the CPU 2a.

In the clock changeover control unit 4, one end of the changeover switch SW is connected to the power supply end via a pull-up resistor, the output of which is input to the flip-flop 4a and further connected to the inverter 4b. This flip-flop 4
Reference character a denotes a series connection of D-type flip-flops, and its Q output has a flip-flop 4c and an AND circuit 4a.
It is input to d and. The flip-flop 4c is also a cascade connection of D-type flip-flops, and its Q output is connected to the other input terminal of the AND circuit 4d.
The transfer data clock 0 is supplied to these flip-flops 4a and 4c as a clock signal via an inverter 4e. On the other hand, flip-flops 4f and 4g in which D-type flip-flops are cascaded are cascade-connected to the inverter 4b, and the respective Q output terminals are input to the AND circuit 4h. The transfer data clock 1 is connected to the clock input terminals of the flip-flops 4f and 4g through an inverter 4i.

Next, the operation of this embodiment will be described.
When the clock 1 is selected instead of the clock 0 for transfer data, the clock switch SW is turned from OFF to ON. Then, the L level signal is input to the flip-flop 4a, and after two clocks, the flip-flop 4c
Is also entered. Therefore, when the output of the flip-flop 4c becomes L level, the output of the AND circuit 4d and the output of the AND circuit 3a also become L level and the clock 0 is masked. On the other hand, the L level output of the clock changeover switch SW is inverted by the inverter 4b to be flip-flops 4f, 4f.
Since they are added to g, they are delayed by 2D, and after 4D, the output of the AND circuit 4h becomes H level. This output is input to the AND circuit 3b, and a signal synchronized with the data transfer clock 1 is output. Therefore, it is possible to switch from the clock 0 system to the clock 1 system without causing disturbance or whiskers in the clock at the output of the OR circuit 3c.

FIG. 9 is a block diagram showing a second embodiment embodying the invention of claims 1, 2 and 4 of the present application, and the same parts as those of the above-mentioned first embodiment are denoted by the same reference numerals and detailed. The description is omitted. In FIG. 9, the output of the switch SW is input to the halt control unit (HALT control unit) 5. This HAL
The T control unit 5 has a clock changeover switch SW as shown in the figure.
It has a clock switching detector 5a, one end of which is connected to the flip-flop 5b, and a counter 5c for counting clocks. The clock switching detector 5a outputs an L level signal to the RS flip-flop 5d as a reset signal at the time of switching. Further, the flip-flop 5b has one end of the switch SW connected to the input end,
HALT / ACK signal is connected to the clock input terminal. The Q output is input to the clock switching unit 3 as a switching signal. On the other hand, the counter 5c counts a predetermined number of clock signals selected by the clock switching unit 3, for example, 16 pulses, and its overflow output is input as a set signal to the RS flip-flop 5d and reset to the RS flip-flop 5e. It is input as a signal.
The RS flip-flop 5d sends the Q signal to the CPU 2a.
Is output as a HALT bar signal. This output is output as an enable signal for the counter 5c.

Next, the operation of this embodiment will be described.
When the clock switch SW is off and its output is at the H level, it is assumed that the transfer data clock 1 is selected. For example, when the clock changeover switch SW is changed from the off state to the on state, the clock changeover switch S
The output signal of W becomes L level, and the clock switching detector 5a outputs the signal of L level for a short time every time the switching is performed, and resets the RS flip-flop 5d. Therefore, the Q output of the RS flip-flop 5d becomes L level and the CPU
A halt command is issued to 2a. And CPU
When the switching of the halt is completed, the halt completion signal (HALT / ACK signal) is input to the flip-flop 5b. Therefore, the flip-flop 5b outputs the L level which is the output state of the clock switch SW,
The L level is added to the clock switching unit 3. Therefore, the transfer data clock 0 is selected, and this clock is used as the S / P converter 1a, the P / S converter 1b, and the CPU 2.
Input to a. At this time, the HALT / ACK signal is R
In addition to the S flip-flop 5e, the set state is established and the counter 5c is enabled. Therefore, the selected transfer data clock 0 is added to the counter 5c, and the counter 5c starts counting. And, for example, 1
When 6 counts are counted, the overflow output is RS
The flip-flop 5d is set and the halt of the CPU 2a is stopped. At the same time, RS flip-flop 5
e is reset and the operation of the counter 5c is stopped. Therefore, the CPU 2a returns to the normal state after the stop command is released a predetermined time after the stop is released.

Next, a third embodiment embodying the inventions of claims 5 and 6 of the present application will be described. FIG. 10 is a block diagram showing the configuration of the third embodiment of the present invention. The same parts as those in the first and second embodiments described above are designated by the same reference numerals and detailed description thereof will be omitted. The clocks 0 and 1 for transfer data are connected to the clock switching circuit 3d that switches the clocks, and are further input to the clock break detection units 7a and 7b. The clock break detection unit 7a is composed of a monostable multivibrator (MM), detects that the transfer data clock 1 is cut off, and outputs a detection signal to the clock switching control unit 7c when cut off. Similarly, the clock loss detection unit 7b is also composed of a monostable multivibrator, detects the interruption of the transfer data clock 0, and its detection output is input to the clock switching control unit 7c. On the other hand, the clock switching control unit 7c outputs a switching signal to the clock switching circuit 3d when the currently selected clock is cut off, and when the detection signals are input from both clock loss detection units 7a and 7b, the clock switching circuit 7d. It is output to 3e. In this clock switching circuit 3e, the switching signal of the clock switching circuit 3d is input to one input end, and an internal clock signal different from this is input to the other input end. In addition, the CPU reset signal generation unit 7d is configured such that the CPU reset signal generation unit 7d keeps the CPU for a predetermined time every time the clock is switched by the clock switching control unit 7c.
A reset signal for resetting 2a is generated.

Next, the operation of this embodiment will be described.
During operation, either the transfer data clock 0 or 1 is selected by the clock switching circuits 3d and 3e, and C
It is input to the PU 2a, the S / P converter 1a, and the P / S converter 1b. Now, the selected transfer data clock 1
When the clock is cut off, the clock break detection unit 7a detects the cut of the clock and gives an output to the clock switching control unit 7c. Therefore, the switching signal is input to the clock switching unit 3d from the clock switching control unit 7c and switched to the transfer data clock 0. At this time, the CPU 2a is reset by the CPU reset signal generator 7d for a certain period of time, and then starts operating. Therefore, C due to clock abnormality
The malfunction of the PU can be prevented. When the two clocks are cut off at the same time, the internal clock 3f is selected.

Next, a fourth embodiment embodying the invention of claim 7 of the present application will be described. FIG. 11 is a block diagram showing the configuration of the fourth embodiment. The same parts as those in the above-mentioned embodiments are designated by the same reference numerals and detailed description thereof will be omitted. In the figure, clock 0 and clock 1 for transfer data are input to the PLO unit 8 via the clock switching unit 3. This PL
The O unit 8 is a phase control oscillator, which stably oscillates a clock having a constant relationship with the input clock,
The data is output to the conversion unit 1a, the P / S conversion unit 1b and the CPU 2a. Therefore, even if an abnormality occurs in the input clock, a normal clock can be generated and added to each unit. Also, if an abnormality occurs during clock switching, PL
Since the clock is supplied from the O unit 8 to each unit, the CPU 2
A will not cause a malfunction. Further, even if both the input clocks are in the disconnected state, the PLO unit 8 outputs the data, so that the CPU 2a can be operated without causing a malfunction.

[0022]

As described above in detail, according to the present invention, since the clock of the CPU control unit and the clock of the data transfer circuit unit are common, the cross effect of the system bus of the CPU on the transfer data. It is possible to synchronize the talk, and it is possible to obtain the effect that the latch miss of the transfer data can be suppressed to the minimum. Further, in the inventions of claims 2 and 3, since a plurality of clocks are switched through the clock switching section, the data transfer device and the CPU control section can be operated with arbitrary clocks. Further, in the inventions of claims 3 and 4, the malfunction of the CPU can be prevented even when the clocks are switched, and the clocks can be surely switched. Further, in the inventions of claims 5 and 6 of the present application, when the clock is cut off, it is possible to automatically switch to the other clock, and in claim 6, when both clocks are cut off, it is automatically switched to the internal clock. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an inventive principle of claim 1 of the present application.

FIG. 2 is a block diagram showing the configuration of the invention principle of claim 2 of the present application.

FIG. 3 is a block diagram showing a configuration of an inventive principle of claim 3 of the present application.

FIG. 4 is a block diagram showing a configuration of an inventive principle of claim 4 of the present application.

FIG. 5 is a block diagram showing a configuration of an inventive principle of claim 5 of the present application.

FIG. 6 is a block diagram showing a configuration of an inventive principle of claim 6 of the present application.

FIG. 7 is a block diagram showing a configuration of an inventive principle of claim 7 of the present application.

FIG. 8 is a block diagram showing a configuration of a data transfer device according to a first embodiment of the data transfer device of the present invention.

FIG. 9 is a block diagram showing the configuration of a data transfer device according to a second embodiment of the data transfer device of the present invention.

FIG. 10 is a block diagram showing the configuration of a data transfer device according to a third embodiment of the data transfer device of the present invention.

FIG. 11 is a block diagram showing the configuration of a data transfer device according to a fourth embodiment of the data transfer device of the present invention.

[Explanation of symbols]

 1 data transfer circuit section 1a S / P conversion section 1b P / S conversion section 2 CPU control section 2a CPU 2b memory 2c hard register 3 clock switching section 4 clock switching control section 5 HALT control section 6 clock failure detection section 7 individual clock failure Detection unit 7a, 7b Clock loss detection unit 7c Clock switching control unit 7d CPU reset signal generation unit 8 PLO unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical display location G06F 15/16 330 G06F 1/04 340D (72) Inventor Toshiyuki Sakai Nakada Ward, Kanagawa Prefecture Address 1015, inside Fujitsu Limited (72) Inventor, Aya Suzuki, Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa 1015 Address, inside Fujitsu Limited

Claims (7)

[Claims] 1. A data transfer circuit unit that receives a clock signal and transfers data based on the clock signal, and a CPU control unit that controls data transfer of the data transfer circuit unit. A data transfer device, comprising: driving the operation clock of the data transfer circuit unit and the system clock of the CPU control unit using the same clock signal. 2. A clock switching unit for inputting a plurality of clock signals and a clock switching signal and selecting a clock signal for driving the data transfer circuit unit and the CPU control unit from the plurality of clock signals. The data transfer device according to claim 1. 3. The clock switching unit masks an input clock based on a control signal from the outside, and a selection unit to which an output of the mask unit is input.
The data transfer device, based on the clock switching signal, masks the clock signal by the masking unit in synchronization with the selected clock signal, and at the same time by the selecting unit in synchronization with the switched signal. 3. The data transfer device according to claim 2, further comprising a clock switching control unit that switches clock signals. 4. The data according to claim 2, further comprising: a halt control unit that suspends the CPU based on the clock switching signal and outputs the clock switching signal to the clock switching unit after confirming the suspension. Transfer device. 5. A clock break detection unit that detects a break of the clock signal switched by the clock switch unit, and switches to the other clock signal when the clock break is detected by the clock break detection unit. The data transfer device according to claim 2, wherein 6. An individual clock disconnection detection unit for detecting the interruption for each input clock, and a clock signal which is not interrupted and a clock signal in the apparatus are selected by the clock switching unit. The data transfer device according to claim 2. 7. A clock signal selected by the clock switching unit is input as a reference signal, and a phase control oscillator having a phase locked on the basis of the reference signal is provided. The phase control oscillator includes the data transfer circuit unit and the CPU. The data transfer device according to claim 2, wherein a clock signal is supplied to the control unit.