JPS6251013B2 - - Google Patents

Info

Publication number
JPS6251013B2
JPS6251013B2 JP54100706A JP10070679A JPS6251013B2 JP S6251013 B2 JPS6251013 B2 JP S6251013B2 JP 54100706 A JP54100706 A JP 54100706A JP 10070679 A JP10070679 A JP 10070679A JP S6251013 B2 JPS6251013 B2 JP S6251013B2
Authority
JP
Japan
Prior art keywords
clock distribution
clock
distribution system
switching
distribution board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54100706A
Other languages
Japanese (ja)
Other versions
JPS5625847A (en
Inventor
Yoichi Ito
Satokazu Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP10070679A priority Critical patent/JPS5625847A/en
Publication of JPS5625847A publication Critical patent/JPS5625847A/en
Publication of JPS6251013B2 publication Critical patent/JPS6251013B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0079Receiver details
    • H04L7/0083Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)

Description

【発明の詳細な説明】 本発明はPCM端局装置における現用系のクロ
ツク分配系の障害を検知し、予備系に切り替える
クロツク分配系切替方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock distribution system switching system for detecting a failure in a working clock distribution system in a PCM terminal station and switching to a protection system.

第1図はクロツク分配系切替方式の従来例を示
す。図中1は端局装置、2は端局装置1のクロツ
ク源(DCS)で、クロツク源2から供給される
基本クロツクは、端局装置1内の現用系クロツク
分配盤3及び予備系クロツク分配盤4に入る。ク
ロツク分配盤3,4は同一の回路で、通常は現用
系クロツク分配盤3が用いられる。クロツク分配
盤3から出た各種クロツクは、スイツチ5を経て
各システム6,7,…,nへ供給される。ここで
各システム6,7,…,nは同一構成のものとす
る。現用系クロツク分配盤3に障害を生じた場合
には、監視回路Aによつて切替用制御信号SA
スイツチ5を駆動し予備系クロツク分配盤4へ切
り替えられ、予備系クロツク分配盤4から出た各
種クロツクが各システム6,7,…,nへ供給さ
れる。
FIG. 1 shows a conventional example of a clock distribution system switching system. In the figure, 1 is the terminal device, 2 is the clock source (DCS) of the terminal device 1, and the basic clock supplied from the clock source 2 is distributed to the working clock distribution board 3 and the standby clock distribution in the terminal device 1. Enter board 4. The clock distribution boards 3 and 4 have the same circuit, and the working clock distribution board 3 is normally used. Various clocks output from the clock distribution board 3 are supplied to each system 6, 7, . . . , n via a switch 5. Here, each system 6, 7, . . . , n has the same configuration. When a failure occurs in the active system clock distribution board 3, the switching control signal S A is sent by the monitoring circuit A to the switch 5 to switch to the backup system clock distribution board 4, and the clock is transferred from the backup system clock distribution board 4. The output various clocks are supplied to each system 6, 7, . . . , n.

第2図はクロツク分配系切替方式の別の従来例
で、第1図と同符号のものは同一物を示す。クロ
ツク分配盤は先の従来例と同様二重化され、現用
系クロツク分配盤3に障害を生じた場合は監視回
路Aの働きによつて切替用制御信号SAがスイツ
チ5を駆動し、予備系クロツク分配盤4へ切り替
える。クロツク分配盤3,4内はさらにクロツク
受信部x3,x4とタイミングパルス発生盤y3,y4
にわかれている。クロツク受信部x3,x4の動作
は、第1図におけるクロツク分配盤3,4と同じ
である。タイミングパルス発生盤は、第1図の場
合には各システム6,7,…,nがそれぞれ持つ
ていたものであるが、同期端局1内に於ては送
信・受信のクロツクが同期しているので、各種タ
イミングパルスはすべてのシステムで共通のもの
を使用することが可能であるため、クロツク分配
盤3,4内におさめて全システムに共通にしたも
のである。クロツク源2から来た基本クロツク
は、クロツク分配盤3,4に入り、ここで各種タ
イミングパルスが作られ、スイツチ5を経て各シ
ステム6,7,…,nに供給される。
FIG. 2 shows another conventional example of a clock distribution system switching system, in which the same reference numerals as in FIG. 1 indicate the same components. The clock distribution board is duplicated as in the previous example, and if a failure occurs in the active system clock distribution board 3, the switching control signal S A drives the switch 5 by the function of the monitoring circuit A, and the backup system clock is switched on. Switch to distribution board 4. The clock distribution boards 3 and 4 are further divided into clock receiving sections x 3 and x 4 and timing pulse generation boards y 3 and y 4 . The operation of the clock receivers x 3 and x 4 is the same as that of the clock distribution boards 3 and 4 in FIG. In the case of Fig. 1, each system 6, 7, ..., n has a timing pulse generator, but in the synchronous terminal station 1, the transmitting and receiving clocks are synchronized. Since the various timing pulses can be used in common in all systems, they are stored in the clock distribution boards 3 and 4 and made common to all systems. The basic clock coming from the clock source 2 enters a clock distribution board 3, 4, where various timing pulses are generated and supplied via a switch 5 to each system 6, 7, . . . , n.

ところで監視回路は、クロツク分配盤から各シ
ステムに供給されるすべてのクロツクまたはタイ
ミングパルスを監視しなくてはならない。どれか
1つのクロツクまたはタイミングパルスが異常を
来たしても、全システムに影響が及ぶためであ
る。この監視に必要なハードウエア量はかなり多
く、とくに第2従来例のようにタイミングパルス
発生盤を全システムに共通にした場合には膨大な
ものとなる。
However, the monitoring circuit must monitor all clock or timing pulses supplied to each system from the clock distribution board. This is because even if any one clock or timing pulse becomes abnormal, the entire system will be affected. The amount of hardware required for this monitoring is quite large, especially when the timing pulse generator is made common to the entire system as in the second conventional example.

従つて本発明は従来の技術の上記欠点を改善す
るもので、その目的は簡単な構成でクロツク分配
系の障害を検出し現用系から予備系への切り替え
を制御するクロツク分配系切替方式を提供するこ
とにある。この目的を達成するための本発明の特
徴は、 各種クロツクを第1クロツク分配系を介し複数
のシステムに供給し、該第1クロツク分配系のク
ロツクの障害に対応して切替スイツチを動作させ
ることにより自動的に第2クロツク分配系に切り
替え、該第2クロツク分配系からクロツクを各シ
ステムに供給するPCM端局装置において、第1
クロツク分配系のクロツクの障害に応じて複数の
システムにおいて発生する同一内容の警報を検出
し、該警報が上記複数のシステムの全てについて
生じたときに切替制御信号を発生させ切替スイツ
チを動作させることにより第2クロツク分配系に
切り替えるごときクロツク分配系切替方式にあ
る。
SUMMARY OF THE INVENTION Therefore, the present invention aims to improve the above-mentioned drawbacks of the prior art, and its purpose is to provide a clock distribution system switching system that detects failures in the clock distribution system and controls switching from the active system to the standby system with a simple configuration. It's about doing. A feature of the present invention for achieving this object is to supply various clocks to a plurality of systems via a first clock distribution system, and to operate a changeover switch in response to a failure of a clock in the first clock distribution system. In the PCM terminal equipment that automatically switches to the second clock distribution system and supplies clocks to each system from the second clock distribution system, the first
Detecting alarms with the same contents occurring in a plurality of systems in response to a clock failure in a clock distribution system, and generating a switching control signal to operate a changeover switch when the alarm occurs in all of the plurality of systems. This is a clock distribution system switching method in which the clock distribution system is switched to the second clock distribution system.

以下図面により実施例を説明する。 Examples will be described below with reference to the drawings.

第3図は本発明によるクロツク分配系切替方式
の第1実施例で、端局装置1のクロツク源2は現
用系クロツク分配盤3及び予備系クロツク分配盤
4に接続され、クロツク分配盤3,4は夫々切替
スイツチ5を介し各システム6,7,…,nに接
続される。切替スイツチ5は、現用系クロツク分
配盤3のクロツク異常時に各システム6,7,
…,nで発生する警報を入力とするAND回路8
a,8bと該AND回路8a,8bの出力を入力
とするOR回路9を介し得られた出力SAによつて
制御され、現用系クロツク分配盤3のクロツク異
常時には、予備系クロツク分配盤4に各システム
6,7,…,nが接続されるごとく構成される。
なお、本実施例においては、タイミングパルス発
生盤は各システムが夫々持つているものとする。
FIG. 3 shows a first embodiment of the clock distribution system switching system according to the present invention, in which the clock source 2 of the terminal equipment 1 is connected to the working system clock distribution board 3 and the standby system clock distribution board 4, and the clock distribution board 3, 4 are connected to each system 6, 7, . . . , n via a changeover switch 5, respectively. The changeover switch 5 switches each system 6, 7,
AND circuit 8 which inputs the alarm generated by ..., n
a, 8b and the outputs of the AND circuits 8a, 8b are controlled by the output SA obtained through the OR circuit 9, and when the clock in the working system clock distribution board 3 is abnormal, the clock is sent to the standby system clock distribution board 4. Each system 6, 7, . . . , n is configured to be connected.
In this embodiment, it is assumed that each system has its own timing pulse generator.

以上のごとき構成でクロツク分配盤3,4から
各システム6,7,…,nに供給されるクロツク
が、例えば伝送路インタフエース用と符号・復号
器用の2種類であるとする。それらのクロツクに
異常が生じると、各システムからは必ず何らかの
警報が発生する。即ち伝送路インタフエース用ク
ロツクに異常があれば、同期パターンに異常を生
じ、対向局から対局警報asが送られる。また符
号・復号器用クロツクに異常が生じると、各シス
テム6,7,…,nにおける符号・復号器の動作
に異常を生じ、符号・復号器監視回路(図示しな
い)の働きにより符号復号器警報acを発する。
クロツク異常時に発せられるこれらの警報は、全
システム6,7,…,nに共通であるから、警報
s,acをそれぞれ全システムについて論理積を
AND回路8a及び8bでとり、その結果をOR回
路9で論理和とすれば、クロツクの異常を示す信
号SAが得られる。これを切替用制御信号として
切替スイツチ5を駆動すれば、現用系クロツク分
配盤3から予備系クロツク分配盤4への切り替え
が行われる。
Assume that in the above configuration, the clocks supplied from the clock distribution boards 3, 4 to the systems 6, 7, . When an abnormality occurs in these clocks, each system always generates some sort of alarm. That is, if there is an abnormality in the transmission line interface clock, an abnormality will occur in the synchronization pattern, and a game alarm a s will be sent from the opposing station. Furthermore, if an abnormality occurs in the encoder/decoder clock, an abnormality will occur in the operation of the encoder/decoder in each system 6, 7,..., n, and the encoder/decoder monitoring circuit (not shown) will cause an alarm in the encoder/decoder. utter a c .
These alarms issued when the clock is abnormal are common to all systems 6, 7,..., n, so the alarms a s and a c are logically ANDed for all systems.
If the results are obtained by AND circuits 8a and 8b and then logically summed by OR circuit 9, a signal S A indicating a clock abnormality is obtained. When the changeover switch 5 is driven using this as a switching control signal, switching from the active system clock distribution board 3 to the standby system clock distribution board 4 is performed.

以上はクロツクの種類が2種類の場合について
述べたが、他の目的に用いるクロツクが付加され
た場合にも、そのクロツクで動作する機能につい
ては監視と警報が付随するので上述したと同様に
切替スイツチ5を制御することができる。
The above describes the case where there are two types of clocks, but even if a clock used for another purpose is added, monitoring and alarms are attached to the functions operated by that clock, so switching can be performed in the same way as described above. The switch 5 can be controlled.

第4図は本発明によるクロツク分配系切替方式
の第2実施例で、タイミングパルス発生盤を全シ
ステムに共通とした場合における本発明の適用例
を示す。即ち、現用系クロツク分配盤3及び予備
系クロツク分配盤4内には、第2図で述べたごと
くクロツク受信部x3,x4のほかにタイミングパル
ス発生盤y3,y4が設けられる。その他の構成は第
1実施例と同一である。
FIG. 4 shows a second embodiment of the clock distribution system switching system according to the present invention, and shows an example of application of the present invention in a case where the timing pulse generator is common to the entire system. That is, in the active system clock distribution board 3 and the standby system clock distribution board 4, in addition to the clock receiving sections x 3 and x 4 as described in FIG. 2, timing pulse generation boards y 3 and y 4 are provided. The other configurations are the same as the first embodiment.

以上のごとき構成で、クロツク分配盤3から各
システム6,7,…,nに各種タイミングパルス
が供給されることになるが、いずれかのパルスに
異常が生じると各システム内では上述した第1実
施例の場合と同様に警報が発せられる。従がつて
各警報の論理積をAND回路8a,8bで、該回
路8a,8bの出力の論理和をOR回路9でとれ
ば、第1実施例とまつたく同様に切替スイツチ5
を介し現用系クロツク分配盤3から予備系クロツ
ク分配盤4に切り替えを行うことができる。
With the above configuration, various timing pulses are supplied from the clock distribution board 3 to each system 6, 7, ..., n. However, if an abnormality occurs in any of the pulses, the above-mentioned first An alarm is issued as in the embodiment. Therefore, if the AND circuits 8a and 8b take the logical product of each alarm, and the OR circuit 9 takes the logical sum of the outputs of the circuits 8a and 8b, the changeover switch 5 will be activated in the same manner as in the first embodiment.
It is possible to switch from the active clock distribution board 3 to the standby clock distribution board 4 via.

以上説明したように本発明によるクロツク分配
系切替方式においては、各システムにおける監視
及び警報機能が夫々の被監視領域に関係したクロ
ツクに異常があれば必ず動作し対局警報、符号復
号器警報等を発するという性質を利用し、警報が
全システムにあらわれたときにクロツクに異常が
あると判断し、予備系クロツク分配盤に切り替え
るごとくしたので、クロツク監視用の回路を付加
する必要がなく、切替制御のために付加するハー
ドウエア量も極めて少なく構成が簡単になるとい
う利点がある。
As explained above, in the clock distribution system switching system according to the present invention, the monitoring and alarm functions in each system are activated whenever there is an abnormality in the clock related to each monitored area, and issue a game alarm, code/decoder alarm, etc. By taking advantage of this property, when an alarm appears in the entire system, it is determined that there is an abnormality in the clock, and the switch is switched to the standby clock distribution panel.Therefore, there is no need to add a circuit for clock monitoring, and switching control is possible. This has the advantage that the amount of hardware added for this purpose is extremely small and the configuration is simple.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はクロツク分配系切替方式の従来例、第
2図はクロツク分配系切替方式の別の従来例、第
3図は本発明によるクロツク分配系切替方式の第
1実施例、第4図は本発明によるクロツク分配系
切替方式の第2実施例を示す。 1…端局装置、2…クロツク源、3…現用系ク
ロツク分配盤、4…予備系クロツク分配盤、5…
切替スイツチ、6,7〜n…各システム、A…ク
ロツクまたはタイミングパルス監視回路、x3…ク
ロツク受信部(現用系)、x4…クロツク受信部
(予備系)、y3…共通タイミングパルス発生盤(現
用系)、y4…共通タイミングパルス発生盤(予備
系)、SA…切替用制御信号、as…対局警報、ac
…符号復号器警報、8a,8b…AND回路、9
…OR回路。
FIG. 1 shows a conventional example of a clock distribution system switching system, FIG. 2 shows another conventional example of a clock distribution system switching system, FIG. 3 shows a first embodiment of a clock distribution system switching system according to the present invention, and FIG. A second embodiment of the clock distribution system switching system according to the present invention is shown. DESCRIPTION OF SYMBOLS 1... Terminal equipment, 2... Clock source, 3... Working system clock distribution board, 4... Standby system clock distribution board, 5...
Changeover switch, 6, 7 to n...Each system, A...Clock or timing pulse monitoring circuit, x 3 ...Clock receiver (active system), x 4 ...Clock receiver (standby system), y 3 ...Common timing pulse generation board (active system), y 4 ... Common timing pulse generator board (standby system), S A ... switching control signal, a s ... game alarm, a c
...Code decoder alarm, 8a, 8b...AND circuit, 9
...OR circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 各種クロツクを第1クロツク分配系を介し複
数のシステムに供給し、該第1クロツク分配系の
クロツクの障害に対応して切替スイツチを動作さ
せることにより自動的に第2クロツク分配系に切
り替え、該第2クロツク分配系から各種クロツク
を各システムに供給するPCM端局装置におい
て、第1クロツク分配系のクロツクの障害に応じ
て複数のシステムにおいて発生する同一内容の警
報を検出し、該警報が上記複数のシステムの全て
について生じたときに切替制御用信号を発生させ
切替スイツチを動作させることにより第2クロツ
ク分配系に切り替えることを特徴とするクロツク
分配系切替方式。
1. Supplying various clocks to a plurality of systems via a first clock distribution system, and automatically switching to a second clock distribution system by operating a changeover switch in response to a clock failure in the first clock distribution system; A PCM terminal device that supplies various clocks to each system from the second clock distribution system detects an alarm with the same content occurring in multiple systems in response to a clock failure in the first clock distribution system, and A clock distribution system switching method characterized in that, when a clock distribution system occurs in all of the plurality of systems, a switching control signal is generated and a changeover switch is operated to switch to a second clock distribution system.
JP10070679A 1979-08-09 1979-08-09 Change-over system of clock distribution system Granted JPS5625847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10070679A JPS5625847A (en) 1979-08-09 1979-08-09 Change-over system of clock distribution system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10070679A JPS5625847A (en) 1979-08-09 1979-08-09 Change-over system of clock distribution system

Publications (2)

Publication Number Publication Date
JPS5625847A JPS5625847A (en) 1981-03-12
JPS6251013B2 true JPS6251013B2 (en) 1987-10-28

Family

ID=14281125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10070679A Granted JPS5625847A (en) 1979-08-09 1979-08-09 Change-over system of clock distribution system

Country Status (1)

Country Link
JP (1) JPS5625847A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921156A (en) * 1982-07-27 1984-02-03 Pioneer Electronic Corp Lock detecting system of clock generating pll of digitally modulated signal reader

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS516408A (en) * 1974-07-05 1976-01-20 Hitachi Ltd
JPS5214303A (en) * 1976-07-29 1977-02-03 Nec Corp Synchronization error detection method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS516408A (en) * 1974-07-05 1976-01-20 Hitachi Ltd
JPS5214303A (en) * 1976-07-29 1977-02-03 Nec Corp Synchronization error detection method

Also Published As

Publication number Publication date
JPS5625847A (en) 1981-03-12

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