JPH09292928A - Clock signal source monitoring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a monitoring device by constituting the monitoring device detecting the abnormality of a clock signal source of only a digital circuit in a system with plural clock signal source. SOLUTION: Clock signals from the clock signal sources 1 to 3 are given to counters 4 to 6 respectively as clear signals, clock signals from the clock signal sources 1 and 2 are given respectively to the counters 5 and 4 as clear signals and clock signals from the clock signal source 1 are given to a counter 6 a count input. Consequently, when one of the clock signal is broken, a count value goes up to a set value so that an alarm signals is outputted. In addition just after supplying a power source, a counting value is set to be in an alarming state by means of a preset signal from a counting value setting part. Thereby, as the alarm signal is not eliminated at the time of supplying the power source even when plural clock signal sources are broken, the fault can be detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for monitoring the normality of a clock signal source in a system having a plurality of clock signal sources as necessary for failure monitoring.

[0002]

2. Description of the Related Art Some communication systems and control systems include
Some require multiple clock signal sources. Some communication devices, depending on the transmission line speed, for example, 6MHz,
Three types of clock signal sources for respectively generating clock signals of 1.5 MHz and 2 MHz are provided, and these clock signal sources are mounted on a printed board and are detachably provided as a clock unit in the apparatus main body. In order to prevent accidents in the system as a whole, in the above system, it is monitored whether or not each clock signal source is operating normally, that is, whether or not the clock is disconnected.

FIG. 6 shows a conventional method for monitoring clock loss.
As shown in FIG. 1, a method is known in which the clock signals from the clock signal sources 1 to 3 are input to the monostable multivibrators M1 to M3. As another method, as shown in FIG. 7, a clock signal of a specific clock signal source, for example, the clock signal source 1 is given to the counter units CA and CB as count inputs, and the other clock signal sources 2 and 3 are supplied to the counter unit CA. , CB, and the clock signal of the clock signal source 1 is input to the monostable multivibrator M1. In the method of FIG. 7, when the count value of the counter unit CA (CB) exceeds a certain value, it is determined that the clock signal source CA (CB) that has input the clear signal is out of clock.

[0004]

However, since the method of FIG. 6 uses the monostable multivibrator, it requires a resistor and a capacitor, and it is difficult to put the monostable multivibrator in the gate array. It was an obstacle to miniaturization.

In the method shown in FIG. 7, the counter units CA and C are used.
Although the clock signal sources 2 and 3 can be mutually monitored by B, a monostable multivibrator is still required to monitor a specific clock signal source 1, so it is necessary to replace it with a completely digital circuit. Therefore, it was difficult to downsize.

The present invention has been made under such circumstances, and its purpose is to avoid the use of a monostable multivibrator, and to perform miniaturization by processing all in a digital circuit. An object is to provide a monitoring device for a signal source.

[0007]

SUMMARY OF THE INVENTION The present invention is configured to mutually monitor the abnormality of each clock signal source through a counter section, and the clock signals are respectively input as clear signals from a plurality of clock signal sources. A counter input is provided to each counter unit from a clock signal source that is different from the clock signal source that provides a clear signal to the counter unit, and the count value of the counter unit is cleared due to an abnormality in the clear signal. Instead, a predetermined value is set and an alarm signal is issued.

However, when a plurality of clock signal sources fail at the same time, the abnormality cannot be detected. Therefore, when the power is turned on, the count value setting unit sets the count value of each counter unit to the output state of the abnormality signal. By doing so, even when a plurality of clock signal sources fail, the alarm signal issued when the power is turned on is not released, so that the failure can be detected. Since the probability that a plurality of clock signal sources will fail at the same time during operation is equal to zero, there is no practical problem even if this point is not taken into consideration.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings based on an embodiment of the present invention. FIG.
FIG. 3 is a schematic diagram of a communication device, in which 3 in a clock unit 10 is provided.
Clock signals from one clock signal source 1 to 3, for example 6
Clock signals of MHz, 1.5 MHz, and 2 MHz are given to units A (for example, a transmission unit), B, ... A monitoring device 20 for self-monitoring the clock signal is provided in the clock unit 10.

As shown in FIG. 2, the monitoring device 20 is provided with counter units 4 to 6, and clock signals from the clock signal sources 1 to 3 are respectively input to clear input terminals 4a to 6a of the counter units 4 to 6. It is designed to be captured. Further, the count input terminal 4b of the counter unit 4 receives the clock signal from the clock signal source 2, and the count input terminal 5b of the counter unit 5 receives the clock signal from the clock signal source 1.
The clock signal from the clock signal source 1 is taken into each of the count input terminals 6b of the counter section 6.

Further, the preset input terminals 4c to 6c of the counter units 4 to 6 are adapted to receive the preset signal of the count value setting unit 7 for setting the count value to the value of the alarm signal generation state. The count value setting unit 7 is configured to output a preset signal immediately after the power is turned on. As the counter units 4 to 6, for example, ones that output an alarm signal with a count value of "256" can be used. In this case, the preset signal output from the count value setting unit 7 sets the count value to "256". It becomes a signal for setting.

More specifically, each of the counter units 4 to 6 uses two counters as shown in FIG. For example, in the case of the counter unit 4, two counters 41 and 42 are used, and the count input signal (clock signal from the clock signal source 2) and the preset signal are counters 41 and 42, respectively.
Is entered in both. Further, the clear signal for monitoring (clock signal from the clock signal source 1) is supplied to one counter 41.
To the other counter 42 via the inverter 43.

The output signals of the counters 41 and 42 are input to the OR circuit 44. The reason why the two counters 41 and 42 are combined as the counter unit 4 is that when the clock signal from the clock signal source 1 which is the clear signal for monitoring remains in the “H” level as the disconnection state. Since there are both cases when it becomes "L" level, if there is no counter 42, the counter 41 will be cleared even in an abnormal state where the clock signal remains at "H" level. Since the alarm signal is no longer output, it is possible to detect in any case.

The detection signals of the counter sections 4 to 6 are sent to the control section (not shown) via the OR circuit 8 as an alarm output, and are switched to the standby side when the clock unit has a redundant configuration, for example. Is used as a switching signal.

Next, the operation of the above embodiment will be described. If all the clock signal sources 1 to 3 are normal, the counter units 4 to 6 are cleared by the clock signals from the clock signal sources 1 to 3, and the count values of the counter units 4 to 6 reach the alarm generation state. No, therefore no alarm signal is emitted. However, since the frequency of the clock signal of the count input is different from that of the clock signal of the clear input, the set value that causes the alarm is a set value that does not count up between the pulses of the clock signal of the clear input.

When an abnormality occurs in the clock signal source 1, the output signal of the clock signal source 1 remains in the "H" level state or the "L" state. As described above, in the counter unit 5, the count of the clock signal from the clock signal source 2 does not stop, so that the count value becomes "256" and the alarm signal is output. At this time, the output of the OR circuit 44 is input to the counters 41 and 42 as a counter stop signal, whereby the alarm signal is held. FIG. 4 is a time chart showing this state.

If the clock signal sources 1 and 2 fail at the same time, the count inputs themselves of the counter units 1 and 2 disappear, so that the count-up does not occur and the alarm output cannot be obtained. However, it is unlikely that the two clock signal sources will fail simultaneously in the hundreds of ns. Therefore, it is not actually necessary to consider this case. However, since there is a possibility that both counter units 1 and 2 will fail,
Immediately thereafter, when the counter unit 4 is turned on again by a preset signal from the count value setting unit 7,
The count value of ~ 6 is set to the alarm occurrence state, that is, the value of "256". If this is done, the alarm signal will be released if the clock signal is normal, but if there is a clock outage condition, the alarm signal will continue, so even if multiple clock signal sources are abnormal. , The abnormality can be detected.

In the above, the clock signal sources 1 to 3 and the counter units 4 to 6 may be connected as shown in FIG. This example is different from the configuration of FIG. 2 in that the clock signal of the clock signal source 2 is input to the counter unit 6 as a count signal, and the clock signal of the clock signal source 3 is input to the counter unit 4 as a count signal. . As the counter unit, either an up counter or a down counter may be used, and a unit whose output changes by counting a predetermined number of pulses, such as a shift register, is also included in the counter unit in the present invention.

[0019]

According to the present invention, since the monostable multivibrator is not used, the clock signal source can be monitored only by the digital circuit without using the analog circuit such as the resistor and the capacitor. Therefore, the device of the clock signal source can be incorporated in, for example, a gate array, which is effective for downsizing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an entire clock unit including a clock signal source monitoring device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of a clock signal source monitoring device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a counter section.

FIG. 4 is a time-chart diagram showing the operation of the embodiment of the present invention.

FIG. 5 is a block diagram showing an overall configuration of a clock signal source monitoring device according to another embodiment of the present invention.

FIG. 6 is a block diagram showing an example of a conventional clock signal source monitoring device.

FIG. 7 is a block diagram showing another example of a conventional clock signal source monitoring device.

[Description of Reference Signs] 10 clock unit 20 monitoring device for clock signal source 1 to 3 clock signal source 4 to 6 counter unit 41, 42 counter 7 count value setting unit

Claims (2)

[Claims] 1. A device for monitoring a clock signal from a plurality of clock signal sources to detect an abnormality of the clock signal source, wherein a plurality of counter units are respectively inputted with the clock signals as clear signals from the plurality of clock signal sources. A count input is provided to each counter section from a clock signal source different from the clock signal source that gives a clear signal to the counter section, and the count value of the counter section is not cleared due to an abnormality in the clear signal The clock signal source monitoring device is configured so as to output an alarm signal and mutually monitor the abnormality of each clock signal source through a counter section. 2. The clock signal source according to claim 1, further comprising a count value setting unit for setting the count value of each counter unit to the output state of the alarm signal when the power of the clock signal source is turned on. Monitoring equipment.