JP2006072454A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor capable of rapidly executing data processing while preventing failure of processing in a device applied to a digital camera or viewer in which a clock frequency is changed according the frequency of access to a memory. <P>SOLUTION: A priority order determination circuit 50 selects any one of a plurality of transfer modes. A clock control circuit 36 sets the frequency of an internal clock generated by a clock generator 22 to a frequency corresponding to a selected transfer mode. When an acknowledgement signal S_ACK is outputted from a S_ACK generation circuit 38, data transfer according to the selected transfer mode is executed by a buffer circuit 20 or 28. This data transfer responds to the internal clock. If the transfer mode selected this time is a specific transfer mode for executing data transfer in cooperation with a CPU responding to an external clock, the output timing of acknowledgement signal S_ACK is delayed until the setting operation of the clock control circuit 36 is completed. According to this, data processing can be rapidly executed while avoiding failure of processing. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus that is applied to, for example, a digital camera or a viewer and changes a clock frequency in accordance with the frequency of access to a memory.

An example of a conventional device of this type is disclosed in Patent Document 1. According to this prior art, the operating frequency is set to a low frequency in the standby state and set to the normal frequency in the normal state. As a result, a significant reduction in power consumption and a quick transition from the standby state to the normal state are realized. In the prior art, the clock frequency is not switched in the normal state.
JP 11-3131 A [G06F 1/04]

  However, as a normal processing mode, prepare a mode that executes data processing using only the internal clock and a mode that executes data processing using the internal clock and external clock, and set the frequency of the internal clock to mode. When changing according to the following, the following problems arise.

  That is, in the former mode, even if data processing is started prior to the change of the frequency of the internal clock, the processing does not fail. On the other hand, in the latter mode, if data processing is started before the internal clock frequency is changed, that is, before the internal clock frequency is matched with the external clock frequency, the processing fails.

    SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a data processing apparatus that can prevent processing failure and can execute data processing quickly.

  A data processing apparatus according to the present invention includes a selecting unit that selects one of a plurality of transfer modes, and a transfer that executes data transfer according to the transfer mode selected by the selecting unit in response to an internal clock when a trigger is issued A setting means for setting the frequency of the internal clock to a frequency corresponding to the transfer mode selected by the selection means; a determination means for determining whether the mode selection by the selection means satisfies a predetermined condition; and a determination by the determination means When the result is affirmative, the delay unit delays the trigger issuance timing until the setting operation of the setting unit is completed, and the predetermined condition cooperates with the processor whose transfer mode currently selected by the selection unit responds to the external clock. And a mode condition that the data transfer is a specific transfer mode.

  The selection unit selects any one of a plurality of transfer modes. When the trigger is issued, the data transfer according to the transfer mode selected by the selection unit is executed by the transfer unit. This data transfer is responsive to the internal clock. The setting means sets the frequency of the internal clock to a frequency corresponding to the transfer mode selected by the selection means.

  Whether the mode selection by the selection means satisfies a predetermined condition is determined by the determination means. The delay means delays the trigger issuance timing until the setting operation of the setting means is completed when the determination result of the determination means is affirmative. Here, the predetermined condition includes a mode condition that the transfer mode selected this time by the selection means is a specific transfer mode in which data transfer is executed in cooperation with a processor that responds to an external clock.

  Therefore, when the transfer mode for executing the data transfer in cooperation with the processor is selected, the trigger issue timing is delayed. Data transfer is started after a predetermined frequency relationship is established between the internal clock and the external clock. This avoids processing failures. Further, when a transfer mode that does not require cooperation with the processor is selected, delay processing by the delay means is not performed. The frequency of the internal clock is quickly set to a frequency corresponding to the selected transfer mode. As a result, data processing is performed quickly.

  A data processing apparatus according to a second aspect of the present invention is dependent on the first aspect, and the transfer means includes access means for accessing the memory in a burst transfer mode. Thereby, high-speed access is realized.

  The data processing apparatus according to the invention of claim 3 is dependent on claim 2, and the predetermined condition corresponds to a transfer mode in which the frequency of the internal clock corresponding to the transfer mode selected this time by the selection means is selected by the selection means. The frequency condition is lower than the frequency of the internal clock. Thus, when the frequency of the internal clock is changed in the upward direction, the predetermined condition is not satisfied, and the trigger is not delayed by the delay means.

  In burst transfer, overhead occurs prior to data access. In this overhead time zone, there is no need to establish a predetermined frequency relationship between the internal clock and the external clock. Here, the length of time required for the overhead depends on the frequency of the internal clock. That is, the lower the internal clock frequency, the longer the overhead time. Therefore, the setting means can complete the setting operation before the data access is started, and it is possible to avoid processing failure.

  A data processing device according to a fourth aspect of the present invention is dependent on any one of the first to third aspects, wherein the transfer means includes a generation means for generating a transfer request prior to the data transfer, and the trigger is an approval signal for approving the transfer request. It is.

  According to the present invention, when the transfer mode for executing data transfer in cooperation with the processor is selected, the trigger issue timing is delayed. Data transfer is started after a predetermined frequency relationship is established between the internal clock and the external clock. This avoids processing failures. Further, when a transfer mode that does not require cooperation with the processor is selected, delay processing by the delay means is not performed. The frequency of the internal clock is quickly set to a frequency corresponding to the selected transfer mode. As a result, data processing is performed quickly.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  Referring to FIG. 1, data processing apparatus 10 of this embodiment includes a clock generator 16 that generates an external clock. In response to the external clock output from the clock generator 16, the CPU 14 transfers one frame of image data from the recording medium 12 to the ASIC 18. The transfer speed at this time is 54 MHz, and the transferred image data is stored in the SRAM 20 s forming the buffer circuit 20. Note that one frame of image data has a resolution of, for example, vertical 640 pixels × horizontal 480 pixels.

  The controller 20c forming the buffer circuit 20 gives a write request to the SDRAM control circuit 24 every time a predetermined amount (for example, 64 pixels) of image data is accumulated in the SRAM 20s. When the write request is approved by the SDRAM control circuit 24, the controller 20c sends a predetermined amount of image data stored in the SRAM 20s to the SDRAM control circuit 24 together with control data in which address information and access mode information are described. Output.

  At this time, the internal clock output from the clock generator 22 has a frequency of 54 MHz, and the image data and the control data are given to the SDRAM control circuit 24 at a clock rate of 54 MHz. The SDRAM control circuit 24 writes a predetermined amount of image data at a designated address of the SDRAM 26 in a burst transfer manner. By repeating such a writing operation, one frame of image data is accumulated in the SDRAM 26.

  On the other hand, the controller 28 c provided in the buffer circuit 28 gives a read request to the SDRAM control circuit 24. When the read request is approved by the SDRAM control circuit 24, the buffer circuit 28 provides the SDRAM control circuit 24 with control data in which address information and access mode information are described. The SDRAM control circuit 24 reads a predetermined amount of image data from the designated address of the SDRAM 26 in a burst transfer manner, and transfers the read image data to the buffer circuit 28.

  At this time, the clock generator 22 outputs an internal clock of 108 MHz, and the image data is given to the buffer circuit 28 at a clock rate of 108 MHz. The given image data is stored in the SRAM 28s by the controller 28c. By repeating such a reading operation, the image data stored in the SDRAM 26 is transferred to the buffer circuit 28 by a predetermined amount.

  The video encoder 30 sequentially reads image data from the SRAM 28s, and encodes the read image data into composite image data. The encoded composite image data is converted into a composite image signal which is an analog signal by the D / A converter 32, and the converted composite image signal is output to the LCD monitor 34. As a result, the reproduced image is displayed on the monitor screen.

  A mode in which a predetermined amount of image data is transferred from the buffer circuit 20 to the SDRAM 26 is defined as a “write mode”, and a mode in which a predetermined amount of image data is transferred from the SDRAM 26 to the buffer circuit 28 is defined as a “read mode”. Also, all of the buffer circuits 20 and 28, the SDRAM control circuit 24, the video encoder 30 and the D / A converter 32 forming the ASIC 18 perform processing in synchronization with the internal clock output from the clock generator 22.

  The ASIC 18 is configured as shown in FIG. The operation of the ASIC 18 will be described with reference to FIGS. The controller 20 c of the buffer circuit 20 outputs the write request W_REQ to the priority determination circuit 50, and the controller 28 c of the buffer circuit 28 outputs the read request R_REQ to the priority determination circuit 50.

  The priority determination circuit 50 selects the buffer circuit 20 (that is, the writing mode) or the buffer circuit 28 (that is, the reading mode) according to the priority every time the transfer of the predetermined amount of image data DT is completed. From the priority order determination circuit 50, a selection number SNO. Is output. Selection number SNO. Indicates “1” when the buffer circuit 20 is selected and indicates “2” when the buffer circuit 28 is selected. The generated selection number SNO. Is supplied to buffer circuits 20 and 28, selectors 40, 42 and 44, S_ACK generation circuit 38, and clock control circuit 36.

  Note that the priority determination circuit 50 selects the selection number SNO.2 when there is no subsequent request when the transfer of the predetermined amount of image data DT is completed. Is set to “0”.

  Each of the buffer circuits 20 and 28 has a selection number SNO. Is compared to the identification number assigned to you. When the comparison result indicates “match”, the buffer circuit starts the access operation when the active L acknowledgment signal S_ACK output from the S_ACK circuit 38 falls. When the buffer circuit 20 is selected, control data describing the address information Adrs and the access mode information W is output from the controller 20c, and a predetermined amount of image data DT is output from the SRAM 20s. When the buffer 28 is selected, control data describing the address information Adrs and the access mode information R is output from the controller 28c.

  Each of selectors 40, 42 and 44 has a selection number SNO. The buffer circuit corresponding to is selected. The selector 40 provides access mode information R / W from the selected buffer circuit to the command generation circuit 46, and the selector 42 provides address information Adrs from the selected buffer circuit to the address converter 48. The selector 44 selects the selection number SNO. Indicates "1", the image data DT output from the buffer circuit 20 is applied to the SDRAM 26, and the selection number SNO. When “2” indicates “2”, the image data DT read from the SDRAM 26 is supplied to the buffer circuit 28.

  The command generation circuit 46 generates a command CMND corresponding to the access mode information R / W from the selector 40, and gives the generated command CMND to the SDRAM 26. The address converter 48 converts the address indicated by the address information Adrs from the selector 42 into the real address ADRS of the SDRAM 26, and gives the converted real address ADRS to the SDRAM 26. As a result, the image data DT output from the selector 44 is written to the desired address of the SDRAM 26, or the image data DT directed to the selector 44 is read from the desired address of the SDRAM 26.

  When the writing / reading of the predetermined amount of image data DT is completed, an active H end signal is output from the command generation circuit 46. The end signal END rises in response to the end of writing / reading, and falls when one clock period has elapsed from the rise.

  The clock control circuit 36 selects the selection number SNO. Based on the above, the active C request C54_REQ or C108_REQ is output to the clock generator 22. Selection number SNO. Indicates "1", the request C54_REQ rises and the selection number SNO. Indicates “2”, the request C108_REQ rises.

  The rising timing of the request C54_REQ is the selection number SNO. Indicates “1”, and the rising timing of the request C108_REQ is the selection number SNO. Is the time when one clock period has elapsed since the value of “2” indicates “2”. Further, the request C54_REQ or C108_REQ falls at the timing when the active L acknowledgment signal S_ACK rises.

  The clock generator 22 raises the active H acknowledgment signal C54_ACK in response to the rising edge of the request C54_REQ, and falls the active H acknowledgment signal C54_ACK in response to the falling edge of the request C54_REQ. The clock generator 22 also raises the active H acknowledgment signal C108_ACK in response to the rising edge of the request C108_REQ, and falls the active H acknowledgment signal C108_ACK in response to the falling edge of the request C108_REQ. The approval signal C54_ACK is input to the clock control circuit 36. The approval signal C108_ACK is supplied to the clock control circuit 36 and the S_ACK generation circuit 38.

  The clock generator 22 sets the frequency of the internal clock S_CLK to 54 MHz while the approval signal C54_ACK maintains the H level, and sets the frequency of the internal clock S_CLK to 108 MHz while the approval signal C108_ACK maintains the H level. Then, the frequency of the internal clock S_CLK is set to 27 MHz in a period in which both of the approval signals C54_ACK and C108_ACK are maintained at the L level.

  The S_ACK generation circuit 38 is configured as shown in FIG. In the period A shown in FIG. 4, the S_ACK generation circuit 38 operates in the manner shown in FIG. The acknowledgment signal C108_ACK from the clock generator 22 is given to the access restriction circuit 38a, and the selection number SNO. Is supplied to the access restriction circuit 38a and the access start instruction circuit 38b, and the end signal END from the command generation circuit 46 is supplied to the R terminal of the flip-flop circuit 38d.

  The access start command circuit 38b selects the selection number SNO. Is updated from “0” to “1” or “2”, or the selection number SNO. Is changed between “1” and “2”, the active high start signal STRT is raised for a predetermined tens of clock periods.

  The access restriction circuit 38a selects the selection number SNO. With the approval signal C108_ACK at the H level. When "1" indicates "1", the active H delay signal DLY is raised. That is, for the rise of the delay signal DLY, the mode condition that the transfer mode selected this time is a write mode in which data transfer is executed in cooperation with the CPU 14 and the direction of changing the frequency of the internal clock S_CLK is decreasing ( 108 MHz → 54 MHz) is required. If these two conditions are not satisfied, the delay signal DLY maintains the L level, and if these two conditions are satisfied, the delay signal DLY shifts to the H level.

  Note that the delay signal DLY that has shifted to the H level falls simultaneously with the fall of the approval signal C108_ACK.

  The start signal STRT and the delay signal DLY are applied to the non-inverting input terminal and the inverting input terminal of the AND gate 38c, respectively. When the delay signal DLY is at L level, the output signal AND of the AND gate 38c rises simultaneously with the rise of the start signal STRT. On the other hand, when the delay signal DLY is at the H level, the output signal AND of the AND gate 38c rises simultaneously with the fall of the approval signal C108_ACK. The output signal AND of the AND gate 38c is supplied to the S terminal of the flip-flop circuit 38d.

  The flip-flop circuit 38d raises the output of the Q terminal in response to the rise of the S terminal, and falls the output of the Q terminal in response to the rise of the R terminal. The output of the Q terminal is inverted by the inverter 38e, thereby generating an active L acknowledgment signal S_ACK.

  Therefore, when the transfer mode is changed from the read mode to the write mode (108 MHz → 54 MHz), the approval signal S_ACK falls in response to the fall of the approval signal C108_ACK. On the other hand, when the transfer mode is changed from the write mode to the read mode (54 MHz → 108 MHz), when the write mode is continuous (54 MHz → 54 MHz), or when the read mode is continuous (108 MHz → 108 MHz), the approval signal S_ACK is The signal falls at the same time as the start signal STRT rises.

  Note that the falling approval signal S_ACK rises when the transfer of the predetermined amount of image data DT is completed as described above.

  As can be understood from the above description, the priority determination circuit 50 selects one of a plurality of transfer modes. When the acknowledgment signal S_ACK (trigger) is output from the S_ACK generation circuit 38, the buffer circuit 20 or 28 performs data transfer according to the transfer mode selected by the priority determination circuit 50. This data transfer is in response to the internal clock S_CLK output from the clock generator 22. The clock control circuit 36 sets the frequency of the internal clock S_CLK to a frequency corresponding to the transfer mode selected by the priority determination circuit 50.

  Whether or not the mode selection by the priority determination circuit 50 satisfies a predetermined condition is determined by the access restriction circuit 38a. When the determination result of the access restriction circuit 38a is affirmative, the AND gate 38c delays the output timing of the approval signal S_ACK until the setting operation of the clock control circuit 36 is completed.

  Here, the predetermined condition includes a mode condition that the transfer mode selected this time by the priority determination circuit 50 is a write mode (specific transfer mode) in which data transfer is performed in cooperation with the CPU 14 responding to the external clock. .

  Therefore, when the write mode for executing data transfer in cooperation with the CPU 14 is selected, the output timing of the approval signal S_ACK is delayed. Data transfer is started after the frequency of the internal clock S_CLK is set to 54 MHz. This avoids processing failures. Further, when a read mode that does not require cooperation with the CPU 14 is selected, the issuing timing of the approval signal S_ACK is not delayed. The frequency of the internal clock S_CLK is quickly set to a frequency corresponding to the selected transfer mode. As a result, data processing is performed quickly.

  Further, the predetermined condition is that the frequency of the internal clock S_CLK corresponding to the transfer mode selected this time by the priority determining circuit 50 is lower than the frequency of the internal clock S_CLK corresponding to the transfer mode previously selected by the priority determining circuit 50. The frequency condition is further included. Accordingly, when the frequency of the internal clock S_CLK is changed in the upward direction, the predetermined condition is not satisfied, and the issue of the approval signal S_ACK is not delayed.

  In burst transfer, overhead occurs prior to data access. In this overhead time zone, there is no need to establish a predetermined frequency relationship between the internal clock S_CLK and the external clock. Here, the time length required for the overhead depends on the frequency of the internal clock S_CLK. That is, the lower the frequency of the internal clock S_CLK, the longer the overhead time. Therefore, the clock control circuit 36 can complete the setting operation before the data access is started, and it is possible to avoid the failure of the process.

  In this embodiment, as a condition for raising the delay signal DLY, a frequency condition that the frequency of the internal clock S_CLK is changed in a decreasing direction (108 MHz → 54 MHz) is required, but this frequency condition is omitted. Also good. When the frequency condition is omitted, the delay signal DLY rises also when the frequency of the internal clock S_CLK is changed from 27 MHz to 54 MHz, that is, when the write mode is shifted from the idle state.

It is a block diagram which shows the structure of one Example of this invention. FIG. 2 is a block diagram showing an example of a configuration of an SDRAM control circuit applied to the embodiment in FIG. 1. FIG. 3 is a block diagram illustrating an example of a configuration of an S_ACK generation circuit applied to the embodiment in FIG. 2. FIG. 3 is a timing chart showing a part of the operation of the embodiment in FIG. 2; FIG. 10 is a timing diagram showing another part of the operation of the embodiment in FIG. 2; FIG. 4 is a timing chart showing a part of the operation of the embodiment in FIG. 3;

Explanation of symbols

10 ... Digital camera 14 ... CPU
16, 22 ... Clock generator 18 ... ASIC
20, 28 ... Buffer circuit 24 ... SDRAM control circuit 26 ... SDRAM

Claims (4)

Selection means for selecting any one of a plurality of transfer modes;
Transfer means for executing data transfer according to the transfer mode selected by the selection means in response to an internal clock when a trigger is issued;
Setting means for setting the frequency of the internal clock to a frequency corresponding to the transfer mode selected by the selection means;
Determining means for determining whether or not the mode selection by the selecting means satisfies a predetermined condition; and when the determination result of the determining means is affirmative, issuance timing of the trigger until the setting operation of the setting means is completed With delay means to delay,
The data processing apparatus, wherein the predetermined condition includes a mode condition that a transfer mode selected this time by the selection unit is a specific transfer mode in which the data transfer is executed in cooperation with a processor that responds to an external clock.   2. The data processing apparatus according to claim 1, wherein said transfer means includes access means for accessing the memory in a burst transfer mode.   The predetermined condition further includes a frequency condition that a frequency of the internal clock corresponding to the transfer mode currently selected by the selection unit is lower than a frequency of the internal clock corresponding to the transfer mode selected last by the selection unit. The data processing apparatus according to claim 2, further comprising: The transfer means includes generating means for generating a transfer request prior to the data transfer;
The data processing apparatus according to claim 1, wherein the trigger is an approval signal for approving the transfer request.

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