JP2009163172A - Display system and projector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent image burn-in in a liquid crystal panel. <P>SOLUTION: A display system includes: a liquid crystal panel which forms images; a timing-generating circuit which designates the horizontal position and vertical position of an image formed by the liquid crystal panel; and a time-measuring counter which detects the elapse of a prescribed time length. The timing-generating circuit changes at least either the horizontal position or the vertical position every time the time-measuring counter detects the elapse of a prescribed time length. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display system such as a projector.

  As techniques for preventing image burn-in in a liquid crystal panel, there are known AC driving methods such as a V inversion method, an S inversion method, an H inversion method, and a dot inversion method (for example, Patent Document 1).

Japanese Patent Laid-Open No. 10-73802

  However, even when the polarity of the voltage applied to the pixel portion of the liquid crystal panel is reversed at a predetermined timing by the AC driving method, the same voltage is continuously applied to the same pixel portion in the liquid crystal panel. In some cases, burn-in may occur due to the characteristics of the liquid crystal panel.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention is realized as the following forms or application examples.

  Application Example 1 A display system forms a liquid crystal panel that forms an image, a timing generation circuit that defines a horizontal position and a vertical position of the image formed by the liquid crystal panel, and a timing that detects the passage of a predetermined time length And a counter. Here, every time the time counter detects the passage of the predetermined time length, the timing generation circuit changes at least one of the horizontal position and the vertical position.

  According to the above configuration, the horizontal position and vertical position of the image change every time the time counter detects the passage of the predetermined time, so that the same voltage can be continuously applied to the same pixel portion in the liquid crystal panel. And the likelihood of image burn-in formed is reduced.

  Application Example 2 A display system includes a liquid crystal panel that forms an image, a timing generation circuit that defines a horizontal position and a vertical position of the image formed by the liquid crystal panel, and a scene change of the image according to an image signal. A scene change detector for detecting the accumulated time, and a time counter for measuring the accumulated time and detecting that the measured accumulated time has reached a predetermined time length, wherein the scene change detector detects the scene change And a time counter for initializing the measured accumulated time. Here, every time the time counter detects that the accumulated time has reached the predetermined time length, the timing generation circuit changes at least one of the horizontal position and the vertical position.

  If there is a scene change in the image, the possibility that the same voltage is applied to the same pixel portion of the liquid crystal panel before and after the scene change is reduced. Therefore, in the above application example, when a scene change is detected, the accumulated time measured by the time counter is initialized, so that the horizontal position or vertical position of the image is reduced while reducing the possibility of image burn-in. You can reduce the number of changes.

  Note that the display system of the application example 1 or 2 can also be realized as a projector.

  Hereinafter, an embodiment will be described with reference to the drawings, taking a case where the display system is a projector as an example. In addition, the embodiment shown below does not limit the content of the invention described in the claim at all.

(Embodiment 1)
The display system 1 in FIG. 1 is a projector. Specifically, the display system 1 includes an input terminal 11, a write synchronization generator 12, an A / D converter 13, a frame memory device 14, a read synchronization generator 15, and a D / A converter 16. A timing generation circuit 17, a drive circuit 18, a liquid crystal panel 19, a control unit 22, a light source unit 20, and a projection optical system 21. In another form, the display system 1 may be a direct-view type liquid crystal monitor instead of the projector.

  The input terminal 11 is supplied with an image signal IV1 and synchronization signals (horizontal synchronization signal HS1 and vertical synchronization signal VS1) synchronized with the image signal IV1 from an external device (not shown) such as a personal computer. In the present embodiment, the image signal supplied to the input terminal 11 is an analog RGB signal, but may be a digital signal in other forms. In FIG. 1, the synchronization signal and the image signal IV1 are supplied to the common input terminal 11. However, as long as the image signal IV1 and the synchronization signal are synchronized with each other, they may be supplied to different terminals. .

  The horizontal synchronization signal HS1 and the vertical synchronization signal VS1 supplied to the input terminal 11 are supplied to the write synchronization generator 12. Then, the write synchronization generator 12 generates the dot clock signal DC1 based on the horizontal synchronization signal HS1 among the synchronization signals. The dot clock signal DC1 has a frequency obtained by multiplying the frequency of the horizontal synchronization signal HS1, and represents the dot frequency of the image signal IV1.

  The image signal IV1 supplied to the input terminal 11 is supplied to the A / D converter 13. The A / D converter 13 digitizes the image signal IV1 in synchronization with the dot clock signal DC1, thereby generating an image signal IV2 based on the image signal IV1.

  The image signal IV2 is written into the frame memory device 14 as image data in synchronization with the dot clock signal DC1, the horizontal synchronization signal HS1, and the vertical synchronization signal VS1. The frame memory device 14 includes a DRAM, an address controller, and a DRAM controller (all not shown). The address controller forms an address for designating a storage area in the DRAM based on the dot clock signal DC1, the horizontal synchronization signal HS1, and the vertical synchronization signal VS1. Then, the DRAM controller writes the image signal IV2 as image data in the storage area based on the formed address.

  The read synchronization generator 15 generates a dot clock signal DC2, a horizontal synchronization signal HS2, and a vertical synchronization signal VS2.

  The image data written in the frame memory device 14 is read out as an image signal IV3 in synchronization with the dot clock signal DC2, the horizontal synchronization signal HS2, and the vertical synchronization signal VS2. Specifically, first, the address controller described above forms an address for designating a storage area in the DRAM based on the dot clock signal DC2, the horizontal synchronization signal HS2, and the vertical synchronization signal VS2. Then, the above-described DRAM controller reads image data from the storage area as the image signal IV3 based on the formed address.

  Even if there is a difference between the frequency (dot frequency, horizontal frequency, vertical frequency) of the image signal IV1 output from the external device and the driving frequency of the liquid crystal panel 19 due to the above configuration including the frame memory device 14. The image represented by the image signal IV1 is correctly formed by the liquid crystal panel 19.

  The image signal IV3 output from the frame memory device 14 is supplied to the D / A converter 16. The D / A converter 16 analogizes the image signal IV3 in synchronization with the dot clock signal DC2, and thereby generates an image signal IV4 based on the image signal IV3. Note that the image signal IV4 is synchronized with the dot clock signal DC2, the horizontal synchronization signal HS2, and the vertical synchronization signal VS2. That is, the dot frequency of the image signal IV4 is the same as the frequency of the dot clock signal DC2, the horizontal frequency of the image signal IV4 is the same as the frequency of the horizontal synchronization signal HS2, and the vertical frequency of the image signal IV4 is the vertical synchronization signal VS2. Is the same frequency.

  The timing generation circuit 17 has a function of defining a horizontal position and a vertical position of an image formed by the liquid crystal panel 19. A specific configuration of the timing generation circuit 17 is as follows.

  As shown in FIG. 2, the timing generation circuit 17 includes a horizontal reference signal generator 17a and a vertical reference signal generator 17b.

  Of these, the horizontal reference signal generator 17a outputs a horizontal timing signal HTMG and a clock pulse DLX based on the dot clock signal DC2 and the horizontal synchronization signal HS2. Here, the frequency of the horizontal synchronization signal HS2 and the frequency of the horizontal timing signal HTMG are the same. Further, the horizontal timing signal HTMG is input as a start pulse to a horizontal shift register (not shown) included in the drive circuit 18. The horizontal timing signal HTMG is a reference for timing at which the horizontal shift register starts to sequentially supply data signals (horizontal and vertical effective display periods of the image signal IV4) to a plurality of data lines (not shown) in the liquid crystal panel 19. become. For this reason, the horizontal position of the image on the liquid crystal panel 19 is determined by the horizontal timing signal HTMG. On the other hand, the clock pulse DLX represents each timing at which the horizontal shift register sequentially supplies data signals to the plurality of data lines.

  On the other hand, the vertical reference signal generator 17b outputs a vertical timing signal VTMG and a clock pulse DLY based on the horizontal synchronization signal HS2 and the vertical synchronization signal VS2. Here, the frequency of the vertical synchronization signal VS2 and the frequency of the vertical timing signal VTMG are the same. The vertical timing signal VTMG is input as a start pulse to a vertical shift register (not shown) included in the drive circuit 18. The vertical timing signal VTMG serves as a reference for timing at which the vertical shift register starts to sequentially select a plurality of scanning lines (not shown) in the liquid crystal panel 19. Therefore, the vertical position of the image on the liquid crystal panel 19 is determined by the vertical timing signal VTMG. On the other hand, the clock pulse DLY represents each timing at which the vertical shift register sequentially selects a plurality of scanning lines.

  Returning to FIG. 1, the drive circuit 18 responds to the horizontal timing signal HTMG, the clock pulse DLX, the vertical timing signal VTMG, the clock pulse DLY, and the image signal IV4 from the D / A converter 16. The panel 19 is configured to be driven. When the driving device drives the liquid crystal panel 19, an image corresponding to the image signal IV4 is formed by the liquid crystal panel 19. The method for driving the liquid crystal panel 19 by the driving circuit 18 is understood by those skilled in the art based on the description in Japanese Patent No. 3965875, and therefore will be omitted here. Further, the liquid crystal panel 19 of the present embodiment is a matrix type liquid crystal panel.

  The light source unit 20 includes a lamp 20A and an illumination optical system 20B. With such a configuration, the light source unit 20 generates a light beam. The light beam generated by the light source unit 20 enters the liquid crystal panel 19 forming an image and is spatially modulated by the liquid crystal panel 19. The projection optical system 21 is arranged to project a modulated light beam or a formed image.

  The control unit 22 includes a CPU 23, a RAM 24, a ROM 25, a bus 26 that connects these components so as to communicate with each other, and a CPU access controller (not shown). The RAM 24 is used as a storage area when the CPU 23 executes processing. The ROM 25 stores a program that defines processing executed by the CPU 23. Further, the CPU 23 can access the write synchronization generation unit 12, the frame memory device 14, the read synchronization generation unit 15, and the timing generation circuit 17 through the CPU access controller.

  A “time counter” described later is one of the functions realized by the control unit 22. When the control unit 22 functions as a “time counter”, the control unit 22 repeatedly detects the elapse of the predetermined time length TS. As will be described later, in this embodiment, every time the time counter detects the elapse of the predetermined time length TS, the timing generation circuit 17 is configured to display at least one of the horizontal position and the vertical position of the image formed by the liquid crystal panel 19. change.

  FIG. 3A shows a case where the horizontal position and the vertical position of the image formed by the liquid crystal panel 19 are at the standard positions, respectively. In this case, the phase relationship between the horizontal timing signal HTMG and the horizontal synchronization signal HS2 is set so that the horizontal position of the image formed by the liquid crystal panel 19 becomes the standard position. Similarly, the phase relationship between the vertical timing signal VTMG and the vertical synchronization signal VS2 is set so that the vertical position of the image formed by the liquid crystal panel 19 becomes the standard position.

  FIG. 3B shows a case where the horizontal position of the image is changed. In this case, first, the horizontal reference signal generator 17a in the timing generation circuit 17 delays the phase of the horizontal timing signal HTMG with respect to the horizontal synchronization signal HS2. For example, the horizontal reference signal generator 17a delays the phase of the horizontal timing signal HTMG by one pixel of the image (one period of the dot clock signal DC2) with respect to the horizontal synchronization signal HS2. Then, as shown in FIG. 3B, the horizontal position of the image changes from the standard position.

  Thereafter, the horizontal reference signal generator 17a returns the phase of the horizontal timing signal HTMG to the horizontal synchronization signal HS2 so that the horizontal position of the image returns to the standard position (FIG. 3A). For the purpose of facilitating understanding, in FIG. 3B, the change in the horizontal position of the image is exaggerated from the actual one. Further, FIGS. 3C and 3D described later are similarly exaggerated.

  FIG. 3C shows a case where the vertical position of the image is changed. In this case, first, the vertical reference signal generator 17b in the timing generation circuit 17 delays the phase of the vertical timing signal VTMG with respect to the vertical synchronization signal VS2. For example, the vertical reference signal generator 17b delays the phase of the vertical timing signal VTMG by one scanning line (one period of the horizontal synchronizing signal HS2) of the image with respect to the vertical synchronizing signal VS2. Then, as shown in FIG. 3C, the vertical position of the image changes from the standard position.

  Thereafter, the vertical reference signal generator 17b returns the phase of the vertical timing signal VTMG to the vertical synchronization signal VS2 so that the vertical position of the image returns to the standard position (FIG. 3A).

  FIG. 3D shows a case where both the horizontal position and the vertical position of the image are changed. In this case, first, the horizontal reference signal generator 17a delays the phase of the horizontal timing signal HTMG with respect to the horizontal synchronization signal HS2, and the vertical reference signal generator 17b sets the phase of the vertical timing signal VTMG with respect to the vertical synchronization signal VS2. Delay. Then, as shown in FIG. 3D, both the horizontal position and the vertical position of the image change with respect to the standard position.

  Thereafter, the horizontal reference signal generator 17a returns the phase of the horizontal timing signal HTMG with respect to the horizontal synchronization signal HS2 so that the horizontal position and vertical position of the image return to the respective standard positions (FIG. 3A). The vertical reference signal generator 17b may return the phase of the vertical timing signal VTMG to the vertical synchronization signal VS2.

  With reference to FIG. 4, the flow will be described in more detail by taking as an example a case where the horizontal position of an image changes.

  First, as an initialization process, the timing generation circuit 17 changes the phase of the horizontal timing signal HTMG to the horizontal synchronization signal HS2 so that the horizontal position and the vertical position of the image become standard positions according to the control of the control unit 22, respectively. The phase of the vertical timing signal VTMG is set with respect to the vertical synchronization signal VS2 (step SA0).

  Next, the control unit 22 initializes the variable i. As a result, in the case of FIG. 4, “0” is stored in the variable i (step SA1). Thereafter, the control unit 22 initializes a variable tc indicating the elapsed accumulated time. As a result, in the case of FIG. 4, “0” is stored in the variable tc (step SA2). Then, the control unit 22 increases the value of the variable tc, for example, in units of one second with the passage of time, thereby measuring the accumulated time. Note that the variable i and the variable tc are realized by respective storage areas in the RAM 24.

  Next, the control unit 22 determines whether or not the variable tc (or the accumulated time represented by the variable tc) is equal to or longer than the predetermined time length TS (step SA3). When the variable tc is less than the predetermined time length TS (“No” in step SA3), the control unit 22 repeats step SA3 until the variable tc becomes equal to or greater than the predetermined time length TS.

  When the variable tc is equal to or greater than the predetermined time length TS (step SA3 is “Yes”), the control unit 22 determines whether the variable i is “0” (step SA4). When the variable i is “0” (step SA4 is “Yes”), the horizontal reference signal generator 17a delays the phase of the horizontal timing signal HTMG with respect to the horizontal synchronization signal HS2 in accordance with the control of the control unit 22. (Step SA5).

  Next, the control unit 22 adds “1” to the variable i (step SA6). That is, in step SA6, the value of the variable i is incremented. After step SA6, the process returns to step SA2. Then, variable tc is initialized in step SA2.

  If the variable i is not “0” in step SA4 (step SA4 is “No”), the horizontal reference signal generator 17a changes the phase of the horizontal timing signal HTMG in accordance with the control of the control unit 22. Return to HS2 (step SA7). After step SA7, the process returns to step SA1 described above. Then, variable i is initialized in step SA1.

  By the processing as described above, the horizontal position of the image formed by the liquid crystal panel 19 changes every time the time counter detects the elapse of the predetermined time length TS.

  Instead of the above flow, the control unit 22 may control the timing generation circuit 17 so that the vertical position of the image changes in each of Step SA5 and Step SA7. Further, in each of step SA5 and step SA7, the control unit 22 may control the timing generation circuit 17 so that both the horizontal position and the vertical position change.

  The above-mentioned predetermined time length TS is a time length such that image sticking that occurs when a voltage of the same magnitude is continuously applied to the same pixel portion in the liquid crystal panel is within an allowable range. It has been established. In this embodiment, every time the time counter detects the elapse of the predetermined time length TS, at least one of the horizontal position and the vertical position of the image formed by the liquid crystal panel 19 changes. For this reason, the possibility that the same voltage is applied to the same pixel portion is reduced, and therefore, the formed image is less likely to be burned. A typical predetermined time length TS is about 10 seconds.

  In the present embodiment, since the change in the horizontal position of the image is one pixel or one scanning line, the user hardly perceives the displacement of the image. Here, even when the change in the horizontal position of the image is only one pixel or one scanning line, burn-in of the contour of the object in the image is prevented.

(Embodiment 2)
There is a low possibility that the same voltage is applied to the same pixel portion of the liquid crystal panel 19 before and after the image scene change. Therefore, in this embodiment, every time a scene change of an image is detected, the accumulated time measured by the time counter is initialized. As a result, according to the present embodiment, the possibility of image burn-in decreases and the number of times of changing the horizontal position and vertical position of the image decreases. In the following description, the same reference numerals as those of the first embodiment are given to the same components as those of the first embodiment.

  The display system 2 shown in FIG. 5 includes a scene change detector 30 in addition to the configuration of the display system 1 of the first embodiment. The scene change detector 30 displays an image represented by the image signal IV2 in accordance with the image signal IV2, the dot clock signal DC1, the horizontal synchronization signal HS1, and the vertical synchronization signal VS1 output from the A / D converter 13. Detect scene changes. Instead of this configuration, the scene change detector 30 corresponds to the image signal IV4 output from the D / A converter 16, the dot clock signal DC2, the horizontal synchronizing signal HS2, and the vertical synchronizing signal VS2. The scene change of the image represented by the image signal IV4 may be detected.

  In the present embodiment, the scene change detector 30 detects a scene change between two frames based on the difference in average luminance value between two adjacent frames. For example, when the difference in average luminance value is outside a predetermined range, the scene change detector 30 supplies a signal indicating that a scene change has been detected to the control unit 22 so that the difference in average luminance value is a predetermined value. If it is within the range, a signal indicating that there is no scene change is supplied to the control unit 22.

  When a scene change is detected, the time counter (control unit 22) initializes the accumulated time that has already been measured, and measures the accumulated time again from the time of the detected scene change. When the time counter detects that the accumulated time has reached the predetermined time length TS before the next scene change is detected, the timing generation circuit 17 generates a horizontal image of the image formed by the liquid crystal panel 19. Change at least one of position and vertical position.

  With reference to FIG. 6, the flow will be described in more detail by taking as an example a case where the horizontal position of the image changes.

  First, as an initialization process, the timing generation circuit 17 changes the phase of the horizontal timing signal HTMG to the horizontal synchronization signal HS2 so that the horizontal position and the vertical position of the image become standard positions according to the control of the control unit 22, respectively. The phase of the vertical timing signal VTMG is set with respect to the vertical synchronization signal VS2 (step SB0).

  Next, the control unit 22 initializes the variable i. As a result, in the case of FIG. 6, “0” is stored in the variable i (step SB1). Thereafter, the control unit 22 initializes a variable tc indicating the elapsed accumulated time. As a result, in the case of FIG. 6, “0” is stored in the variable tc (step SB2). Then, the control unit 22 increases the value of the variable tc, for example, in units of 5 seconds with the passage of time, thereby measuring the accumulated time. Note that the variable i and the variable tc are realized by the respective storage areas in the RAM 24 described above.

  Next, the control unit 22 determines whether or not the scene change detector 30 has detected a scene change (step SB3). If a scene change is detected (step SB3 is “Yes”), the process returns to step SB2. In step SB2, the variable tc is initialized.

  On the other hand, when there is no scene change (step SB3 is “No”), the process proceeds to step SB4. In step SB4, the control unit 22 determines whether or not the variable tc (or the accumulated time represented by the variable tc) is equal to or greater than the predetermined time length TS. When the variable tc is less than the predetermined time length TS (step SB4 is “No”), the process returns to step SB3. Only when there is no scene change, the control unit 22 repeats Step SB3 and Step SB4 until the variable tc becomes equal to or longer than the predetermined time length TS.

  When the variable tc is equal to or greater than the predetermined time length TS (step SB4 is “Yes”), the control unit 22 determines whether the variable i is “0” (step SB5). When the variable i is “0” (step SB5 is “Yes”), the horizontal reference signal generator 17a delays the phase of the horizontal timing signal HTMG with respect to the horizontal synchronization signal HS2 in accordance with the control of the control unit 22. (Step SB6).

  Next, the control unit 22 adds “1” to the variable i (step SB7). That is, in step SB7, the value of the variable i is incremented. After step SB7, the process returns to step SB2. In step SB2, the variable tc is initialized.

  When the variable i is not “0” in step SB5 (step SB5 is “No”), the horizontal reference signal generator 17a changes the phase of the horizontal timing signal HTMG according to the control of the control unit 22 to the horizontal synchronization signal. Return to HS2 (step SB8). After step SB8, the process returns to step SB1 described above. In step SB1, the variable i is initialized.

  Instead of the above flow, the control unit 22 may control the timing generation circuit 17 so that the vertical position of the image changes in each of step SB6 and step SB8. Further, in each of step SB6 and step SB8, the control unit 22 may control the timing generation circuit 17 so that both the horizontal position and the vertical position are changed.

  If there is a scene change in the image, the possibility that the same voltage is applied to the same pixel portion of the liquid crystal panel before and after the scene change is reduced. Therefore, according to the above flow, when a scene change is detected, the accumulated time measured by the time counter (control unit 22) is initialized, so that the possibility of image burn-in is reduced and the image is reduced. The number of times to change the horizontal position and vertical position of can be reduced.

1 is a block diagram illustrating a display system according to a first embodiment. FIG. 2 is a block diagram illustrating a timing generation circuit according to the first embodiment. (A) is a schematic diagram showing a case where the image is at the standard position, (b) is a schematic diagram showing a case where the horizontal position of the image is changed from the standard position, and (c) is a diagram where the vertical position of the image is standard. It is a schematic diagram which shows the case where it changes from a position, (d) is a schematic diagram which shows the case where the horizontal position and vertical position of an image have changed from each standard position. FIG. 3 is a diagram illustrating a flow when changing the horizontal position of an image in the first embodiment. FIG. 6 is a diagram showing a display system of a second embodiment. FIG. 9 is a diagram illustrating a flow when changing the horizontal position of an image in the second embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 2 ... Display system, 11 ... Input terminal, 12 ... Write synchronization generator, 13 ... A / D converter, 14 ... Frame memory device, 15 ... Read synchronization generator, 16 ... D / A converter, 17 ... Timing generation circuit, 17a ... Horizontal reference signal generator, 17b ... Vertical reference signal generator, 18 ... Drive circuit, 19 ... Liquid crystal panel, 20 ... Light source part, 21 ... Projection optical system, 22 ... Control part, 23 ... CPU 24 ... RAM, 25 ... ROM, 26 ... bus, 30 ... scene change detector.

Claims (4)

A liquid crystal panel for forming an image;
A timing generation circuit for defining a horizontal position and a vertical position of the image formed by the liquid crystal panel;
A time counter that detects the passage of a predetermined length of time;
With
Each time the time counter detects the elapse of the predetermined time length, the timing generation circuit changes at least one of the horizontal position and the vertical position.
Display system. A liquid crystal panel for forming an image;
A timing generation circuit for defining a horizontal position and a vertical position of the image formed by the liquid crystal panel;
A scene change detector for detecting a scene change of the image according to an image signal;
A time counter for measuring the accumulated time and detecting that the measured accumulated time has reached a predetermined time length, wherein the measured accumulated time is detected when the scene change detector detects the scene change. A time counter to initialize,
With
Each time the time counter detects that the accumulated time has reached the predetermined time length, the timing generation circuit changes at least one of the horizontal position and the vertical position.
Display system. A liquid crystal panel for forming an image;
A timing generation circuit for defining a horizontal position and a vertical position of the image formed by the liquid crystal panel;
A time counter that detects the passage of a predetermined length of time;
With
Each time the time counter detects the elapse of the predetermined time length, the timing generation circuit changes at least one of the horizontal position and the vertical position.
projector. A liquid crystal panel for forming an image;
A timing generation circuit for defining a horizontal position and a vertical position of the image formed by the liquid crystal panel;
A scene change detector for detecting a scene change of the image according to an image signal;
A time counter for measuring the accumulated time and detecting that the measured accumulated time has reached a predetermined time length, wherein the measured accumulated time is detected when the scene change detector detects the scene change. A time counter to initialize,
With
Each time the time counter detects that the accumulated time has reached the predetermined time length, the timing generation circuit changes at least one of the horizontal position and the vertical position.
projector.

Images