JP2009109955A - Timing controller for matrix display device, and liquid crystal display device adopting the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing controller for a matrix display device adopting control that makes inconspicuous flicker and noise of a display image due to noise superimposed on an input signal to the matrix display device. <P>SOLUTION: The timing controller 14 for the matrix display device for controlling a scanning line driving circuit to have a pause is provided with a timing control part 30 generating control signals for gate drivers 3-5 and control signals for source drivers 6-13 respectively based on reference input signals HD, VD, DENA, DCLK input from the outside, and an enable signal generating part 15 having a noise detecting circuit 17 for detecting entry of noise into the input signals, and outputting an enable signal (/OE) for turning off the output of the scanning line driving circuit for a predetermined period based on the output (Npulse) of the noise detecting circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a timing controller for a matrix display device and a liquid crystal display device employing the same, and in particular, an input signal from the outside to the liquid crystal display device has a timing different from a steady state due to external noise or the like. When it becomes, it can use suitably for the apparatus which made the noise visually recognized on a display inconspicuous.

  In the matrix liquid crystal display device, a timing controller that controls the image signal line driving circuit and the scanning line driving circuit includes a horizontal synchronization signal (hereinafter referred to as HD), a vertical synchronization signal (hereinafter referred to as VD), Control signals for the image signal line driving circuit and the scanning line driving circuit are generated using a dot clock (hereinafter referred to as DCLK) with reference to a data enable signal (hereinafter referred to as DENA).

  Therefore, once a non-stationary signal such as noise is mixed into the reference input signals (HD, VD, DENA) and DCLK during the display operation due to static electricity or the like, the signal generated inside the timing controller malfunctions. Incorrect control signals and image data may be output to the image signal line driving circuit and the scanning line driving circuit, and unsightly noise is visually recognized on the display screen.

  Further, even when the mutual relationship (timing) of the signals (HD, VD, DENA) serving as the control reference suddenly changes, a signal generated inside the timing controller malfunctions, and an erroneous control signal or image data is generated. May be output to the image signal line driving circuit and the scanning line driving circuit.

  Therefore, a method of fixing a control signal or image data output from the timing controller to a certain value for a while after detecting a change in timing as evidence of the erroneous control signal is well known (Patent Document). 1).

  However, the above method is also a measure for preventing an erroneous signal from being output to the image signal line driving circuit and the scanning line driving circuit, but an all-white or all-black screen is displayed during the fixed period of the signal. However, the flicker and noise of the displayed image are not necessarily made inconspicuous.

Japanese Patent Laid-Open No. 2001-134244

  The present invention has been made to solve the above-described problems. When an unsteady signal such as noise is mixed with an external input signal to the matrix display device, the display image flickers. Another object of the present invention is to obtain a timing controller and a display device of a display device that employs control that makes noise less noticeable.

  The timing controller of the matrix display device according to the present invention includes a timing control unit that generates a control signal for the scanning line driving circuit and a control signal for the image signal line driving circuit, respectively, based on a reference input signal input from the outside. And an unsteady timing detection circuit for detecting that the input signal has a timing different from the steady state, and the output of the scanning line driving circuit is turned off for a predetermined period based on the output of the unsteady timing detection circuit. And an enable signal generator for outputting an enable signal, wherein the scan line driver circuit controls the scan line driver circuit to receive the enable signal and to have a predetermined scan pause period.

  As a result, even if there is an error in the control signal or image data output from the timing controller due to noise or a change in the timing of the input signal, the noise appearing on the display can be made inconspicuous.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in order to avoid redundant description, elements having the same or corresponding functions in each drawing are denoted by the same reference numerals.

Embodiment 1 FIG.
FIG. 1 shows a circuit configuration of a liquid crystal display device 1 according to the first embodiment, and particularly shows a configuration of a peripheral circuit for driving a liquid crystal panel 2 in which scanning lines and video signal lines are formed in a matrix. is there. Drives image display data V-Data given from the outside of the liquid crystal display device 1 and image signal line drive circuits (6 to 13) and scanning line drive circuits (3 to 5) arranged to drive the liquid crystal panel 2 A plurality of signals serving as a control reference for the timing controller 14 to be input to the timing controller 14 together with DCLK serving as a reference for performing these processes.

  It should be noted that a plurality of signals serving as control references for the timing controller 14 in the figure are HD used as a reference signal for synchronizing the liquid crystal panel 2 in the horizontal direction, and for synchronizing the liquid crystal panel 2 in the vertical direction. VD used as a reference signal, DENA indicating a period during which image data is valid, and the like are included.

The timing controller 14 generates control signals for driving the image signal line drive circuits indicated by reference numerals 6 to 13 and the scanning line drive circuits indicated by reference numerals 3 to 5 in the timing control unit 30. .
Since the image signal line drive circuits (6 to 13) drive a plurality of image signal lines, a plurality of drive circuits connected to the signal lines are integrated, and similarly, the scan line drive circuits (3 to 5). ) Integrates a plurality of circuits for driving the scanning lines in order to drive the plurality of scanning lines. Further, by using a plurality of these integrated circuits, the number of image signal lines and the number of scanning lines of the liquid crystal panel 2 can be accommodated. (In FIG. 1, the scanning line represents the first wiring 31, the video signal line represents the leftmost wiring 32, and the other wirings are omitted.)

More specifically, signals for controlling the image signal line drive circuits (6 to 13) output from the timing controller 14 mainly include image display data (RGB-data: RGB is red, green, and blue, respectively). Digital signals, each having a data bus configuration of several bits wide), a reference clock CLKH for performing signal processing, and a start indicating the start of the image display data RGB-data in the horizontal direction A pulse STH, a latch pulse LP for transmitting the image display data RGB-data to the output side of the image signal line drive circuit (6 to 13), a polarity inversion signal (not shown) for inverting the polarity of the liquid crystal drive, etc. Contains control signals.
The signals for controlling the scanning line driving circuits (3 to 5) output from the timing controller 14 mainly include a clock CLKV for performing signal processing in the scanning line driving circuits (3 to 5), and a vertical signal. A start pulse STV indicating the start of scanning is included.
Further, a scanning line driving circuit output enable signal / OE is output from the timing controller 14 to the scanning line driving circuits (3 to 5) in order to adjust the timing and period of writing to the pixels 33, and the scanning line driving circuit is output by the signal. (3-5) Output ON / OFF is controlled. (Hereinafter, the symbol “/” represents that the subsequent signal is negative logic.) When the high level is input to the scanning line driving circuit (3-5) as the scanning line driving circuit output enable signal / OE. In the meantime, Low is applied to the scanning line from all output terminals. On the other hand, when the scanning line drive circuit output enable signal / OE is Low, a normal output operation is performed.

  Normally, the image signal line drive circuit (6 to 13) is connected to the pixel for each pixel corresponding to the scan line turned on by the scan line drive circuit (3 to 5). The desired image display voltage is written through each of the above. By performing this control sequentially for each scanning line, the entire image is displayed. (In FIG. 1, each pixel of the liquid crystal panel 2 shows only the pixel 33 and the TFT in the first row and the first column, and the others are omitted.)

  Here, the timing controller 14 generates control signals for the image signal line driving circuit and the scanning line driving circuit by using DCLK based on a plurality of signals (HD, VD, DENA) which are inputted as control references. Yes.

Next, the configuration of the output enable signal generation unit 15 that generates the scanning line drive circuit output enable signal / OE will be described with reference to FIG. As shown in the figure, the output enable signal generation unit 15 includes a noise detection circuit 17, a holding circuit 18, and an OR circuit 16, and is a part of the internal circuit of the timing controller 14.
The output enable signal / OEo turns on the output of the scanning line driving circuits (3 to 5) in order to adjust the timing and period of writing to the pixels from the timing controller 14 to the scanning line driving circuits (3 to 5). This is an internal signal of the timing controller 14 for controlling / OFF independently of other signals. The output enable signal / OEo signal is logically operated by the noise detection holding signal Nkeep and the OR gate 16 to drive the scanning line. A circuit output enable signal / OE is generated.

Here, the noise detection signal Npulse in FIG. 2 indicates that the noise detection circuit 17 has detected a timing different from the steady state such as noise (this noise detection circuit detects an unsteady timing period of the input signal). Input to the holding circuit 18.
The holding circuit 18 receives the noise detection signal Npulse and the control reference signals (HD, VD, DENA, DCLK) and detects the unsteady timing in the noise detection circuit 17, and then detects the noise for a predetermined period. The signal Npulse is held, and the noise detection holding signal Nkeep is output to the OR circuit 16. As a result, the noise detection holding signal Nkeep is a signal obtained by extending the noise detection signal Npulse for a predetermined period. The predetermined period is set to the timing exemplified below in the holding circuit 18 using signals (HD, VD, DENA, DCLK, etc.) that are input as control references. (Hereinafter, the “predetermined period” means a predetermined “predetermined scanning pause period”.)

  In FIG. 2, it is assumed that the scanning line driving circuit output enable signal / OE sets the output of the scanning line driving circuits (3 to 5) to an OFF state (disable) when the scanning line driving circuit output enable signal / OE is logically in a high state. Therefore, the OR circuit 16 is used for the logical operation of the output enable signal / OEo and the noise detection holding signal Nkeep.

  FIG. 3 shows a timing chart of the output enable signal / OEo, the noise detection signal Npulse, the noise detection holding signal Nkeep, and the scanning line drive circuit output enable signal / OE. The noise detection signal Npulse detected by the noise detection circuit 17 has a relatively short pulse width corresponding to an input period of unsteady timing represented by noise and the signal is extended for a predetermined period. The noise detection holding signal Nkeep is a signal having a pulse width of at least the HD period. Therefore, the scanning line drive circuit output enable signal / OE that has passed through the OR circuit 16 also has a pulse width equal to or greater than the HD period.

  Next, the configuration of the scanning line driving circuits (3 to 5) employed in this embodiment is shown in FIG. The state pulse STV signal input to the scanning line driving circuit (3 to 5) and indicating the start of the vertical scanning is shifted in the shift register 20 for each cycle of the scanning clock CLKV for performing signal processing. The ON signals are sequentially shifted in the order of g1, g2,.

  As a result, the outputs of the scanning line driving circuits (3 to 5) corresponding to the ON lines are boosted to a desired voltage via the level shifter circuit group 22 in order of G1, G2,. The pixels for one line of the panel 2 are in a state in which writing is possible in line order in synchronization with the scanning clock CLKV.

  In FIG. 4, the scanning line driving circuit output enable signal / OE is turned off by using the inverter circuit 23 and the NAND circuit group 21 at the timing independent of the signal from the shift register 20. It is a negative logic signal that can be put into a state. Other configurations are common in the scanning line driving circuit, and detailed description thereof is omitted here.

  Next, configuration examples of the noise detection circuit 17 and the holding circuit 18 are shown below.

  FIG. 5 is a block diagram showing an embodiment of the noise detection circuit 17. FIG. 6 shows a timing waveform (electric waveform) of the internal signal of the noise detection circuit 17 shown in FIG.

  In FIG. 5, signals (HD, VD, DENA, DCLK, etc.) serving as control standards are input to the noise detection circuit 17. These signals (HD, VD, DENA, DCLK) serving as control standards have timing constraints depending on the resolution of the liquid crystal panel 2 to be connected. In the present embodiment, the liquid crystal panel 2 has a resolution of VGA (640 × 480), and an image signal line drive circuit (6 to 6) that captures image display data RGB-data for one dot (R, G, B) every 1 DCLK. 13) is adopted, and DENA needs a length corresponding to DCLK640 clocks. (In FIG. 6, when DENA is High, it is assumed that the positive logic is the data valid period.)

  The length of the DENA is a restriction attributed to the liquid crystal display device having a predetermined resolution. This value is stored as a parameter in the timing constraint holding circuit 25 with ref = 640 (FIG. 6). Then, ref = m).

  On the other hand, the comparison circuit 26 has a counter for counting DCLK (not shown), and continues to count up the DCLK signal during the period when DENA is High. When this count value is n, DENA is Low. Then, the value n of the counter is compared with the value m.

  When the comparison results are not the same (n ≠ m), the comparison circuit 26 determines that it is in an unsteady state (a state in which noise or the like is included) and outputs a noise detection signal Npulse having a certain width.

  In this circuit, an example of determining whether the reference signal (DENA) is in a steady state or an unsteady state by comparing the effective period (High) width with respect to the restriction item (ref = 640) of the DENA. Although it is shown, as another method, it is easy to determine whether it is steady or unsteady by counting and comparing the constraint conditions of HD and VD and their actual signal waveforms (pulse width, period length, etc.) sequentially. It can also be judged.

  Further, here, the restriction item ref (= 640) of the DENA is treated as a preset fixed parameter (a constant unique to the display device), but the pulse width of the input DENA is measured by a counter (not shown), and the DENA If the effective period (High) width is extracted and stored a plurality of times (in the storage circuit in the timing constraint holding circuit 25), and the stored value is repeated a predetermined number of times (for example, three times or five times). The value may be stored as a definite value of the restriction item ref and used in the comparison circuit 26, and the value of the restriction item ref from which an unsteady timing period such as noise is removed can be obtained.

  Next, FIG. 7 shows a timing chart of input / output and internal signals of the holding circuit 18 shown in FIG. The holding circuit 18 fixes the noise detection holding signal Nkeep to High for a predetermined period by receiving the noise detection signal Npulse (scanning pause period). In FIG. 7, the detection of the non-stationary timing, that is, the scanning line driving circuit (3 to 5) is turned off for approximately 2HD (= 2 line scanning period) immediately after the noise detection signal Npulse is input. In addition, the noise detection holding signal Nkeep is continuously fixed to High using HD as a reference signal.

In order to minimize the influence on the display, it is desirable that the period during which the scanning line driving circuits (3 to 5) are turned off be performed in units of lines or frames.
Therefore, in the present embodiment, the purpose is to control the output signal of the timing controller 14, and as shown in FIG. 2, HD is one of the input signals to the timing controller 14, and the HD is used as a reference. When the noise detection holding signal Nkeep is generated as a signal, timing adjustment is preferably performed in units of a reference clock (for example, DCLK) synchronized with the scanning clock CLKV generated based on HD.

  By the way, in this embodiment, as shown in FIGS. 2 and 3, the scanning line drive circuit output enable signal / OE is logically output for a predetermined period after the unsteady timing such as noise is detected in the timing controller 14. By setting a high level, the output of the scanning line driving circuit (3-5) is independent of the operating state of the image signal line driving circuit (6-13) and the operating state of the scanning line driving circuit (3-5). Is set to the OFF state, and the scanning pause period is set.

  As a result, even if an unsteady timing such as noise is input, the image signal line driving circuit (6 to 13) temporarily enters a malfunction state, and the noise is superimposed on the image signal to become an erroneous signal. Even if the signal line driving circuit (6 to 13) tries to write the erroneous signal to the liquid crystal panel 2, each pixel in the liquid crystal panel 2 is in an OFF state while the output of the scanning line driving circuit (3 to 5) is in the OFF state. The TFT is not turned on.

Therefore, during the scanning pause period, the liquid crystal panel 2 holds the previous image state in which the unsteady timing is detected.
In each pixel, the state of the previous image often does not change greatly even if it becomes the next frame unless a moving image having a large luminance change is displayed.

  Therefore, even if noise or the like is superimposed on the input signal and the control output signal related to the timing controller 14 or the image signal becomes an incorrect signal, the disturbance in the display image can be made inconspicuous.

  Here, after the non-stationary timing such as noise is detected by the noise detection circuit 17, the scanning pause period in which the output of the scanning line driving circuit (3 to 5) is kept in the OFF state is an assumed unsteady timing. The timing controller detects the non-stationary timing from the input signal of the timing controller 14 and the time until the input signal returns to the normal state and the control in the timing controller 14 returns to the normal state. The required time length differs for each 14.

  For this reason, after considering the assumed unsteady timing duration and the return time that varies depending on the configuration of each timing controller, a predetermined period (a plurality of periods) in which the OFF state (disable) is maintained for a sufficient time including these. HD period).

  Furthermore, the timing for returning to the normal driving state is a state where the control state for the image signal line driving circuits (6 to 13), the scanning line driving circuits (3 to 5) and the liquid crystal panel 2 connected thereto is halfway. It must not be from. This is because there is a high possibility that the display will be disturbed by returning from the halfway control state.

In order to eliminate these influences, it is desirable that the scanning pause period in which the output of the scanning line driving circuits (3 to 5) is kept OFF before returning is performed in line units or frame units.
For example, the scanning pause period may be a plurality of lines including the line period in which the unsteady timing is detected, and the end of the period may be the end of the frame to which the line period belongs.
Furthermore, a sufficient normal return period may be secured by extending the end of the period by several frames (at least one frame). This is because signals (HD, VD, DENA, DCLK) serving as control references are input to the holding circuit 18, and the period of the noise detection holding signal Nkeep is controlled by the holding circuit 18 using these reference signals. Can be easily realized.

  As another example, since the reference signal and the noise detection signal Npulse are input to the holding circuit 18, the length of the unsteady timing such as noise, that is, the period length of the noise detection signal Npulse, and the timing control accordingly The length of the scanning pause period may be selected in consideration of the time until the unit 30 returns from the noise input to the normal driving state.

  FIG. 7 shows an example in which the noise detection holding signal Nkeep is generated in units of horizontal periods (lines), and an HD that drives in units of horizontal periods is directly used as the reference signal. In 14, there are many other cases in which signals that are driven in units of several horizontal periods are internally generated.

  Further, when the noise detection holding signal Nkeep is generated in units of vertical periods (frames), VD that is driven in units of vertical periods may be used as the reference signal of the holding circuit 18.

Embodiment 2. FIG.
This embodiment is different from the first embodiment in that a circuit that detects a significant change in timing (hereinafter, this circuit is referred to as a timing change detection circuit) is used instead of using the noise detection circuit. Different. FIG. 8 shows a block diagram of the output enable signal generator 15 employing the timing change detection circuit 27. As shown in FIG.

  Here, the timing change detection signal Cpulse in FIG. 8 indicates that a significant change in timing has been detected, and the timing change holding signal Ckeep further detects unsteady timing such as noise by the timing change detection signal Cpulse. Then, by holding the value for a while, it indicates that it is within a predetermined period (scanning pause period) from detection of a significant change in timing.

  Further, the output enable signal / OEo generated to be sent from the timing controller 14 to the scanning line driving circuits (3 to 5) is logically operated by the timing change holding signal Ckeep and the OR gate 16, thereby finally The same scanning line driving circuit output enable signal / OE is generated as in the first embodiment.

  8 and 9, as in the first embodiment, when the scanning line drive circuit output enable signal / OE is logically in a high state, the output of the scanning line drive circuit is turned off (disabled). This circuit is based on the assumption that

  As a result, the image signal line drive circuit (6-13) temporarily enters a malfunction state due to a sudden change in timing due to noise or the like, and the image signal becomes an erroneous signal, and the image signal line drive circuit (6-13) Even if the erroneous signal is written into the liquid crystal panel 2, each pixel TFT in the liquid crystal panel 2 is not turned on while the output of the scanning line driving circuit (3 to 5) is in the off state (see FIG. 9).

  For this reason, during the scanning pause period, the liquid crystal panel 2 holds the image state of the previous frame for detecting a sudden change in timing.

  Therefore, even if the control signal related to the timing controller 14 or the image signal becomes an erroneous signal due to the sudden change of the timing due to the input of an unsteady signal such as noise, the disturbance in the display image can be made inconspicuous. .

  Here, the length of the predetermined period for keeping the output of the scanning line driving circuit (3-5) in the OFF state (disabled) after detecting the sudden change in the timing is the duration of the assumed timing change, Depending on the time from when the input signal of the timing controller 14 undergoes a sudden change in timing and when the input signal returns to the normal state and the control within the timing controller 14 returns to normal completely, The required time length is different.

  Therefore, in consideration of the assumed duration of the timing change and the return time for each timing controller, a sufficient period including these is maintained for a predetermined period of time during which the OFF state (disable) is maintained (disabled). (Multiple HD periods) should be set.

  Furthermore, the timing for returning to the normal driving state is a state where the control state for the image signal line driving circuits (6 to 13), the scanning line driving circuits (3 to 5) and the liquid crystal panel 2 connected thereto is halfway. It must not be from. This is because there is a high possibility that the display will be disturbed by returning from the halfway control state.

  In order to eliminate these influences, it is desirable that the scanning pause period during which the output of the scanning line driving circuits (3 to 5) is kept OFF before returning is controlled in line units or frame units.

  Hereinafter, details of the timing change detection circuit 27 will be described. FIG. 10 is a block diagram showing an example of the timing change detection circuit 27. As shown in FIG. FIG. 11 shows the flow of signals (electrical waveforms) used in FIG.

  In FIG. 10, signals (HD, VD, DENA, DCLK) serving as control references are input to the timing change detection circuit 27. These timing relationships are not frequently changed in the normal driving state. Therefore, in FIG. 11, as an example, the number of dot clocks DCLK from the rising edge of HD to the rising edge of DENA is handled as timing information (ref = m).

  Since the timing information is not frequently changed in the normal driving state as described above, it is held as a parameter in the normal timing information holding circuit 28 (ref = m in FIG. 11).

  On the other hand, a counter is provided in the comparison circuit 26, and during the period from the rising edge of HD to the rising edge of DENA, for example, DCLK is continuously counted up, and when DENA = 1, the counter values n and m Compare

  If the comparison results are not the same (n ≠ m), it is determined that the timing has just been changed, and the timing change detection signal Cpulse is raised.

  At the same time, the changed timing is updated by the timing information holding circuit 28 as a new parameter.

  As described above, in FIGS. 10 and 11, it is determined whether the state is the normal driving state or the state immediately after the timing is changed by comparing the parameters that are likely to affect the image disturbance due to the timing change. However, it is assumed that the affected timing varies depending on the logic design of the timing controller 14 and the placement and routing of the logic elements. Therefore, it is preferable to store / detect timing information suitable for each timing controller to detect a sudden change in timing.

  Moreover, although the example which updates timing information whenever timing information is changed was demonstrated here, when the same value is repeated without updating each time, the value is updated as timing information. Also good.

  Next, FIG. 12 shows a timing chart of input / output and internal signals of the holding circuit 18 shown in FIG. The holding circuit 18 receives the timing change detection signal Cpulse and fixes the timing change holding signal Ckeep for a predetermined period to High (scan pause period). In FIG. 12, the scanning line driving circuits (3 to 5) are turned off (disabled) for approximately 2HD (= 2 line scanning period) immediately after the detection of unsteady timing such as noise, that is, the timing change detection signal Cpulse. The timing change holding signal Ckeep is kept fixed at High with HD as a reference signal.

  In order to minimize the influence on the display, it is desirable that the period during which the scanning line driving circuits (3 to 5) are turned off be performed in units of lines or frames. Therefore, in the present embodiment, the purpose is to control the output signal of the timing controller 14, and as shown in FIG. 8, HD is one of the input signals to the timing controller 14, and the HD is used as a reference. When the timing change holding signal Ckeep is generated as a signal, it is preferable to adjust the timing in units of a clock (for example, DCLK) serving as a reference synchronized with the scanning clock CLKV generated based on HD.

  FIG. 12 shows an example in which the timing change holding signal Ckeep is generated in units of horizontal periods (lines), and an HD that drives in units of horizontal periods is directly used as the reference signal. In 14, there are many other cases in which signals that are driven in units of several horizontal periods are internally generated.

  Further, when the timing change holding signal Ckeep is generated in units of vertical periods (frames), VD that is driven in units of vertical periods may be used as the reference signal of the holding circuit 18.

  As in the first embodiment, the scanning pause period may be a plurality of lines including the line period in which the unsteady timing is detected, and the end of the period may be the end of the frame to which the line period belongs. Furthermore, a sufficient normal return period may be secured by extending the end of the period by several frames (at least one frame). This is facilitated by controlling the period of the timing change holding signal Ckeep in the holding circuit 18 using the reference signals (HD, VD, DENA) inputted to the holding circuit 18 and using these reference signals. Can be realized.

  Further, since the reference signal and the timing change detection signal Cpulse are input to the holding circuit 18, the length of the non-stationary timing period such as noise, that is, the period length of the timing change detection signal Cpulse and the timing control unit 30 accordingly. The length of the scanning pause period may be selected in consideration of the time from the unsteady timing input to the return to the normal driving state.

  The circuits described in Embodiment Modes 1 and 2 can be provided in a scan line driver circuit.

In the first and second embodiments described above, the superposition of external noise has been described as an example of the cause of the input signal having a timing different from the steady state. However, the present invention is not limited to this. is not.
For example, discontinuity of the video synchronization signal when the video signal displayed on the in-vehicle display device is switched from an image signal input from outside the device such as a TV broadcast image to a signal generated inside the device such as a navigation map screen. As a result, similar non-stationary timing may occur, and switching noise can be made inconspicuous using the present invention.

  Finally, the signals etc. used in the description of the embodiment only show the main signals necessary for explaining the control contents. In practice, there are some other preliminary signals. Other signals are also required.

It is a block diagram of the liquid crystal display device which concerns on Embodiment 1 of this invention. FIG. 2 is a block diagram illustrating a configuration of an output enable signal generation unit in FIG. 1. FIG. 3 is a waveform diagram showing timings of internal signals and input / output signals in FIG. 2. It is a block diagram showing the structure of a scanning line drive circuit. It is a block diagram showing the structure of a noise detection circuit. FIG. 6 is a waveform diagram showing timings of internal signals and input / output signals of the noise detection circuit shown in FIG. 5. FIG. 3 is a waveform diagram showing timings of internal signals and input / output signals of the holding circuit shown in FIG. 2. 6 is a block diagram illustrating a configuration of an output enable signal generation unit according to Embodiment 2. FIG. FIG. 9 is a waveform diagram illustrating timings of internal signals and input / output signals in FIG. 8. FIG. 9 is a block diagram illustrating a configuration of a timing change detection circuit in FIG. 8. It is a wave form diagram showing the timing of the internal signal and output signal which were shown in FIG. FIG. 9 is a waveform diagram showing timings of internal signals and input / output signals of the holding circuit shown in FIG. 8.

Explanation of symbols

2 Liquid crystal panel 3, 4, 5 Scan line drive circuit 6, 7, 8, 9, 10, 11, 12, 13 Image signal line drive circuit 14 Timing controller 15 Output enable signal generator 16 OR circuit 17 Noise detection circuit 18 Holding Circuit 25 Timing constraint holding circuit 26 Comparison circuit 27 Timing change detection circuit 28 Timing information holding circuit 30 Timing control unit 31 Scan line 32 Video signal line

Claims (9)

A matrix display device timing controller having a timing control unit that generates a control signal for a scanning line driving circuit and a control signal for an image signal line driving circuit based on a reference input signal input from the outside,
An unsteady timing detection circuit that detects that the input signal has a timing different from the steady state, and outputs an enable signal for turning off the output of the scanning line driving circuit based on the signal output of the unsteady timing detection circuit Further comprising an enable signal generation unit,
A timing controller for a matrix display device, wherein the scanning line driving circuit controls the scanning line driving circuit so that the scanning line driving circuit receives the enable signal and has a predetermined scanning pause period. 2. The matrix display device according to claim 1, wherein the non-stationary timing detection circuit outputs a non-stationary timing detection signal when the timing constraint determined in accordance with the resolution of the display screen does not match. 3. Timing controller. The non-stationary timing detection circuit detects that the timing of the signal has changed significantly with respect to a reference signal input from the outside, and outputs the non-stationary timing detection signal. 2. A timing controller for a matrix display device according to 1. 4. The timing controller for a matrix display device according to claim 1, wherein the predetermined scanning pause period is a scanning period for one line. 4. The timing controller for a matrix display device according to claim 1, wherein the predetermined scanning pause period is a scanning period for a plurality of lines. 4. The predetermined scanning pause period can be selected according to the length of the non-stationary period and the time from when the timing control unit detects the non-stationary timing until the normal driving state is reached. The timing controller according to any one of the above. 4. The matrix display device timing controller according to claim 1, wherein the predetermined scanning pause period is a period from when the unsteady timing is detected to when the frame ends. 5. The matrix according to any one of claims 1 to 3, wherein the predetermined scanning pause period is a period from the detection of the unsteady timing to the end of the frame and a few frames later. Timing controller for display devices. A liquid crystal panel, a scanning line driving circuit for driving the scanning line, and
9. A liquid crystal display device using the timing controller according to claim 1, which controls the scanning line driving circuit.

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