KR20080010986A - Driving apparatus and liquid crystal display comprising the same - Google Patents

Abstract

A driver and a liquid crystal device having the same are provided to normally operate a gate driver by preventing operation failure in which data corresponding to a last line is not output. A drive mode detection unit(310) performs OR operation on first and second gate clock signals every activation period of a vertical sync start signal to output a line overlap signal. A gate driver(330) provides n numbers of gate selection signals to select the gat line. A carry signal proving unit(350) selectively outputs (n-1)th gate selection signal or n-th gate selection signal in accordance with the line overlap signal. The drive mode detection unit has a signal calculation unit for performing OR operation on the first and second gate clock signals and a signal reset unit for resetting the line overlap signal.

Description

Driving apparatus and liquid crystal display including the same {Driving apparatus and liquid crystal display comprising the same}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an internal block diagram of a driving apparatus according to an embodiment of the present invention.

3 is an internal block diagram of the driving mode detector of FIG. 2.

4 is an output timing diagram of a carry signal according to first and second gate clock signals.

5 is a timing diagram illustrating a line overlap mode according to an embodiment of the present invention.

6 is an internal block diagram of a gate driver according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: liquid crystal panel 200: voltage generator

300: driving device 310: driving mode detection unit

330: gate driver 350: carry signal providing unit

400: gamma voltage generator 500: data driver

600: timing controller

The present invention relates to a driving device and a liquid crystal display including the same, and more particularly, to a driving device capable of preventing a malfunction of the gate driver and a liquid crystal display including the same.

In general, a liquid crystal display includes a TFT substrate on which a thin film transistor (TFT) for switching each pixel is formed, and a color filter substrate on which a color pixel is formed, and a TFT substrate and a color filter substrate. It consists of a sealed liquid crystal layer. The liquid crystal constituting the liquid crystal layer is characterized in that the arrangement is changed according to the electric field applied between the two substrates, and the light transmittance (transmissive index) is changed according to the arrangement.

Recently, in order to improve display characteristics, a liquid crystal display uses a 120Hz driving method that drives a screen twice as fast as a conventional 60H driving method. Here, the liquid crystal display is composed of two thin film transistors, and the pixel electrode is composed of two sub pixel electrodes. In this case, each thin film transistor is connected to each sub pixel electrode. Due to the fast switching operation characteristics, the charging rate of the liquid crystal display may be insufficient. In order to solve this problem, a line overlap driving method is used.

The gate driving IC recognizes the line overlap driving method by performing the OR operation on the gate clock signal CPV1 and the gate clock signal CPV2 and performing line overlap driving when the result is a high level. However, when the operation result is a low level in the period between the frame and the frame, that is, the blank period, the normal driving is performed and the operation does not operate again in the line overlap driving mode. For this reason, the output timing of the carry signal of the gate driver does not match, and the gate driver malfunctions.

An object of the present invention is to provide a driving device that can prevent the malfunction of the gate driver.

An object of the present invention is to provide a liquid crystal display device including a driving device capable of preventing a malfunction of the gate driver.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, a driving mode detection unit for outputting a line overlap signal by performing a calculation on the first and second gate clock signals for each activation period of a vertical synchronization start signal is performed. A gate driver for sequentially providing n (where n is a natural number) gate selection signals for selecting a line, and optionally an n-1 th gate selection signal or an n th gate selection signal as a carry signal according to the line overlap signal It includes a carry signal providing unit for outputting.

According to an exemplary embodiment of the present invention, a liquid crystal panel including a plurality of unit pixels defined in an area where a plurality of gate lines and data lines intersect, a gate driver, and a data driver is driven. A timing controller configured to generate a gate and data control signal, a driving voltage generator configured to receive the control signal, and generate a plurality of driving voltages; A driving mode detector for outputting a line overlap signal, a gate driver sequentially providing n (where n is a natural number) gate selection signals for selecting a gate line, and an n-1th gate selectively according to the line overlap signal A carry for outputting a select signal or an nth gate select signal as the carry signal And a data driver for applying a data voltage to the data line.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 100, a voltage generator 200, a driver 300, a gamma voltage generator 400, and a data driver ( 500, the timing controller 600.

The liquid crystal panel 100 is connected to a plurality of display signal lines G1-Gn and D1 -Dm as viewed in an equivalent circuit, and includes a plurality of unit pixels arranged in a matrix form.

Here, the display signal lines G1-Gn and D1-Dm include a plurality of gate lines G1-Gn transferring gate signals and data lines D1-Dm transferring data signals. The gate lines G1-Gn extend in the row direction and are substantially parallel to each other, and the data lines D1-Dm extend in the column direction and are substantially parallel to each other.

Each unit pixel includes a switching element Q connected to the display signal lines G1-Gn, D1-Dm, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. The sustain capacitor Cst may be omitted as necessary.

The switching element Q is provided on the TFT substrate, and the control terminal and the input terminal thereof are connected to the gate lines G1-Gn and the data lines D1-Dm, respectively, and the output terminal is a liquid crystal capacitor. (Clc) and sustain capacitor (Cst).

The liquid crystal capacitor Clc has a pixel electrode of a TFT substrate and a common electrode of a color filter substrate as two terminals, and the liquid crystal layer between the two electrodes functions as a dielectric. The pixel electrode is connected to the switching element Q, and the common electrode is formed on the front surface of the color filter substrate and receives the common voltage Vcom. Here, the common electrode may be provided in the TFT substrate, in which case both electrodes are made in a linear or bar shape.

The sustain capacitor Cst is formed by superimposing a separate signal line (not shown) and a pixel electrode provided on the TFT substrate, and a predetermined voltage such as the common voltage Vcom is applied to the separate signal line (independent wiring method). However, the sustain capacitor Cst may be formed such that the pixel electrode overlaps the front end gate line directly above the insulator (shear gate method).

On the other hand, in order to implement color display, each unit pixel should be able to display color, which is possible by providing a red, green, or blue color filter in a region corresponding to the pixel electrode. Here, the color filter can be formed in the corresponding region of the color filter substrate, and can also be formed above or below the pixel electrode of the TFT substrate.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the TFT substrate and the color filter substrate of the liquid crystal panel 100.

The voltage generator 200 generates a plurality of driving voltages. For example, the voltage generator 200 generates a gate on voltage Von, a gate off voltage Voff, and a common voltage Vcom.

The driving device 300 is connected to the gate lines G1-Gn of the liquid crystal panel 100 to receive a gate selection signal formed of a combination of a gate on voltage Von and a gate off voltage Voff from the outside. -Applied to Gn). In addition, the driving device 300 receives the vertical synchronization start signal STV and the first and second gate clock signals CPV1 and CPV2 from the timing controller 60 to generate a line overlap signal, and generates the line overlap signal. The gate selection signal is selectively output as a carry signal DOI. Detailed description thereof will be described with reference to FIG. 2.

The gamma voltage generator 400 may generate two sets of gamma voltages related to transmittance of a unit pixel. In other words, one of the two sets is the positive data voltage and the other is the negative data voltage. The positive data voltage and the negative data voltage mean voltages whose polarities of the data voltages are opposite to the common voltage Vcom, and are alternately provided to the liquid crystal panel during inversion driving.

The data driver 500 is connected to the data lines D1-Dm of the liquid crystal panel 100, and generates a plurality of data voltages based on the plurality of gamma voltages provided from the gamma voltage generator 400. The data voltage is selected and applied to the unit pixel as a data signal, and is usually composed of a plurality of integrated circuits.

The timing controller 600 generates control signals for controlling operations of the driving apparatus 300 and the data driver 500, and provides the corresponding control signals to the driving apparatus 300 and the data driver 500.

Hereinafter, the display operation of the liquid crystal display will be described in more detail.

The timing controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal. (Hsync), main clock (MCLK), data enable signal (DE) is provided. The timing controller 600 generates a gate control signal CONT1, a data control signal CONT2, and the like based on the input control signal, and appropriately matches the image signals R, G, and B with the operating conditions of the liquid crystal panel 100. After processing, the gate control signal CONT1 is provided to the driving device 300, and the data control signal CONT2 and the processed image signals R ', G', and B 'are provided to the data driver 500.

Here, the gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate on pulse (gate on voltage section), a gate clock signal CPV controlling the output timing of the gate on pulse, and a gate on. An output enable signal OE or the like that defines the width of the pulse. Among these, the output enable signal OE and the gate clock signal CPV are provided to the voltage generator 200.

The data control signal CONT2 is a horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and a load signal for applying a corresponding data voltage to the data lines D1-Dm. TP), the polarity signal (POL) and the data clock signal (inverting the polarity of the data voltage with respect to the common voltage (VCOM) (hereinafter referred to as 'polarity of the data voltage by reducing the polarity of the data voltage for the common voltage') HCLK) and the like.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of unit pixels according to the data control signal CONT2 from the timing controller 600. By selecting data voltages corresponding to the image data R ', G', and B ', the image data R', G ', and B' are converted into the corresponding data voltages.

The driving device 300 applies a gate-on voltage Von to the gate lines G1-Gn in response to the gate control signal CONT1 from the timing controller 600, and is connected to the gate lines G1-Gn. Turn on (Q).

While a gate-on voltage Von is applied to one gate line G1-Gn, and a row of switching elements Q connected thereto is turned on (this period is '1H' or '1 horizontal period'). And the same as one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 transmits each data voltage to the corresponding data line D1-Dm. Supply. The data voltage supplied to the data lines D1-Dm is applied to the corresponding unit pixel through the turned-on switching element Q.

The liquid crystal molecules change their arrangement according to the electric field generated by the pixel electrode and the common electrode, and thus the polarization of light passing through the liquid crystal layer changes. This change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the TFT substrate and the color filter substrate.

In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G1 -Gn during one frame to apply data voltages to all the unit pixels. When one frame ends, the next frame starts and the state of the polarity signal POL applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each unit pixel is opposite to that of the previous frame ('frame' reversal'). In this case, the polarity of the data voltage flowing through one data line may be changed ('line inversion') or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the polarity signal POL within one frame ( 'Dot reversal').

2 is an internal block diagram of a driving apparatus according to an embodiment of the present invention, FIG. 3 is an internal block diagram of the driving mode detection unit of FIG. 2, and FIG. 4 is a view of a carry signal according to first and second gate clock signals. 5 is a timing diagram illustrating a line overlap mode according to an embodiment of the present invention, and FIG. 6 is an internal block diagram of a gate driver according to an embodiment of the present invention.

Referring to FIG. 2, the driving device 300 according to an exemplary embodiment of the present invention includes a driving mode detector 310, a gate driver 330, and a carry signal providing unit 350.

The driving mode detector 310 includes a signal calculator 312 and a signal reset unit 314 as shown in FIG. 3.

The signal operation unit 312 receives the vertical synchronization start signal STV and the first and second gate clock signals CPV1 and CPV2 from the timing controller 600, so that the first and second signals are activated for each activation period of the vertical synchronization start signal. The gate clock signal is ORed to output the line overlap signal CPV_LO.

The signal reset unit 314 resets the line overlap signal CPV_LO to output the line overlap reset signal CPV_RST. At this time, the reason for resetting the line overlap signal is as follows. Here, it is assumed that one gate driver provides a gate output signal corresponding to 1 to 270 gate lines.

Referring to FIG. 4, in the blank period A before the vertical synchronization start signal is input, the first and second gate clock signals CPV1 and CPV2 have a low level so that the overlap signal CPV_LO is low. There is a section with a level. In addition, the periods B and C having the low level of the line overlap signal CPV_LO are generated by the noise, so that the gate driver operates in the normal mode.

Therefore, the original gate driver 330 overlaps the charging rate of the next n + 1th gate line to be output in advance for a short time (T) while the nth gate line is being charged as shown in FIG. Must operate in mode.

However, the gate driver 330 does not operate in the line overlap mode, but outputs the carry signal G from the 270th second gate clock signal E to operate in the normal mode as shown in FIG. 3. Therefore, in the present invention, the line overlap signal CPV_LO is generated by performing the OR operation on the first and second gate clock signals for each activation period of the vertical synchronization start signal, and outputting the carry signal DOI according to the line overlap signal CPV_LO. Adjust the view point. That is, the gate driver operates in the overlap mode so that the carry signal F is output at the falling edge of the 269 th first gate clock signal D. FIG.

The gate driver 330 starts outputting the first and second gate clock signals CPV1 and CPV2 according to the vertical synchronization start signal STV from the timing controller 600, and arranges the gate lines G1-Gn in a row. ), A gate selection signal, that is, a gate-on voltage Von is applied in turn.

As shown in FIG. 6, the first shift register 232 starts outputting the gate-on voltage Von in synchronization with the vertical synchronization start signal STV and the first gate clock signal CPV1, and the second shift. From the register 234, the output of the gate-on voltage Von is started in synchronization with the output voltage of the previous shift register and the second gate clock signal CPV2. Although not shown, the shift register may be represented by an SR latch and an AND gate by an equivalent circuit.

The carry signal providing unit 350 includes a line overlap signal CPV_LO provided from the driving mode detection unit 310, an n-1 th gate selection signal Gn-1 and an n th gate selection provided from the gate driver 330. The signal Gn is input. The n-th gate selection signal Gn-1 or the n-th gate selection signal Gn is selectively output as the carry signal DOI according to the line overlap signal CPV_LO. Here, when the line overlap signal is at the high level ('1'), as shown in FIG. 5, the n-1 th gate selection signal is synchronized with the falling edge of the first gate clock signal CPV1 as a carry signal. Output as (DOI). In addition, when the overlap signal is at the low level '0', the n-th gate selection signal is output as the carry signal DOI in synchronization with the falling edge of the second gate clock signal CPV2.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

As described above, the driving device and the liquid crystal display including the same generate line overlap signals using the first and second gate clock signals for each activation period of the vertical synchronization start signal, and generate a line overlap signal according to the signal. By controlling the output timing of the carry signal, the output timing of the carry signal does not match between the gate drivers, thereby preventing a driving failure in which data corresponding to the last line is not output. Therefore, the gate driver can be normally operated.

Claims (8)

A driving mode detector for outputting a line overlap signal by performing an operation on the first and second gate clock signals for each activation period of the vertical synchronization start signal; A gate driver sequentially providing n (where n is a natural number) gate selection signals for selecting a gate line; And And a carry signal providing unit configured to selectively output an n−1 th gate selection signal or an n th gate selection signal as a carry signal according to the line overlap signal. The method of claim 1, The driving mode detector may include a signal calculator configured to output a line overlap signal by performing an operation on the first and second gate clock signals for each activation period of the vertical synchronization start signal; And And a signal reset unit configured to reset the line overlap signal and output a line overlap reset signal. The method of claim 1, And outputting the N-th gate selection signal as a carry signal in synchronization with a falling edge of the first gate clock signal when the line overlap signal is at a high level. The method of claim 1, And outputting the N-th gate selection signal as a carry signal in synchronization with the falling edge of the second gate clock signal when the overlap signal is at the low level. A liquid crystal panel including a plurality of unit pixels defined in an area where a plurality of gate lines and data lines cross each other; A timing controller configured to generate gate and data control signals for driving the gate driver and the data driver; A driving voltage generator configured to receive the control signal and generate a plurality of driving voltages; A driving mode detector for outputting a line overlap signal by calculating and calculating the first and second gate clock signals for each activation period of the vertical synchronization start signal, and sequentially performing n (where n is a natural number) gate selection signals for selecting a gate line. A driving device including a gate driver configured to provide an N-th gate selection signal or an n-th gate selection signal as a carry signal, in response to the line overlap signal; And And a data driver for applying a data voltage to the data line. The method of claim 5, wherein The driving mode detector may include a signal calculator configured to output a line overlap signal by performing an operation on the first and second gate clock signals for each activation period of the vertical synchronization start signal; And And a signal reset unit configured to reset the line overlap signal to output a line overlap reset signal. The method of claim 5, wherein And outputs the N-th gate selection signal as a carry signal in synchronization with a falling edge of the first gate clock signal when the line overlap signal is at a high level. The method of claim 5, wherein And outputting the N-th gate selection signal as a carry signal in synchronization with the falling edge of the second gate clock signal when the overlap signal is at the low level.

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