KR20070077379A - Driving apparatus and liquid crystal display comprising the same - Google Patents

Abstract

A driving apparatus and a liquid crystal display device having the same are provided to suppress a horizontal stripe error on an LCD panel by masking an undesired vertical synchronization start signal during initial booting and resolution mode conversion processes. An apparatus for driving an LCD(Liquid Crystal Display) device includes a signal controller(600) and a signal masking unit(610). The signal controller generates gate and data control signals for driving an LCD panel. The signal masking unit includes a memory, a counter, and an output unit. The number of reference pixels in a vertical direction which is set according to the resolution of the LCD panel is stored on the memory. The counter counts the number of gate clock signals from application timing of a vertical synchronization start signal and provides a mask signal which represents end timing of the counting process. The output unit delivers the vertical synchronization start signal in response to the mask signal.

Description

Driving apparatus and liquid crystal display including the same {Driving apparatus and liquid crystal display comprising the same}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an internal block diagram of a signal mask unit according to an exemplary embodiment of the present invention.

3 is a view showing an output unit according to another embodiment of the present invention.

4 is a timing diagram illustrating an operation of a signal mask unit according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: liquid crystal panel 200: drive voltage generator

300: gate driver 400: gamma voltage generator

500: data driver 600: signal controller

610: signal mask portion 612: memory portion

614: gate clock signal counter section 616: output section

The present invention relates to a driving device and a liquid crystal display including the same, and more particularly, to a driving device and a liquid crystal display including the same that can prevent a horizontal line defect generated in the liquid crystal panel.

In general, a liquid crystal display (Liquid Crystal Display) is a flat panel display device that displays an image using a liquid crystal (Liquid Crystal), is thinner and lighter than other display devices, has the advantage of low power consumption and low driving voltage There is this.

In a liquid crystal display device, a liquid crystal layer is interposed between a color filter display panel on which a reference electrode and a color filter are formed, and a thin film transistor substrate on which a thin film transistor and a pixel electrode are formed, and different potentials are applied to the pixel electrode and the reference electrode. By forming an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance to represent the image.

In such a liquid crystal display, amorphous or polycrystalline silicon is used as a material of a thin film transistor. A liquid crystal display formed of polysilicon may have a high electron mobility, and thus, the driving unit may be easily integrated into a glass substrate. However, a liquid crystal display formed of amorphous silicon may have a low electron mobility. Only pixels are provided in the panel, and a driver chip is manufactured and used separately.

For example, if you want to implement the XGA resolution mode, you need to drive 1024 * 3 * 768 subpixels, so use 8 384 channel data driving chips and 3 256 channel gate driving chips, or Four data drive chips and six 256-channel gate drive chips are available. In the latter case, since the pitch of the gate lines is about three times the pitch of the data lines, dual gate driving is performed in which the gate driving chips constituting the gate driver are not mounted on one side and mounted on both sides and driven.

However, liquid crystal panels using dual gate driving are susceptible to horizontal line defects. Horizontal line defects are usually caused during boot-up or resolution mode switching. This is because the previous resolution data and the changed resolution data are not converted in units of frames at the time of mode switching, so that emergency frame data is input. As a result, the vertical synchronization start signal STV, which indicates the start of output of the gate-on pulse, should be generated once during one frame. At this time, the vertical synchronization start signal STV should be generated twice during one frame.

It is an object of the present invention to provide a driving device capable of preventing a horizontal line defect occurring in a liquid crystal panel.

Another object of the present invention is to provide a liquid crystal display including a driving device capable of preventing a horizontal line defect generated in a liquid crystal panel.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a driving apparatus including a signal controller configured to generate a gate and a data control signal for driving a liquid crystal panel, and a vertical reference pixel set according to a resolution mode of the liquid crystal panel. A memory unit in which a number is stored, a counting unit counting a gate clock signal by the number of reference pixels in the vertical direction from a time point at which the vertical synchronizing signal is output among the gate control signals, and providing a mask signal indicating the counting end; And an output unit configured to transfer the vertical synchronization signal in response to a mask signal.

In addition, the liquid crystal display according to another embodiment of the present invention for achieving the above technical problem, a liquid crystal panel including a plurality of unit pixels defined in a region where a plurality of gate lines and data lines intersect, the liquid crystal panel A signal controller for generating a gate and a data control signal for driving, a memory unit storing the number of reference pixels in a vertical direction set according to the resolution mode of the liquid crystal panel, and starting from a time point at which a vertical synchronization signal is output among the gate control signals A signal mask part including a counting part for counting a gate clock signal by a number of reference pixels in a vertical direction and providing a mask signal indicating the counting end, and an output part for transmitting the vertical synchronization signal in response to the mask signal; Receiving a signal to generate a plurality of driving voltages Such voltage generation unit, receives the driving voltage and a data driver for applying a data voltage to the gate driver and the data line is applied to the gate line.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 100, a driving voltage generator 200, a gate driver 300, a gamma voltage generator 400, and a data driver. 500, the signal controller 600.

The liquid crystal panel 100 is connected to a plurality of display signal lines G1-Gn and D1 -Dm as viewed in an equivalent circuit, and includes a plurality of unit pixels arranged in a matrix form.

Here, the display signal lines G1-Gn and D1-Dm include a plurality of gate lines G1-Gn transferring gate signals and data lines D1-Dm transferring data signals. The gate lines G1-Gn extend in the row direction and are substantially parallel to each other, and the data lines D1-Dm extend in the column direction and are substantially parallel to each other.

Each unit pixel includes a switching element Q connected to the display signal lines G1-Gn, D1-Dm, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. The sustain capacitor Cst may be omitted as necessary.

The switching element Q is provided on a TFT substrate, and is a three-terminal element whose control terminal and providing terminal are connected to the gate lines G1-Gn and the data lines D1-Dm, respectively, and the output terminal is a liquid crystal capacitor. (Clc) and sustain capacitor (Cst).

The liquid crystal capacitor Clc has a pixel electrode of a TFT substrate and a common electrode 24 of a color filter substrate as two terminals, and the liquid crystal layer between the two electrodes functions as a dielectric. The pixel electrode is connected to the switching element Q, and the common electrode is formed on the front surface of the color filter substrate and receives the common voltage Vcom. Here, the common electrode may be provided in the TFT substrate, in which case both electrodes are made in a linear or bar shape.

The sustain capacitor Cst is formed by superimposing a separate signal line (not shown) and a pixel electrode provided on the TFT substrate, and a predetermined voltage such as the common voltage Vcom is applied to the separate signal line (independent wiring method). However, the sustain capacitor Cst may be formed such that the pixel electrode 12 overlaps the front end gate line directly above the insulator (shear gate method).

On the other hand, in order to implement color display, each unit pixel should be able to display color, which is possible by providing a red, green, or blue color filter in a region corresponding to the pixel electrode. Here, the color filter can be formed in the corresponding region of the color filter substrate, and can also be formed above or below the pixel electrode of the TFT substrate.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the TFT substrate and the color filter substrate of the liquid crystal panel 100.

The driving voltage generator 200 generates a plurality of driving voltages. For example, the driving voltage generator 200 generates a gate on voltage Von, a gate off voltage Voff, and a common voltage Vcom.

The gate driver 300 is connected to the gate lines G1-Gn of the liquid crystal panel 100 to receive a gate signal formed by a combination of a gate on voltage Von and a gate off voltage Voff from the outside. Applied to Gn).

The gamma voltage generator 400 may generate two sets of gamma voltages related to transmittance of a unit pixel. That is, one of the two sets is the positive voltage, and the other is the negative voltage. The positive voltage and the negative voltage mean voltages whose polarities of the data voltages are opposite to the common voltage Vcom, and are alternately provided to the liquid crystal panel during inversion driving.

The data driver 500 is connected to the data lines D1-Dm of the liquid crystal panel 100, and generates a plurality of gray voltages based on the plurality of gamma voltages provided from the gamma voltage generator 400. The gray level voltage is selected and applied to the unit pixel as a data signal, and is usually composed of a plurality of integrated circuits.

The signal controller 600 generates control signals for controlling operations of the gate driver 300 and the data driver 500, and provides the corresponding control signals to the gate driver 300 and the data driver 500.

The signal mask unit 610 masks and outputs a vertical synchronization start signal STV that indicates the start of output of the gate-on pulse among control signals for controlling the operation of the gate driver. The description thereof will be described in detail with reference to FIG. 2.

Hereinafter, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 controls RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync. ), A main clock MCLK, and a data enable signal DE are provided. The signal controller 600 generates a gate control signal CONT1, a data control signal CONT2, and the like based on the control signal, and appropriately processes the image signals R, G, and B according to the operating conditions of the liquid crystal panel 100. After that, the gate control signal CONT1 is provided to the gate driver 300, and the data control signal CONT2 and the processed image signals R ', G', and B 'are provided to the data driver 500.

Here, the gate control signal CONT1 may be a vertical synchronization start signal STV indicating the start of output of the gate on pulse (gate on voltage section), a gate clock signal CPV controlling the output timing of the gate on pulse, and a gate on. An output enable signal OE or the like that defines the width of the pulse.

The data control signal CONT2 is a horizontal synchronization start signal STH indicating the start of the image data R ', G', and B 'and a load signal LOAD for applying a corresponding data voltage to the data lines D1-Dm. ), An inverted signal (RVS) and a data clock signal (inverting the polarity of the data voltage relative to the common voltage (VCOM) (hereinafter referred to as 'polarity of the data voltage by reducing the polarity of the data voltage for the common voltage') HCLK) and the like.

The data driver 500 receives image data R ′, G ′, and B ′ corresponding to one unit pixel in a row according to the data control signal CONT2 from the signal controller 600. By selecting the gray scale voltages corresponding to the image data R ', G', and B ', the image data R', G ', and B' are converted into the corresponding data voltages.

The gate driver 300 applies a gate-on voltage Von to the gate lines G1-Gn according to the gate control signal CONT1 from the signal controller 600, and is connected to the gate lines G1-Gn. Turn on (Q).

While a gate-on voltage Von is applied to one gate line G1-Gn, and a row of switching elements Q connected thereto is turned on (this period is '1H' or '1 horizontal period'). And the same as one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 transmits each data voltage to the corresponding data line D1-Dm. Supply. The data voltage supplied to the data lines D1-Dm is applied to the corresponding unit pixel through the turned-on switching element Q.

The liquid crystal molecules change their arrangement according to the electric field generated by the pixel electrode and the common electrode, and thus the polarization of light passing through the liquid crystal layer changes. This change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the TFT substrate and the color filter substrate.

In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G1 -Gn during one frame to apply data voltages to all the unit pixels. When one frame ends, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each unit pixel is opposite to that of the previous frame ('frame' reversal'). In this case, the polarity of the data voltage flowing through one data line may be changed ('line inversion') or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame ( 'Dot reversal').

2 is an internal block diagram of a signal mask unit according to an exemplary embodiment of the present invention. 3 is a view showing an output unit according to another embodiment of the present invention.

As shown in FIG. 2, the signal mask unit 610 according to an embodiment of the present invention includes a memory unit 612, a gate clock signal counter unit 614, and an output unit 616.

The memory unit 612 stores the number of reference pixels in the horizontal and vertical directions corresponding to the resolution of the liquid crystal panel. Here, the number of reference pixels may be set differently according to the resolution of the liquid crystal panel. For example, the XGA resolution is 1024 × 768, the number of reference pixels in the horizontal direction is 1024, and the number of reference pixels in the vertical direction is 768.

The gate clock signal counter 614 counts the number of gate clock signals CPV for controlling the output timing of the gate on pulses from the time point at which the vertical synchronization start signal STV indicating the output of the gate on pulses is output. . At this time, the gate clock signal counter unit 614 counts the number of gate clock signals while comparing the number of vertical reference pixels stored in the memory unit 612. If the resolution mode of the liquid crystal panel is set to XGA, the number of reference pixels in the vertical direction is set to 768. Accordingly, the gate clock signal counter unit 614 counts the number of gate clock signals until the gate clock signal becomes 768. In addition, the gate clock signal counter 614 outputs a mask signal STV_mask indicating the end of counting of the gate clock signal. Here, a low level signal is output while counting the number of gate clock signals, and a high level signal is output when the number of gate clock signals is counted by the set number of vertical reference pixels, and the operation is repeated. .

The output unit 616 performs a logical operation on the vertical synchronization start signal STV generated in the signal controller 600 and the mask signal STV_mask output from the gate clock signal counter 614. In this case, the output unit 616 includes an AND gate, and outputs the final vertical synchronization start signal STV ′ by ANDing the vertical synchronization start signal STV and the mask signal STV_mask. In this case, as shown in FIG. 3, the output unit 616 may be implemented as a switching device in which the mask signal switching device is turned on in response to the mask signal STV_mask to transfer the vertical synchronization start signal. For example, the vertical synchronization start signal STV is transmitted only when the mask signal STV_mask is at a high level.

4 is a timing diagram illustrating an operation of a signal mask unit according to an exemplary embodiment of the present invention.

The signal controller 600 receives the data enable signal DE from an external graphic controller, and outputs a vertical synchronization start signal STV for instructing the output of the gate-on pulse after a predetermined time delay. Here, one signal is output to one frame of the vertical synchronization start signal STV. However, as shown in FIG. 4, when the frame data C smaller than the number of vertical reference pixels of the liquid crystal panel is input when the resolution mode of the liquid crystal panel is switched, the vertical synchronization start signal STV is generated twice during one frame. Done. For example, in FIG. 4, the section “A” represents a state where the resolution mode of the liquid crystal panel is set to SXGA, and the section “B” represents a state where the resolution mode of the liquid crystal panel is switched to XGA. Here, when the resolution mode is XGA, the number of reference pixels in the vertical direction is 768. Therefore, when more than 768 reference pixels in the vertical direction are input to one frame, the vertical synchronization start signals C and D are generated twice during one frame.

To solve this problem, the signal mask unit 610 of the present invention counts the number of gate clock signals CPV by the number of vertical reference pixels set according to the resolution mode of the liquid crystal panel from the time when the vertical synchronization start signal STV is output. do. In this case, a mask signal STV_mask indicating a counting state of the gate clock signal is output, and a low level signal is output in a section counting the number of gate clock signals, and counting of the gate clock signal is completed by the set number of reference pixels. In the section, a high level signal is output. Then, the AND operation is performed on the original vertical synchronization start signal STV and the mask signal STV_mask to generate a final vertical synchronization start signal STV '. Therefore, the vertical synchronization start signal E generated by inputting frame data smaller than the number of reference pixels in the vertical direction when switching the resolution mode of the liquid crystal panel may be eliminated. For this reason, the horizontal line defect which arises in a liquid crystal panel can be prevented.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

According to the driving device and the liquid crystal display including the same according to the present invention as described above, the liquid crystal panel generates masks by masking unwanted vertical synchronization start signals (STVs) generated during initial setting of the liquid crystal panel and switching between resolution modes. It can prevent the horizontal line defect.

Claims (8)

A signal controller configured to generate a gate and data control signal for driving the liquid crystal panel; And The memory unit stores the number of reference pixels in the vertical direction set according to the resolution mode of the liquid crystal panel, and counts the gate clock signal by the number of the reference pixels in the vertical direction from the time point at which the vertical synchronization start signal is output among the gate control signals. And a signal mask unit including a counting unit providing a mask signal indicating the counting end and an output unit transmitting the vertical synchronization start signal in response to the mask signal. The method of claim 1, The mask signal has a low level in a section counting the gate clock signal and a high level in a section in which counting of the gate clock signal ends. The method of claim 1, And the output unit performs an AND operation on a mask signal and the vertical synchronization start signal. The method of claim 1, And the output unit includes a switching device that is turned on in response to a mask signal to transfer the vertical synchronization start signal. A liquid crystal panel including a plurality of unit pixels defined in a region where the plurality of gate lines and the data lines cross each other; A signal controller configured to generate a gate and data control signal for driving the liquid crystal panel; The memory unit stores the number of reference pixels in the vertical direction set according to the resolution mode of the liquid crystal panel, and counts the gate clock signal by the number of the reference pixels in the vertical direction from the time point at which the vertical synchronization start signal is output among the gate control signals. A signal mask unit including a counting unit providing a mask signal indicating the counting end and an output unit transmitting the vertical synchronization start signal in response to the mask signal; A driving voltage generator configured to receive the control signal and generate a plurality of driving voltages; A gate driver which receives the driving voltage and applies it to the gate line; And And a data driver for applying a data voltage to the data line. The method of claim 5, The mask signal has a low level in a section counting the gate clock signal and a high level in a section in which counting of the gate clock signal ends. The method of claim 5, And the output unit performs an AND operation on a mask signal and the vertical synchronization start signal. The method of claim 5, And the output unit includes a switching element that is turned on in response to a mask signal to transfer the vertical synchronization start signal.

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