KR20080017988A - Driving apparatus and liquid crystal display comprising the same - Google Patents

Abstract

An LCD(Liquid Crystal Display) device and an LCD driver are provided to adjust an output delay time of a data voltage by adjusting a charge sharing time by using an output delay time regulator. An LCD driver includes a timing controller(600) and an output delay time regulator(520). The timing controller generates a data load signal which is used to apply data voltages to respective data lines of an LCD panel. The delay time regulator outputs the data voltage in response to the data load signal. A charge sharing time is defined as a duration, when the data load signal is activated. An output delay time is defined as an interval from an activation timing of the data load signal to a timing, when the data voltage reaches a predetermined output voltage level. The output delay time regulator adjusts the charge sharing time to match the output delay time with a target output delay time.

Description

Driving apparatus and liquid crystal display including the same {Driving apparatus and liquid crystal display comprising the same}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a diagram illustrating a data voltage output from a data driver according to an exemplary embodiment of the present invention.

3 is an internal block diagram of an output delay time adjusting unit according to an exemplary embodiment of the present invention.

4 is an internal block diagram of an operation unit according to an embodiment of the present invention.

5 is an internal block diagram of a data load signal output unit according to an exemplary embodiment of the present invention.

6 is a diagram illustrating a data load signal whose activation time is adjusted according to one embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: liquid crystal panel 200: voltage generator

300: gate driver 400: gamma voltage generator

500: data driver 520: output delay time adjusting unit

522: voltage comparator 524: clock counter

526: calculator 528: data load signal controller

532: subtractor 534: adder

536: selection signal output section 538: multiplexer

542: NAND gate 546: register

552: charge sharing control signal 554: data load signal output unit

600: timing controller

The present invention relates to a driving apparatus and a liquid crystal display including the same, and more particularly, to a driving apparatus for adjusting the output delay time of a data voltage to be the same as the target output delay time and a liquid crystal display including the same.

In general, a liquid crystal display includes a TFT substrate on which a thin film transistor (TFT) for switching each pixel is formed, and a color filter substrate on which a color pixel is formed, and a TFT substrate and a color filter substrate. It consists of a sealed liquid crystal layer. The liquid crystal constituting the liquid crystal layer is characterized in that the arrangement is changed according to the electric field applied between the two substrates, and the light transmittance (transmissive index) is changed according to the arrangement.

The liquid crystal display includes a liquid crystal panel, a voltage generator, a gate driver, a gamma voltage generator, a data driver, and a timing controller. In this case, the data driver outputs a data voltage through an internal amplifier.

Recently, the output delay time of the data voltage output from the data driving chip has become an issue. The data driving chip connected to the liquid crystal panel may be manufactured by a plurality of chips having different output delay times, although different manufacturers may use the same. At this time, the design delay of the amplifier is different for each manufacturer, the output delay time of the data voltage is determined according to the characteristics of the amplifier. Therefore, when a manufacturer drives the liquid crystal panel using different data driving chips, variations in the output delay time may occur in each data driving chip, and thus the quality of the liquid crystal panel may not be uniform.

An object of the present invention is to provide a driving apparatus for adjusting an output delay time of a data voltage to be equal to a target output delay time.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display including a driving device that adjusts an output delay time of a data voltage to be equal to a target output delay time.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a driving apparatus including a timing controller for generating a data load signal informing that a corresponding data voltage is applied to each data line of a liquid crystal panel, and the data load signal. A data driver that outputs the data voltage in response, wherein the charge sharing time is defined as the time at which the data load signal is activated, and the output delay time is at which the data voltage reaches a predetermined output voltage level from the time of activation of the data load signal. When defined as up to a time point, the output delay time adjusting unit for adjusting the charge sharing time to adjust the output delay time equal to the target output delay time.

According to an exemplary embodiment of the present invention, a liquid crystal panel includes a plurality of unit pixels defined in an area where a plurality of gate lines and a data line intersect, and each data of the liquid crystal panel. A timing controller configured to generate a data load signal indicative of applying a corresponding data voltage to a line, a driving voltage generator configured to receive the control signal and generate a plurality of driving voltages, and receive the driving voltage and apply the applied voltage to the gate line The data driver outputs the data voltage in response to a gate driver and the data load signal, and a charge sharing time is defined as a time at which the data load signal is activated, and an output delay time is determined by the data voltage from the time at which the data load signal is activated. When defined as until the output voltage level is reached, And an output delay time adjusting unit for adjusting the pre-charge sharing time to adjust the output delay time to be equal to the target output delay time.

Specific details of other embodiments are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 100, a voltage generator 200, a gate driver 300, a gamma voltage generator 400, and a data driver ( 500, the timing controller 600.

The liquid crystal panel 100 is connected to a plurality of display signal lines G1-Gn and D1 -Dm as viewed in an equivalent circuit, and includes a plurality of unit pixels arranged in a matrix form.

Here, the display signal lines G1-Gn and D1-Dm include a plurality of gate lines G1-Gn transferring gate signals and data lines D1-Dm transferring data signals. The gate lines G1-Gn extend in the row direction and are substantially parallel to each other, and the data lines D1-Dm extend in the column direction and are substantially parallel to each other.

Each unit pixel includes a switching element Q connected to the display signal lines G1-Gn, D1-Dm, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. The sustain capacitor Cst may be omitted as necessary.

The switching element Q is provided on the TFT substrate, and the control terminal and the input terminal thereof are connected to the gate lines G1-Gn and the data lines D1-Dm, respectively, and the output terminal is a liquid crystal capacitor. (Clc) and sustain capacitor (Cst).

The liquid crystal capacitor Clc has a pixel electrode of a TFT substrate and a common electrode of a color filter substrate as two terminals, and the liquid crystal layer between the two electrodes functions as a dielectric. The pixel electrode is connected to the switching element Q, and the common electrode is formed on the front surface of the color filter substrate and receives the common voltage Vcom. Here, the common electrode may be provided in the TFT substrate, in which case both electrodes are made in a linear or bar shape.

The sustain capacitor Cst is formed by superimposing a separate signal line (not shown) and a pixel electrode provided on the TFT substrate, and a predetermined voltage such as the common voltage Vcom is applied to the separate signal line (independent wiring method). However, the sustain capacitor Cst may be formed such that the pixel electrode overlaps the front end gate line directly above the insulator (shear gate method).

On the other hand, in order to implement color display, each unit pixel should be able to display color, which is possible by providing a red, green, or blue color filter in a region corresponding to the pixel electrode. Here, the color filter can be formed in the corresponding region of the color filter substrate, and can also be formed above or below the pixel electrode of the TFT substrate.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the TFT substrate and the color filter substrate of the liquid crystal panel 100.

The voltage generator 200 generates a plurality of driving voltages. For example, the voltage generator 200 generates a gate on voltage Von, a gate off voltage Voff, and a common voltage Vcom.

The gate driver 300 is connected to the gate lines G1-Gn of the liquid crystal panel 100 to receive a gate selection signal formed of a combination of a gate on voltage Von and a gate off voltage Voff from the outside. -Applied to Gn).

The gamma voltage generator 400 may generate two sets of gamma voltages related to transmittance of a unit pixel. In other words, one of the two sets is the positive data voltage and the other is the negative data voltage. The positive data voltage and the negative data voltage mean voltages whose polarities of the data voltages are opposite to the common voltage Vcom, and are alternately provided to the liquid crystal panel during inversion driving.

The data driver 500 is connected to the data lines D1-Dm of the liquid crystal panel 100, and generates a plurality of data voltages based on the plurality of gamma voltages provided from the gamma voltage generator 400. The data voltage is selected and applied to the unit pixel as a data signal, and is usually composed of a plurality of integrated circuits. In addition, the data driver 500 adjusts the charge sharing time of the data voltage in response to the data load signal TP provided from the timing controller 600 to adjust the output delay time of the data voltage to be equal to the target output delay time. An output delay time adjusting unit 520 is included. Detailed description thereof will be described with reference to FIG. 2.

The timing controller 600 generates control signals for controlling operations of the driving apparatus 300 and the data driver 500, and provides the corresponding control signals to the driving apparatus 300 and the data driver 500.

Hereinafter, the display operation of the liquid crystal display will be described in more detail.

The timing controller 600 controls an RGB image signal R, G, and B and an input control signal, for example, a vertical sync signal Vsync and a horizontal sync signal, from an external graphic controller (not shown). Hsync, main clock MCLK, and data enable signal DE are provided. The timing controller 600 generates a gate control signal CONT1, a data control signal CONT2, and the like based on the input control signal, and appropriately matches the image signals R, G, and B with the operating conditions of the liquid crystal panel 100. After processing, the gate control signal CONT1 is provided to the driving device 300, and the data control signal CONT2 and the processed image signals R ', G', and B 'are provided to the data driver 500.

Here, the gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate on pulse (gate on voltage section), a gate clock signal CPV controlling the output timing of the gate on pulse, and a gate on. An output enable signal OE or the like that defines the width of the pulse. Among these, the output enable signal OE and the gate clock signal CPV are provided to the voltage generator 200.

The data control signal CONT2 is a horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and a load signal for applying a corresponding data voltage to the data lines D1-Dm. TP), the polarity signal (POL) and the data clock signal (inverting the polarity of the data voltage with respect to the common voltage (VCOM) (hereinafter referred to as 'polarity of the data voltage by reducing the polarity of the data voltage for the common voltage') HCLK) and the like.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of unit pixels according to the data control signal CONT2 from the timing controller 600. By selecting data voltages corresponding to the image data R ', G', and B ', the image data R', G ', and B' are converted into the corresponding data voltages.

The driving device 300 applies a gate-on voltage Von to the gate lines G1-Gn in response to the gate control signal CONT1 from the timing controller 600, and is connected to the gate lines G1-Gn. Turn on (Q).

While a gate-on voltage Von is applied to one gate line G1-Gn, and a row of switching elements Q connected thereto is turned on (this period is '1H' or '1 horizontal period'). And the same as one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 transmits each data voltage to the corresponding data line D1-Dm. Supply. The data voltage supplied to the data lines D1-Dm is applied to the corresponding unit pixel through the turned-on switching element Q.

The liquid crystal molecules change their arrangement according to the electric field generated by the pixel electrode and the common electrode, and thus the polarization of light passing through the liquid crystal layer changes. This change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the TFT substrate and the color filter substrate.

In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G1 -Gn during one frame to apply data voltages to all the unit pixels. When one frame ends, the next frame starts and the state of the polarity signal POL applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each unit pixel is opposite to that of the previous frame ('frame' reversal'). In this case, the polarity of the data voltage flowing through one data line may be changed ('line inversion') or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the polarity signal POL within one frame ( 'Dot reversal').

2 is a diagram illustrating a data voltage output from a data driver according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the timing controller 600 according to an exemplary embodiment of the present invention loads data informing that the data voltage ic_output is applied to each of the data lines D1 to Dm of the liquid crystal panel 100. The signal TP is generated and output to the data driver 500. Then, the data driver 500 outputs a data voltage in response to the data load signal. Here, the data voltage is defined as the charge sharing time (B) defined as the time (A) at which the data load signal is activated, and from the time of activation of the data load signal to the time when the data voltage reaches 90% of the output voltage. Output delay time (C).

In the present invention, the charge sharing time of the data voltage is adjusted to adjust the output delay time to be equal to the target output delay time.

3 is an internal block diagram of an output delay time adjusting unit according to an embodiment of the present invention, FIG. 4 is an internal block diagram of an operation unit according to an embodiment of the present invention, and FIG. 5 is an embodiment of the present invention. 6 is a block diagram illustrating an internal data load signal output unit, and FIG. 6 is a diagram illustrating a data load signal whose activation time is adjusted according to an embodiment of the present invention.

Referring to FIG. 3, the output delay time adjusting unit 520 according to an embodiment of the present invention includes a voltage comparator 522, a clock counter 524, an operation unit 526, and a data load signal output unit 528. It includes.

The voltage comparator 522 compares the data voltage ic_output and the reference voltage Vref output from the data driver 500, and outputs a voltage comparison signal voltage_com as a comparison result. That is, the voltage comparator 522 outputs a voltage comparison signal when the data voltage and the reference voltage become equal. Here, the reference voltage is about 90% similar to the magnitude of the data voltage output from the data driver, and this voltage is suitable as the reference voltage because it is a constant voltage provided from the outside.

The clock counter unit 524 receives the data load signal TP and the voltage comparison signal voltage_com to determine the first clock number clk_num1 from the time when the data load signal is activated to the time when the data voltage and the reference voltage are the same. Output At this time, the clock counter unit 534 starts counting from the rising edge of the data load signal and ends counting when the voltage comparison signal is input.

The calculator 526 calculates a third clock number clk_num3 corresponding to a difference between the first clock number clk_num1 and the second clock number clk_num2 representing the target output delay time, and shares the third charge with the reference charge. The fourth clock number clk_num4 representing the time is added together to output a fifth clock number clk_num5 representing the charge sharing time.

Referring to FIG. 4, the calculator 526 includes a subtractor 532, an adder 534, a select signal output unit 536, a multiplexer 538, a NAND gate 542, and a register 546.

The subtractor 532 calculates a third clock number clk_num3 corresponding to a difference between the first clock number clk_num1 and the second clock number clk_num2 representing the target output delay time. At this time, when the value of the third clock number is a positive value, this indicates that the output delay time of the data voltage is slow based on the number of second clocks. When the value of the third clock number is a negative value, the second clock number is used. On the basis of this, the output delay time of the data voltage is fast. When the value of the third clock number is 0, this indicates that the output delay time of the second clock number and the data voltage is the same.

The adder 534 adds the third clock number clk_num3 and the fourth clock number clk_num4 indicating the reference charge sharing time to output a fifth clock number clk_num5 indicating the charge sharing time.

The selection signal output unit 536 combines the data load signal TP and the enable signal data_en for operating the data driver to output the selection signal sel. At this time, the selection signal sel is output as a logic low ('0') or logic high ('1') signal.

The multiplexer 538 outputs one of the fourth clock number clk_num4 and the fifth clock number clk_num5 as the selection output signal mux_out according to the selection signal sel. Here, when the selection signal sel is a logic low '0', the fourth clock number clk_num4 representing the reference charge sharing time is output as the selection output signal mux_out. In addition, when the selection signal sel is logic high ('1'), the fifth clock number clk_num5 representing the charge sharing time is output as the selection output signal mux_out.

The NAND gate 542 receives a predetermined high bit of the third clock number clk_num3 and the ground voltage GND, and outputs an operation control signal op_con indicating the completion of the calculation. For example, it is assumed that the third clock number clk_num3, which is the output signal of the adder 532, is 8 bits, and the operation control signal op_con outputs '1' only when the upper six bits are "000000". do.

The register 546 stores the selection output signal mux_out output from the multiplexer 538 and outputs the selection output signal mux_out as a register output signal reg_out when the operation control signal op_con is input. For example, the register 548 outputs data stored only when the operation control signal op_con is '1'.

Here, the second clock number clk_num2 representing the target delay time and the fourth clock number clk_num4 representing the reference charge sharing time are values generated in the data driver 500.

In the present invention, the subtractor 532 and the adder 534 change the charge sharing time by adding or subtracting the output delay time of the data voltage ic_output output from the data driver 500 to be different from the target output delay time. . The value determined by the subtractor 532 and the adder 534, that is, the fifth clock number clk_num5, indicates the end point of the charge sharing time B as shown in FIG. 2. In this case, the time point at which the charge sharing time ends is the same as the time point at which the data load signal TP is deactivated. The operation unit 526 is repeatedly operated until the output delay time of the data voltage becomes equal to the target output delay time.

Referring to FIG. 5, the data load signal output unit 528 includes a charge sharing control signal providing unit 552 and a charge sharing signal output unit 554.

As shown in FIG. 6, the charge sharing control signal providing unit 552 provides a charge sharing control signal charge_sharing_control that is activated at a time corresponding to the fifth clock number clk_num5.

The charge sharing signal output unit 554 receives the charge sharing control signal charge_sharing_control and the data load signal TP as shown in FIG. 6, and outputs a data load signal TP_ADJ whose activation time is adjusted. In this case, the data load signal TP_ADJ whose activation time is adjusted is activated at the rising edge of the data load signal TP and is deactivated at the rising edge of the charge sharing control signal charge_sharing_control.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

As described above, the driving apparatus and the liquid crystal display including the same according to the present invention include an output delay time adjusting unit inside the data driving unit, so that even if the manufacturer uses another data driving chip, the charge sharing time is adjusted to adjust the output delay time of the data voltage. Can be easily adjusted.

Claims (20)

A timing controller configured to generate a data load signal indicative of applying a corresponding data voltage to each data line of the liquid crystal panel; And A data driver that outputs the data voltage in response to the data load signal, wherein a charge sharing time is defined as a time at which the data load signal is activated, and an output delay time is defined by the data voltage from a time point at which the data load signal is activated. And an output delay time adjusting unit configured to adjust the charge sharing time to be equal to a target output delay time by adjusting the charge sharing time when the output voltage level is reached. The method of claim 1, The data driver, A voltage comparison unit comparing the data voltage with a reference voltage and outputting a voltage comparison signal indicating a comparison result; A clock counter configured to receive the data load signal and the voltage comparison signal and output a first clock number from an activation time of the data load signal to a time when the data voltage and the reference voltage are equal to each other; The third clock number corresponding to the difference between the first clock number and the second clock number representing the target output delay time is calculated, and the third clock number and the fourth clock number representing the reference charge sharing time are added together. An operation unit for outputting a fifth clock number representing the charge sharing time; A data load signal configured to provide a charge sharing control signal activated at a time corresponding to the fifth clock number, receive the charge sharing control signal and the data load signal, and output a data load signal whose activation time is adjusted; Drive device including an adjustment. The method of claim 2, And the reference voltage is provided from the outside, and has a time of reaching 90% of the output voltage from the start of the sharing time. The method of claim 2, The calculation unit, A subtractor for calculating a third clock number corresponding to a difference between the first clock number and a second clock number representing a target output delay time; An adder for adding the third clock number and the fourth clock number representing the reference charge sharing time to output the fifth clock number representing the charge sharing time; A selection signal output unit configured to output a selection signal by combining the data load signal and an enable signal for operating the data driver; A multiplexer configured to output one of the fourth clock number and the fifth clock number as a selection output signal according to the selection signal; A NAND gate receiving a predetermined high order bit among the third clock numbers and a ground voltage and outputting an operation control signal indicating completion of the operation; And And a register for outputting the selection output signal when the operation control signal is input. The method of claim 4, wherein And when the value of the third clock number is a positive value, indicating that the output delay time of the data voltage is slow based on the second clock number. The method of claim 4, wherein And when the value of the third clock number is negative, indicating that the output delay time of the data voltage is fast based on the second clock number. The method of claim 4, wherein And when the value of the third clock number is zero, indicating that the output delay time of the second clock number and the data voltage is the same. The method of claim 4, wherein And a second clock number representing the target delay time and the reference charge sharing time are values generated inside the data driver. The method of claim 2, The data load signal adjusting unit, A charge sharing control signal providing unit configured to provide a charge sharing control signal activated at a time corresponding to the fifth clock number; And And a data load signal output unit configured to receive the charge sharing control signal and the data load signal and output a data load signal of which the activation time is adjusted. The method of claim 9, Wherein the activated time-controlled data load signal is activated at the rising edge of the data load signal and is deactivated at the rising edge of the charge sharing control signal. A liquid crystal panel including a plurality of unit pixels defined in an area where a plurality of gate lines and data lines cross each other; A timing controller configured to generate a data load signal indicative of applying a corresponding data voltage to each data line of the liquid crystal panel; A driving voltage generator configured to receive the control signal and generate a plurality of driving voltages; A gate driver which receives the driving voltage and applies it to the gate line; And The data voltage is output in response to the data load signal, a charge sharing time is defined as a time at which the data load signal is activated, and an output delay time is a predetermined output voltage level from the time at which the data load signal is activated. And a data driver including an output delay time adjusting unit adjusting the charge sharing time to equal the target output delay time by adjusting the charge sharing time. The method of claim 11, The data driver, A voltage comparison unit comparing the data voltage with a reference voltage and outputting a voltage comparison signal indicating a comparison result; A clock counter configured to receive the data load signal and the voltage comparison signal and output a first clock number from an activation time of the data load signal to a time when the data voltage and the reference voltage are equal to each other; The third clock number corresponding to the difference between the first clock number and the second clock number representing the target output delay time is calculated, and the third clock number and the fourth clock number representing the reference charge sharing time are added to the charge. An operation unit for outputting a fifth clock number representing a sharing time; A data load signal configured to provide a charge sharing control signal activated at a time corresponding to the fifth clock number, receive the charge sharing control signal and the data load signal, and output a data load signal whose activation time is adjusted; Liquid crystal display comprising a control unit. The method of claim 12, The reference voltage is provided from the outside, the liquid crystal display device having a time point of reaching 90% of the output voltage from the start time of the sharing time. The method of claim 12, The calculation unit, A subtractor for calculating a third clock number corresponding to a difference between the first clock number and a second clock number representing a target output delay time; An adder for adding the third clock number and the fourth clock number representing the reference charge sharing time to output the fifth clock number representing the charge sharing time; A selection signal output unit configured to output a selection signal by combining the data load signal and an enable signal for operating the data driver; A multiplexer configured to output one of the fourth clock number and the fifth clock number as a selection output signal according to the selection signal; A NAND gate receiving a predetermined high order bit among the third clock numbers and a ground voltage and outputting an operation control signal indicating completion of the operation; And And a register configured to output the selection output signal when the operation control signal is input. The method of claim 14, And when the value of the third clock number is a positive value, indicating that the output delay time of the data voltage is slow based on the second clock number. The method of claim 14, And when the value of the third clock number is negative, indicating that the output delay time of the data voltage is fast based on the second clock number. The method of claim 14, And when the value of the third clock number is zero, indicating that the output delay time of the second clock number and the data voltage is the same. The method of claim 14, And a second clock number representing the target delay time and the reference charge sharing time are values generated inside the data driver. The method of claim 12, The data load signal adjusting unit, A charge sharing control signal providing unit configured to provide a charge sharing control signal activated at a time corresponding to the fifth clock number; And And a data load signal output unit configured to receive the charge sharing control signal and the data load signal and output a data load signal of which the activation time is adjusted. The method of claim 19, And the data load signal whose activation time is adjusted is activated at the rising edge of the data load signal and inactivated at the rising edge of the charge sharing control signal.

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