KR20070071955A - Liquid crystal display and the method of driving the same - Google Patents

Abstract

A liquid crystal display and a driving method thereof are provided to improve horizontal line defect due to an external abnormal data enable signal by controlling an inversion driving signal. In a liquid crystal display, there is provided a liquid crystal panel. A timing control unit(100) generates an error control signal by inspecting external data enable signals, and supplies an inversion driving signal by controlling the inversion driving signal in response to the error control signal. A data driving unit(400) generates a data driving signal having a positive/negative polarity based on a common voltage by the inversion driving signal, and supplies the data driving signal to the liquid crystal panel. The timing control unit includes an inspecting unit(110) for generating the error control signal by detecting an abnormal data enable signal from the data enable signals, and a control unit(120) for generating first and second pulse signals to identify the start point and the end point of the error control signal and fixing the inversion driving signal from the first pulse signal to the second pulse signal.

Description

Liquid crystal display and the method of driving the same {Liquid crystal display and the method of driving the same}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display of FIG. 1.

3 is a block diagram of the timing controller of FIG. 1.

4 is a waveform diagram of signals of FIG. 3.

5 is an output waveform diagram of a data driver by the inversion driving signal of FIG. 4.

(Explanation of symbols for the main parts of the drawing)

100: timing control unit 110: inspection unit

120: control unit 200: drive voltage generation unit

300: gate driver 400: data driver

450: gamma voltage generator 500: liquid crystal panel

600: liquid crystal display

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof that can improve horizontal line defects.

In recent years, liquid crystal displays have been in the spotlight as display means.

A liquid crystal display device applies an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two display panels, adjusts the intensity of the electric field, and controls the amount of light transmitted through the display panel to obtain a desired image signal. Device.

In the liquid crystal display, a plurality of gate lines parallel to each other and a plurality of data lines insulated from and intersecting the gate lines are formed on the display panel, and an area surrounded by the gate lines and the data lines defines one pixel. Thin film transistors (TFTs) are formed at the intersections of the gate lines and the data lines of each pixel.

In addition, in order to reduce the size, a structure MB4 in which a gate driver attached to the liquid crystal panel is directly configured in the liquid crystal panel is adopted.

The gate driving circuit integrated in the liquid crystal panel is composed of a shift register, and one more shift register is formed and integrated with the gate lines of the liquid crystal panel. In addition, an additional circuit is configured outside the liquid crystal panel, that is, a printed circuit board, to operate by receiving the vertical start signal STV, the gate clock CPV, and the output enable signal OE, as in the conventional gate driver.

This structure does not have the ability to mask the output here. Therefore, the output time of the data driver and the gate off time of the liquid crystal panel must be precisely matched with a specific gap. In order to accurately output the data driver and the gate-off time of the liquid crystal panel, input of a regular data enable signal DE is always required.

However, it is less likely that an abnormal data enable signal will occur in a system that provides a data enable signal, and the abnormal data enable signal may cause a horizontal line defect in the liquid crystal panel.

An object of the present invention is to provide a liquid crystal display device which can improve a horizontal line defect.

Another object of the present invention is to provide a method of driving such a liquid crystal display.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an exemplary embodiment of the present invention, a liquid crystal display device generates an error control signal by inspecting a liquid crystal panel and a data enable signal provided from the outside, and generates an inversion driving signal by the error control signal. The control unit includes a timing control unit for controlling and providing the data driver to the data driver, and a data driver for generating a data driving signal having positive / negative polarity based on a common voltage based on the inversion driving signal and providing the same to the liquid crystal panel.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display, the method comprising: generating an error control signal by detecting an abnormal data enable signal among data enable signals provided from the outside; Generating first and second pulse signals that distinguish the beginning and the end of the control signal, fixing the inversion drive signal for a time period from the first pulse signal to the second pulse signal, and outputting a fixed inversion drive signal; And providing a data driving signal having positive / negative polarity based on the common voltage by the inversion driving signal and providing the same to the liquid crystal panel.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display of FIG. 1.

1 and 2, the liquid crystal display 600 may include a liquid crystal panel 500, a timing controller 100, a driving voltage generator 200, a gate driver 300, a data driver 400, and a gamma voltage. It is configured to include a generator 450.

In the equivalent circuit, the liquid crystal panel 500 includes a plurality of display signal lines G1 to Gn and D1 to Dm, and a plurality of unit pixels connected thereto and arranged in a matrix.

The display signal lines G1 to Gn and D1 to Dm include a plurality of gate lines G1 to Gn for transmitting gate signals and a plurality of data lines D1 to Dm for transmitting data signals. The gate lines G1 to Gn extend in the row direction and are substantially parallel to each other, and the data lines D1 to Dm extend in the column direction and are substantially parallel to each other.

Each unit pixel includes a switching element Q connected to the display signal lines G1 to Gn and D1 to Dm, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. The sustain capacitor Cst may be omitted as necessary.

The switching element Q has two terminals, the pixel electrode PE of the first display panel and the common electrode CE of the second display panel, and the liquid crystal layer (not shown) interposed between the two electrodes PE and CE is a dielectric material. Function as. The pixel electrode PE is connected to the switching element Q, and the common electrode CE is formed on the entire surface of the second display panel to receive the common voltage Vcom. In addition, the common electrode CE may be provided in the first display panel. In this case, both electrodes PE and CE may be formed in a linear or bar shape.

The storage capacitor Cst is formed by overlapping a separate signal line (not shown) and the pixel electrode PE provided on the first display panel, and a predetermined voltage such as the common voltage Vcom is applied to the separate signal line (independence). Wiring method). In addition, the storage capacitor Cst may be formed such that the pixel electrode PE overlaps the front-end gate line directly above the insulator (shear gate method).

Meanwhile, in order to implement color display, each unit pixel should display a color, which is possible by providing a red, green, or blue color filter CF in a region corresponding to the pixel electrode PE. The color filter CF may be formed in a corresponding region of the second display panel, or may be formed above or below the pixel electrode PE of the first display panel.

In addition, a polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the first display panel and the second display panel of the liquid crystal panel 500.

In order to provide driving and control signals to the liquid crystal panel 500, the liquid crystal display 600 may include a timing controller 100, a driving voltage generator 200, a gate driver 300, a data driver 400, and a gamma voltage. Generation unit 450;

The timing controller 100 generates control signals for controlling operations of the gate driver 200 and the data driver 300, and provides the corresponding control signals to the gate driver 200 and the data driver 300.

In addition, the timing controller 100 may detect an abnormal data enable signal DE from among the data enable signals DE provided from the outside and detect the abnormal data enable signal DE to generate an error control signal. And a controller 120 generating first and second pulse signals to control the inversion driving signal.

The driving voltage generator 200 generates a plurality of driving voltages and provides them to the gate driver 300 and the liquid crystal panel 500. The driving voltage generated by the driving voltage generator 200 includes, for example, a gate on voltage Von, a gate off voltage Voff, a common voltage Vcom, and the like.

The gate driver 300 is connected to the gate lines G1 to Gn formed in the liquid crystal panel 500, and is a combination of the gate-on voltage Von and the gate-off voltage Voff provided from the driving voltage generator 200. The formed gate driving signal is provided to the gate lines G1 to Gn.

The data driver 400 is connected to the data lines D1 to Dm formed in the liquid crystal panel 500, and generates and generates a plurality of gray voltages based on the plurality of gamma voltages provided from the gamma voltage generator 450. The selected gray voltage is selected and applied to the unit pixel as a data driving signal, and is typically formed of a plurality of integrated circuits.

The gate driver 300 and the data driver 400 may be mounted on the liquid crystal panel 500 in the form of a plurality of driving integrated circuit chips, or may be mounted on a flexible printed circuit film (FPC). The tape may be attached to the liquid crystal panel 500 in the form of a tape carrier package (TCP). In addition, the gate driver 300 or the data driver 400 may be integrated in the liquid crystal panel 500 together with the display signal lines G1 to Gn and D1 to Dm and the switching element Q.

The gamma voltage generator 450 may generate two sets of gamma voltages related to transmittance of a unit pixel. That is, one of the two sets is the positive voltage, and the other is the negative voltage. Herein, the positive voltage and the negative voltage mean voltages having opposite polarities with respect to the common voltage Vcom, and are alternately provided to the liquid crystal panel 500 during inversion driving.

As described above, the liquid crystal display 600 receives the driving and control signals from the outside and processes them appropriately to provide the driving and control signals of the liquid crystal panel 500.

Hereinafter, the display operation of the liquid crystal display 600 will be described in more detail.

The timing controller 100 may input R, G, and B image signals R, G, and B from the external graphic controller (not shown), and an input control signal for controlling the display thereof, for example, a vertical synchronization signal Vsync, horizontally. The synchronization signal Hsync, the main clock MCLK, and the data enable signal DE are provided.

The timing controller 100 generates a gate control signal CONT1, a data control signal CONT2, and the like based on the input control signal, and applies the image signals R, G, and B to operating conditions of the liquid crystal panel 500. Treat it properly. The gate control signal CONT1 is provided to the gate driver 300, and the data control signal CONT2 and the processed image signals R ', G', and B 'are provided to the data driver 400.

The gate control signal CONT1 is a vertical synchronization signal STV for instructing the output of the gate on pulse (gate on voltage section), the gate clock signal CPV for controlling the output timing of the gate on pulse, and the width of the gate on pulse. An output enable signal OE or the like that defines a.

The data control signal CONT2 is a load for applying a horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B ', and a data driving signal corresponding to the data lines D1 to Dm. The signal LOAD, the inversion driving signal RVS for inverting the polarity of the data driving signal with respect to the common voltage Vcom, the data clock signal HCLK, and the like.

In addition, the timing controller 100 detects the abnormal data enable signal DE from among the data enable signal DE provided from the outside and generates an error control signal CE. Here, the timing controller 100 generates pulse signals PS1 and PS2 based on the error control call CE, and the inversion driving signal RVS provided to the data driver 400 as the pulse signals PS1 and PS2. To control. In this case, the inversion driving signal RVS is fixed and maintained for a predetermined time from the first pulse signal PS1 to the second pulse signal PS2. The operation of the timing controller 100 will be described in detail later with reference to FIGS. 3 to 5.

The data driver 400 sequentially receives image data R ′, G ′, and B corresponding to one row of unit pixels according to the data control signal CONT2 provided from the timing controller 100, and among the gray voltages, respectively. The image data R ', G', B 'is converted into the corresponding data driving signal by selecting the gray scale voltage corresponding to the image data R', G ', B'.

The gate driver 300 is connected to the gate lines G1 to Gn by applying the gate-on voltage Von to the gate lines G1 to Gn according to the gate control signal CONT1 provided from the timing controller 100. Turn on (Q).

Here, while a gate-on voltage Von is applied to one gate line G1 to Gn, and a row of latching elements Q connected thereto is turned on (this period is referred to as' 1H 'or' 1 horizontal period ( horizontal period) 'and is equal to one period of the horizontal synchronization signal STH, the data enable signal DE, and the gate clock signal CPV], and the data driver 400 stores each data driving signal as a corresponding data line. Supply to (D1 ~ Dm). The data driving signal thus supplied is applied to the corresponding unit pixel through the turned-on switching element Q.

In addition, the liquid crystal molecules constituting the liquid crystal layer interposed between the first and second display panels change their arrangement according to the change in the electric field generated by the pixel electrode PE and the common electrode CE, thereby passing through the liquid crystal layer. The polarization of the light is changed. The change in polarization is represented by a change in transmittance of light by polarizers (not shown) attached to the first and second display panels.

In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G1 to Gn during one frame to apply data driving signals to all unit pixels. When one frame ends, the next frame starts, and the inversion driving signal RVS applied to the data driving unit 400 is applied so that the polarity of the data driving signal applied to each unit pixel is opposite to that of the data driving signal in the previous frame. The state is controlled ('frame inversion'). In this case, the polarity of the data driving signal flowing through one data line D1 to Dm is changed ('line inversion') in one frame according to the characteristics of the inversion driving signal RVS, or the data driving signal applied to one pixel row. The polarities of can also be different ('dot reversal').

3 is a block diagram of the timing controller of FIG. 1, and FIG. 4 is a waveform diagram of the signals of FIG. 3.

1 and 3, the timing controller 100 includes an inspector 110 and a controller 120.

The inspection unit 110 inspects the data enable signal DE provided from the outside to generate a predetermined control signal, for example, an error control signal CE. In more detail, the inspection unit 110 detects an abnormal data enable signal DE from among the data enable signal DE provided from the outside. Next, the test unit 110 generates an error control signal CE based on the abnormal data enable signal DE.

The controller 120 generates pulse signals PS1 and PS2 for controlling the existing inversion driving signal RVS ′ based on the error control signal CE provided from the inspection unit 110. In more detail, the controller 120 receives the error control signal CE from the tester 110 and generates the first pulse signal PS1 and the second pulse signal PS2. Here, the first pulse signal PS1 is a signal indicating the start of the error control signal CE, and the second pulse signal PS2 is a signal indicating the end of the error control signal CE.

In addition, the first and second pulse signals PS1 and PS2 control the inversion driving signal RVS provided to the data driver 400. That is, the controller 120 fixes and maintains the state of the inversion driving signal RVS for a predetermined time from the first pulse signal PS1 to the second pulse signal PS2.

Referring to Figure 4 in more detail as follows.

First, the inspection unit 110 of the timing controller 100 inspects the data enable signal DE provided from the outside. That is, the abnormal data enable signal DE having a high value of a time t2 shorter than the normal time t1 is detected among the data enable signals DE continuously provided. Next, the inspection unit 120 generates an error control signal CE that starts at the falling edge of the abnormal data enable signal DE and is maintained at a high value until the falling edge of the normal data enable signal DE. do.

Subsequently, the controller 120 receives the error control signal CE and generates pulse signals PS1 and PS2 for distinguishing the start and the end of the error control signal CE. That is, the controller 120 generates the first pulse signal PS1 to be synchronized with the rising edge of the error control signal CE, and the second pulse signal to be synchronized with the falling edge of the error control signal CE. (PS2) is generated.

Finally, the controller 120 controls the inversion driving signal RVS provided to the data driver 400 based on the first and second pulse signals PS1 and PS2. In more detail, the controller 120 fixes and maintains the existing inversion driving signal RVS 'for a predetermined time T from the first pulse signal PS1 to the second pulse signal PS2. . In this case, it is preferable that the existing inversion driving signal RVS fixed by the controller 120 is fixed and maintained in the state immediately before the first pulse signal PS1. In addition, it is preferable that the inverted driving signal RVS that is held in this manner is fixed and held for a maximum of one frame.

In the present exemplary embodiment, the present invention has been described, for example, when the conventional inversion driving signal RVS 'is fixed by the first and second pulse signals PS1 and PS2, but the present invention is not limited thereto. The same applies to the case where the existing inversion driving signal RVS 'immediately before the first pulse signal PS1 is low.

5 is an output waveform diagram of a data driver by the inversion driving signal of FIG. 4.

1, 3 and 5, the polarity of the data driving signal output from the data driver 400 is controlled by the inversion driving signal RVS provided from the timing controller 100. In addition, the data driving signal is divided into bipolar and negative polarities based on the common voltage Vcom.

More specifically, when the abnormal data enable signal DE is supplied from the data enable signal DE provided from the outside, the timing controller 100 may provide an error control signal CE and a first pulse signal PS1. And a second pulse signal PS2, wherein the error control signal CE, the first pulse signal PS1, and the second pulse signal PS2 are generated by the inversion driving signal generated by the timing controller 100. RVS ') is fixed and held for a predetermined time T. Next, the inverted drive signal RVS held in this manner is provided to the data driver 400, and the data driver 400 does not change the polarity of the output of the data drive signal by the fixed inversion drive signal RVS. .

In this case, the data driving signal fixed by the inversion driving signal RVS is preferably fixed only within one frame at most. This is to minimize the possibility of deterioration of the liquid crystal.

In addition, the TP signal shown in FIG. 5 is a signal for providing a data driving signal corresponding to the data lines D1 to Dm of the liquid crystal panel 500, and is formed in synchronization with a falling edge of the data enable signal DE. The data driving signal output from the data driver 400 has positive and negative values due to the common voltage Vcom, and its polarity is changed by the inversion driving signal RVS and the TP signal. That is, when the value of the inversion driving signal RVS becomes high and the TP signal becomes high after a predetermined time, the data driving signal, which is the output of the data driving unit 400, is reversed and outputted.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the liquid crystal display and the driving method thereof, the horizontal line defect due to the abnormal data enable signal input from the outside can be improved by controlling the inversion driving signal.

Claims (13)

Liquid crystal panels; A timing controller which generates an error control signal by inspecting a data enable signal provided from an external device, and controls an inversion driving signal according to the error control signal to provide the data driver to the data driver; And And a data driver configured to generate a data driving signal having positive / negative polarity based on a common voltage based on the inversion driving signal and provide the data driving signal to the liquid crystal panel. The method of claim 1, wherein the timing controller, A checker configured to detect the abnormal data enable signal among the data enable signals provided from the outside and generate the error control signal; And And a controller configured to generate first and second pulse signals that distinguish the start and the end of the error control signal, and to fix the inversion driving signal for a period from the first pulse signal to the second pulse signal. Device. The method of claim 2, And the inspection unit generates the error control signal which starts from the falling edge of the abnormal data enable signal provided from the outside and continues to the falling edge of the normal data enable signal. The method of claim 2, And the first pulse signal is generated in synchronization with the rising edge of the error control signal, and the second pulse signal is generated in synchronization with the falling edge of the error control signal. The method of claim 2, And the controller is configured to fix the inversion driving signal state immediately before the first pulse signal to maintain the second pulse signal. The method of claim 2, And the controller fixes and maintains the inversion driving signal for up to one frame. According to claim 1, And the inversion driving signal is a one-dot or two-dot inversion driving signal. Generating an error control signal by detecting the abnormal data enable signal among data enable signals provided from the outside; Generating first and second pulse signals that distinguish between a start and an end of the error control signal; Fixing an inversion driving signal for a time period from the first pulse signal to the second pulse signal, and providing the fixed inversion driving signal to a data driver; And And generating a data driving signal having a positive / negative polarity based on a common voltage based on the inversion driving signal and providing the same to a liquid crystal panel. The method of claim 8, The generating of the error control signal by detecting the abnormal data enable signal among the data enable signals provided from the outside may be performed starting from the polling edge of the abnormal data enable signal and up to the polling edge of the normal data enable signal. And generating the error control signal. The method of claim 8, Generating first and second pulse signals that distinguish the beginning and the end of the error control signal, the first pulse signal is generated in synchronization with the rising edge of the error control signal, the second pulse signal is And driving in synchronization with a falling edge of the error control signal. The method of claim 8, The fixing of the inversion driving signal during the time period from the first pulse signal to the second pulse signal may include fixing the state of the inversion driving signal immediately before the first pulse signal to maintain the second pulse signal. Method of driving the display device. The method of claim 8, And the inversion driving signal is fixed for a maximum of one frame. The method of claim 8, And the inversion driving signal is a one-dot or two-dot inversion driving signal.

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