KR20150069591A - Timing Controller for Display Device and Timing Controlling Method thereof - Google Patents

Abstract

The present invention can prevent the deterioration of an image by changes in frame frequencies wherein if a frame frequency of a display device or a refresh rate thereof is changed from a first frame frequency to a second frame frequency which is lower than the first frame frequency, first and second GOE setting values for generating a GOE signal are applied respectively with regard to 2 or more frame frequencies which are stored in advance and thereby changing the GOE signal. Accordingly, a pixel charging time of the ON period of the gate clock signal is maintained substantially the same and thus, the deterioration of an image by changes in frame frequencies can be prevented.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a timing controller for a display device,

The present invention relates to a timing control apparatus and method for a display apparatus.

The conventional display device includes a panel formed by intersecting gate lines and data lines, a gate driver for driving gate lines formed on the panel, a data driver for driving data lines formed on the panel, And a timing controller for controlling the driving timing of the driving signal.

On the other hand, in such a conventional display device, the gate driver supplies a gate control signal (GSC, GSP, GOE, etc.) to each gate line GL to charge a capacitor of a specific pixel, .

Also, the display device operates according to a driving frequency, which is also expressed as a scan driving signal cycle, a screen refresh rate, a frame frequency, and the like. Such a screen refresh frequency is typically 60 Hz, and 60 frames per second are expressed it means.

For example, in the case of a display device composed of M horizontal lines (gate lines), switching of each gate line can be turned on by 1 / M of the time for reproducing the entire panel. Therefore, if the screen refresh rate is 60 Hz and the number of gate lines is 1024, the time that each gate line can be turned on is about 16.3 μs, which is 1 / (60 * 1024) And is output as a gate signal by a gate output enable (hereinafter also referred to as "GOE") signal. That is, the gate is opened for 16.3 μs by the gate output enable signal to charge the source data to the pixel.

On the other hand, in the case of a portable display device such as a notebook monitor, the frame refresh rate or the frame frequency is typically 60 Hz. However, in order to reduce power consumption, the frame frequency is set to 60 Hz or less, for example, 50 Hz, 48 Hz, There may be a so-called " power saving mode "

In this case, when the pixel is driven at a frame frequency lower than the reference frame frequency, the pixel charge time of each gate line becomes longer than the reference frame frequency, and therefore, the brightness change or flickering Flickering phenomenon occurs.

In order to solve such a problem, it has been necessary to solve the problem of perceiving a change in the brightness of the display panel according to the variation of the charge time of each pixel or the problem of flickering when the refresh rate or the frame frequency is changed.

In view of the foregoing, it is an object of the present invention to provide a timing control apparatus and method for a display device capable of preventing a luminance change due to a change in frame frequency in a display device.

It is another object of the present invention to provide a method of controlling such that a change amount of a pixel charge time is not large so that a luminance change or flickering does not occur even when a frame frequency is changed in a display device.

It is still another object of the present invention to provide a display device capable of changing the width of a gate output enable pulse so as to uniformly maintain a charge time before and after a change in a frame frequency, And to provide an apparatus and a method for preventing deterioration in image quality caused by the deterioration of image quality.

In order to achieve the above-mentioned object, in one aspect, the present invention relates to a timing control device connected to a gate driver of a display device and controlling timing for a gate signal, the timing control device controlling a timing of a gate signal from a first frame frequency to a second frame frequency A second GOE (Gate Output Enable) setting value corresponding to the first frame frequency and a second GOE corresponding to a second frame frequency, the second GOE setting value being larger than the first GOE setting value; A GOE signal generator for generating a second GOE signal by using the second GOE setting value and a GOE signal generator for generating a second GOE signal by using the GOE signal when the frame frequency is changed from the first frame frequency to the second frame frequency, And a gate clock signal changing unit for generating a second gate clock signal based on the second GOE signal.

In another aspect, the present invention provides a timing control method coupled to a gate driver of a display device for controlling timing for a gate signal, the timing control method comprising: determining a frame frequency to recognize a frame frequency change from a first frame frequency to a second frame frequency lower than the first frame frequency; A GOE signal generation step of extracting a second GOE setting value larger than a first GOE setting value corresponding to the first frame frequency from the storage section to generate a second GOE signal, And a gate clock signal changing step of generating a second gate clock signal in response to the first gate clock signal and outputting the second gate clock signal in place of the first gate clock signal.

According to an embodiment of the present invention, in a display device including a timing control device such as a liquid crystal display device, when a refresh rate or a frame frequency changes, It is possible to prevent degradation of image quality.

According to an embodiment of the present invention, when the frame frequency is changed to a low value for saving power consumption in a display device of a portable device such as a notebook computer, the width of the gate output enable pulse is varied So that the charge time is uniformly maintained before and after the change of the frame frequency, thereby minimizing image degradation phenomena such as luminance change or flickering.

In addition, according to the embodiment of the present invention, the gate output enable value is appropriately adjusted according to need, so that it is possible to facilitate tuning according to the panel-by-panel deviation.

1 is a schematic system configuration diagram of a display device for applying embodiments.
Fig. 2 shows a timing diagram when a four-phase gate clock signal is used. Fig. 2 (a) shows a case of a first frame frequency, Fig. 2 Frequency operation.
Fig. 3 shows a configuration of an entire display device in which a timing control device according to an embodiment of the present invention is used.
4 is a functional block diagram of a timing controller for a display device according to an embodiment of the present invention.
FIG. 5 shows timing charts of a gate output signal and a GOE signal according to the frame frequency change according to the first embodiment of the present invention, in which (a) shows a first frame frequency, (b) (C) shows a case where the first frame frequency is changed to the second frame frequency while the first embodiment of the present invention is applied.
FIG. 6 is a timing chart of the gate output signal and the GOE signal according to the second embodiment of the present invention. FIG. 6 (a) shows the first frame frequency before the change, The second frame frequency is changed to the second frame frequency.
7 is a flowchart of a timing control method according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a schematic system configuration diagram of a display device 100 to which an embodiment of the present invention is applied.

1, a display device 100 according to an embodiment of the present invention includes a panel 110 formed by intersecting gate lines GL1 through GLn and data lines DL1 through DLm, A data driver 130 for driving the data lines formed on the panel 110 and a gate driver 120 for driving the gate drivers 120 and the data driver 130. [ A timing controller 140 and the like.

Each pixel (P) is defined in the panel 110 by intersecting the gate lines GL1 to GLn and the data lines DL1 to DLm.

The gate driver 120 drives the gate lines GL1 to GLn by sequentially supplying scan signals to the gate lines GL1 to GLn. To this end, the gate driver 120 receives the scan signals from the timing controller 140 (n is a natural number equal to or greater than 2) gate clock signals (GCLKi, i = 1 to x) are input to the gate lines GL1 to GLn based on the inputted x gate clock signals GCLKi And sequentially supplies a signal or a gate output signal Vout.

In this case, a 2-phase or 4-phase signal can be used depending on the number of the gate clock signals GCLKi, that is, the size of x. Since a 4-phase gate clock signal is usually used, GCLK1, GCLK2, GCLK3, GCLK4, Can be used.

The generation of the clock signal of this level shifter will be described with reference to FIG.

1 may be, for example, a liquid crystal display (LCD) or an organic light-emitting diode (OLED), and the present invention is not limited thereto, A gate driver 120, a data driver 130 and a timing controller 140. The gate driver 120 uses a clock signal to drive the gate lines GL1 to GLn It may be any type of display device.

The four gate clock signals may be generated in the timing controller 140, or may be generated in a level shifter included in the gate driver 120 or the like.

2, the level shifter 200 or the timing controller 140 generates driving clock information (CLOCK) and power (CLOCK) input from an external oscillator or the like, Generates four gate clock signals GCLK 1, GCLK 2, GCKL 3, and GCLK 4 based on the high level voltage VGH and the low level voltage VGL supplied from the supply unit 210, Signal to the gate driver 120.

The gate clock signal GCLKi has a pulse shape having an upper voltage section (HIGH or ON) and a lower voltage section (LOW or OFF), and each gate clock signal is repeated with a period of the horizontal section (H) . In this case, the horizontal period (H) period of the gate clock signal may be defined as a reciprocal of a value obtained by multiplying the frame frequency by the number of gate lines.

For example, if the display panel has a resolution of 1920 * 1080, the horizontal interval (H) period becomes 1 / (60Hz * 1080) 15.4 mu s.

As shown in FIG. 2, the four gate clock signals (GCLK1 to GCLK4) described above have the same pulse shape and are provided by being shifted by a predetermined amount of time. As a result, during a period in which the gate clock signal is ON, And therefore, pixel charging is performed during that period.

The timing controller 140 generates a gate output enable signal for triggering generation of the gate output signal Vout in addition to the gate clock signal GCLKi and outputting the gate output signal Vout to the corresponding gate line. GOE ") signal to the gate driver 120, as shown in FIG.

This GOE signal is used to indicate the time point of outputting the gate signal to the corresponding gate line. It is turned on at the time of falling of the i-th gate clock signal GCLKi and is turned on at the time of the (i + 2) -th gate clock signal GCLK _{i +} Is turned off at the time of rising of the pulse signal.

When the GOE signal is ON, the gate output signal is outputted to the i-th gate line. The gate output signal outputted at this time is a signal having the ON pulse width equal to the ON section width of the gate clock signal. And the pixel charging time (Pixel Charging Time).

Fig. 2 shows a timing diagram when a four-phase gate clock signal is used. Fig. 2 (a) shows a case of a first frame frequency, Fig. 2 Frequency operation.

In FIG. 2, the first frame frequency may be, for example, 60 Hz, and the second frame frequency may be, for example, 40 Hz or 48 Hz, but is not limited thereto.

2, each gate clock signal GCLK is a pulse signal having a horizontal section (H) period and is divided into an ON (HIGH) section for the time t and an OFF (LOW) section for the Ht time I have.

The ON period of the i-th gate clock signal and the ON period of the i + 1-th gate clock signal are partially overlapped, but the ON period of the i-th gate clock signal and the ON period of the i + The interval between them, that is, the interval between the polling point of the i-th gate clock signal and the rising point of the (i + 2) -th gate clock signal is defined as GOE.

Referring to FIG. 2, the first gate clock signal GCLK1 of the gate clock signal GCLK is used as a reference. When the gate driver 120 receives GCLK1 and GOE from the timing controller, the third pulse of the GOE is ON At the start time t = t0, the first gate output signal is generated and provided as the first gate line.

At this time, the gate output signal has the same ON period as the ON period of the first gate clock signal, and consequently the mode pixel connected to the first gate line by such gate output signal, more specifically, the storage capacitor The capacitor Cst is charged during the ON period of the gate clock signal GCLK1.

As a result, in the case of having the gate clock signal and the GOE signal as shown in FIG. 2, the ON period of each gate clock signal GCLK becomes the pixel charge time of each pixel.

On the other hand, in the case of a portable device such as a notebook computer, battery consumption is a sensitive problem. Therefore, reduction of power consumption is an important problem. Since power consumption of the display device is large in such a portable device, .

Accordingly, in order to reduce power consumption in a model of a notebook computer or the like, a technique of reducing a refresh rate or a frame frequency in a constant power saving mode has been developed.

Specifically, for example, in some notebook models, a frame frequency of 60 Hz is typically used. In a power saving mode, it is down to 48 Hz in a certain operating system (Win 8.1 or the like), or a Seamless Display Refresh Rate Switching And can be driven down by 40Hz.

In this case, the charging time of the pixel changes, and a change in brightness due to a change in the charged charge amount may be detected or a flickering failure may be detected.

Referring to FIGS. 2 (a) and 2 (b), the image quality degradation due to the change of the pixel charging time will be described below.

2 (a) shows a case of a first frame frequency of 60 Hz, FIG. 2 (b) shows a case of operating a second frame frequency of 40 Hz, and the number of gate lines is assumed to be 1080.

As shown in FIG. 2, when the first frame frequency of 60 Hz is changed to the second frame frequency of 40 Hz, each of the gate clock signals GCLKi and GOE is increased in proportion to the ratio.

That is, the horizontal period H period is increased by about 33% from 1 / (60 * 1080) to 1 / (40 * 1080), and the ON period of the gate clock signal and the ON period of GOE also increase by about 33% As a result, the ON period of the gate output signal provided to each gate line also increases by about 33%.

Therefore, if the frame frequency is reduced from 60 Hz to 40 Hz in order to reduce the power consumption, the pixel charging time is increased by about 33%. As a result, sudden brightness changes appear to brighten the screen or temporary flickering occurs .

In order to solve this problem, in an embodiment of the present invention, when a frame frequency or a refresh rate of a display device is changed from a first frame frequency to a second frame frequency lower than the first frame frequency, The GOE signal is changed by applying the first and second GOE setting value information for the GOE signal generation, thereby maintaining the pixel charge time, which is the ON period of the gate clock signal, substantially the same.

Fig. 3 shows a configuration of an entire display device in which a timing control device according to an embodiment of the present invention is used.

The timing controller 310 according to an embodiment of the present invention may be implemented as a timing controller (T-Con) or as a part of the apparatus, but is not limited thereto and may be a separate device or module Can be provided.

Hereinafter, the timing controller 310 will be described as being implemented in the timing controller of the display device.

A display device to which an embodiment of the present invention can be applied includes a display panel 330 including a plurality of (N) gate lines and a plurality (M) of data lines, A gate driver 320 for generating various control signals, and a timing controller 310 for generating and providing various control signals.

In FIG. 3, a data driver such as a data driver is not shown.

In addition, when it is confirmed that the frame frequency of the display device is changed from the first frame frequency to the second frame frequency lower than the first frame frequency, the timing control device 310 according to the embodiment of the present invention may further include a first A second GOE setting value larger than the first GOE setting value corresponding to the frame frequency is extracted from the storage unit and a second GOE signal and a corresponding second gate clock signal are generated using the second GOE setting value, And outputs it to the driver 320.

The detailed configuration of the timing controller 310 will be described in more detail with reference to FIG.

The gate driver 320 may include a circuit including a plurality of shift registers 321. The gate driver 320 may receive one or more gate clock signals GCLKi and GOE signals from the timing controller 310, Thereby generating gate output signals Vout1 to VoutN for the gate lines GL1 to GLN and providing them as gate lines.

The gate driver 320 may include a plurality of gate drive ICs directly formed on the display panel 330 and sequentially supplying scan signals to the gate lines. Is also referred to as "GIP (Gate Drive IC in Panel) ".

However, the gate driver 320 may be formed directly on the display panel 330, but not limited thereto, and may be connected to the display panel 330 through a tape carrier package (TCP) or the like.

In the above-described display device, when the frame frequency of the display device or the refresh rate of the screen is changed to be low, the ON duration of the first GOE signal at the frame frequency before the change is increased at the same rate as the frame frequency change By using a second GOE setting value that is larger than the first GOE setting value before the change so as to increase the pixel charge time change due to the frame frequency change.

4 is a functional block diagram of a timing controller for a display device according to an embodiment of the present invention.

The timing control device according to an embodiment of the present invention is connected to a gate driver of a display device and controls timing for a gate signal. The timing control device includes a frame frequency change confirmation unit 410, a GOE set value storage unit 420, a GOE signal generation unit 430, a gate clock signal modification unit 440, and a signal output unit 450.

The frame frequency change confirming unit 410 determines that the frame frequency or refresh rate of the display device is changed from a first frame frequency such as 60 Hz to a second frame frequency such as 40 Hz, Function.

The frame frequency change confirmation unit 410 functions to identify that the display device is changed from the first frame frequency to the second frame frequency lower than the operating frequency of the operating system or the power saving mode of the electronic equipment.

The GOE set value storage unit 420 stores a first GOE set value corresponding to the first frame frequency and a second GOE set value corresponding to the second frame frequency but larger than the first GOE set value, And a storage device such as an EEPROM in the controller.

In the present specification, 'GOE setting value' is defined as a numerical value indicating the width of the ON interval of the GOE pulse for generating a GOE signal for activating the gate output signal, that is, a GOE pulse.

For example, when the basic driving frequency of the display device is 1 MHz, the basic driving clock (period) is set to 1 s / 1000000, and the GOE setting value is three times the basic driving clock (period), the GOE signal by this means that the width of the ON period is 3 μs.

However, the GOE setting value does not necessarily have to be defined in this way, but represents a certain fraction of the frame frequency or the horizontal interval (H) period, such as the frame frequency or 1 / K (K is a natural number) of the horizontal interval It may be defined as a constant value. For example, if the GOE setting is set to 1/10 (K = 10) of the horizontal interval (H) period, the frame frequency is 60 Hz, and the number of gate lines is 1080, The ON duration of the GOE signal (see GOE, GOE ', and GOE in FIG. 5) is equal to H / 10 = 15.4 / 10 = 1.54 μs.

That is, the GOE set value storage unit 420 stores a first GOE set value and a second GOE set value that are different from each other to correspond to two or more frame frequencies, and a second GOE set value for a low frame frequency So that the set value is larger than the first GOE setting value for the high frame frequency. As a result, when the frame frequency is changed from the high frame frequency to the low frame frequency, the GOE signal is also changed so that the ON period of the GOE signal for generating the gate clock signal is larger, and accordingly the ON period of the gate clock signal, So as to minimize the change.

That is, the first and second GOE setting values may be defined as a specific integer multiple of the basic driving clock (cycle) by the basic driving frequency, and the second integer multiple (J) for the second GOE setting value may be defined as the first (J) for the GOE setting value.

The GOE signal generator 430 changes the generation of the first GOE signal according to the first GOE setting value to generate the second GOE signal according to the second GOE setting value when the frame frequency changes. The second GOE signal changed in accordance with the change of the frame frequency is transmitted to the gate driver (320 in FIG. 3) at the same time as inducing the gate clock signal to change from the first gate clock signal to the second gate clock signal as will be described later .

The gate clock signal changing unit 440 changes the second GOE signal according to the second GOE setting value when the frame frequency of the display device or the screen refresh rate is changed from the first frame frequency to the second frame frequency lower than the second frame frequency, To generate a second gate clock signal. That is, before the change, the first gate clock signal corresponding to the first frame frequency is generated. If there is a change to the second frame frequency, the changed GOE signal (second GOE signal) And generates a second gate clock signal different from the first gate clock signal.

At this time, the ON period of the second gate clock signal corresponding to the pixel charging time is substantially equal to or slightly greater than the ON period of the first gate clock signal (? T), and the luminance variation May be of a size such that the charging time is extended to such an extent as not to occur.

In addition, the signal output unit 450 transmits the second GOE signal and the second gate clock signal, which are changed by the change of the frame frequency, to the gate driver.

FIG. 5 shows timing charts of a gate output signal and a GOE signal according to the frame frequency change according to the first embodiment of the present invention, in which (a) shows a first frame frequency, (b) (C) shows a case where the first frame frequency is changed to the second frame frequency while the first embodiment of the present invention is applied.

In the embodiment of Figures 5 and 6, it is assumed that the first frame frequency is 60 Hz and the second frame frequency is 40 Hz. It is also assumed that the number of gate lines (the number of scan lines), that is, the vertical resolution is 1080, and that the gate clock signal has four phases.

5A, the first gate clock signal before the frame frequency change is composed of GCLK1 to GCLK4, and each gate clock signal GCLKi is a pulse signal having a horizontal interval (H) period, ON (HIGH) period and an OFF (LOW) period for Ht time. At this time, the horizontal interval (H) period becomes 1 / (60Hz * 1080) 15.4s.

The ON period of the i-th gate clock signal and the ON period of the i + 1-th gate clock signal are partially overlapped, but the ON period of the i-th gate clock signal and the ON period of the i + The interval between them, that is, the interval between the polling point of the i-th gate clock signal and the rising point of the (i + 2) -th gate clock signal is defined as GOE.

Therefore, the resultant first GOE signal is as shown in the bottom timing of FIG. 5A, and the ON section width of the first GOE signal is defined as the first GOE setting value in this specification.

That is, a GOE signal is generated so as to have an ON period determined by the first GOE setting value, and the output of each gate output signal Vout is triggered by this GOE signal. That is, in FIG. 5A, the first gate output signal is outputted at the rising time point of the third pulse of the first GOE signal, and the third gate output signal is outputted at the rising time point of the fifth pulse.

At this time, the ON period t of the first gate clock signal GCLK1 becomes the pixel charge time, and the pixel charge time t is the total horizontal period H period and the (i + 2) (GOE) of the first GOE signal, which is the time interval from the rising time of the gate clock signal GCLK1 to the time of polling of the gate clock signal GCLK1 itself.

As the ON pulse width of the first GOE signal increases, the ON period t of the first gate clock signal, which is the pixel charge time, becomes smaller as the frame frequency is fixed.

On the other hand, the ON pulse width of the first GOE signal is set to a first GOE setting value equal to an integral multiple of the basic driving clock (period). For example, if the basic driving frequency is 1 MHz, the basic driving clock (period) is 1 s, which is 1 s / 1000000. If the first GOE setting value has a value of 3 as an integer multiple, The width of the ON section is set to 3 μs.

Of course, in this case, the ON period (pixel charge time) t of the first gate clock signal is determined by the ON pulse width of the first GOE signal.

FIG. 5 (b) shows a case where an embodiment of the present invention is not applied when the frame frequency is changed from the first frame frequency of 60 Hz to the second frame frequency of 40 Hz.

In this case, if the frame frequency is increased by about 33% and the present invention is not applied, the period of the horizontal section H 'and the ON pulse width GOE' of the GOE signal, as shown in FIG. 5B, Which is about 33% more than the change rate.

In this case, the basic driving frequency also increases by 33% to 1 / 1.333 MHz, so that the basic driving clock (period) also increases by the ratio, and the first GOE signal The ON pulse width GOE 'of the pulse width of the pulse width is also increased by the increase rate of the frame frequency since the integer multiple is not changed.

As a result, the pixel charging time according to the change of the frame frequency, that is, the ON period t 'of the first gate clock signal is also increased by about 33%, thereby causing a luminance change due to the excessive charging as described above.

5C shows a case where the first embodiment of the present invention is applied. When the frame frequency is changed from the first frame frequency (60 Hz) to the second frame frequency (40 Hz), the first GOE setting value A second GOE signal is generated so that the ON pulse width of the GOE signal is larger than the frame frequency reduction ratio by using a second large GOE setting value, thereby generating second gate clock signals (second GCLK1 to 4).

In this case, in the first embodiment of the present invention, the ON period width of the first gate clock signal before the frame frequency change, which is the ON period (pixel charge time) of the second gate clock signal, The second GOE setting value is set.

5C) of the second GOE signal is larger than GOE '(FIG. 5B), which is a natural increment of the ON pulse width of the first GOE signal, And a large degree is defined such that the ON period width t of the second gate clock signal is equal to the ON period width of the first gate clock signal.

For example, in the above example, if the first GOE setting value is set to j = 3, which is an integer multiple of the driving clock (period), and the basic driving frequency is 1 MHz, if the ON pulse width of the first GOE signal is 3 [ The second GOE setting value is, for example, an integer greater than J = 5 so that the On pulse width of the second GOE signal is 5 μs or about 6.653 μs (5 * 1.333 μs). (At this time, if the present invention is not applied, the GOE signal will still be generated by j = 3, which is the first GOE setting value, so that the ON pulse width of the GOE signal is 3.9993 μs, which is 3 * 1.33)

As described above, by increasing the ON pulse width GOE " of the second GOE signal to be larger than the ON pulse width GOE 'of the first GOE signal naturally increased by the frame frequency variation ratio, That is, the pixel charging time can be maintained without fluctuation.

FIG. 6 is a timing chart of the gate output signal and the GOE signal according to the second embodiment of the present invention. FIG. 6 (a) shows the first frame frequency before the change, The second frame frequency is changed to the second frame frequency.

FIG. 6 corresponds to the first embodiment shown in FIG. 5. In the first embodiment, the pixel charging time t is kept unchanged even when the frame frequency fluctuates. On the other hand, in the second embodiment shown in FIG. 6, (T) after the change is larger than the pixel charge time (t) before the change by a certain degree ([Delta] t).

That is, in the second embodiment, when the second frame frequency is reduced from the first frame frequency (60 Hz) to the second frame frequency (40 Hz), the On pulse width GOE '' of the second GOE signal by the second GOE setting value becomes The second GOE setting value is selected to be larger than the ON pulse width GOE " of the second GOE signal according to the embodiment by a certain degree (DELTA t), so that the pixel charge time after the frame frequency change T ') of the clock signal is set to be larger than the pixel charge time before change (that is, the ON duration width t of the first gate clock signal) by a certain degree (DELTA t).

In the ideal case, even if the frame frequency is reduced by a certain rate, if the pixel charging time is the same, no luminance change will occur at all. However, in practice, the off current Due to the increase of the Off Current, it may be necessary to charge the pixel more than before the change.

Therefore, in the second embodiment of the present invention as shown in FIG. 6, when the frame frequency is reduced, the pixel charge time (i.e., the ON period of the gate clock signal) The degree? T can be determined to such an extent as to compensate for the luminance reduction due to the increase in the off current or the like and maintain the resulting display luminance uniform.

7 is a flowchart of a timing control method according to an embodiment of the present invention.

A timing control method in accordance with a frame frequency change according to an embodiment of the present invention includes a frame frequency change confirmation step (S710) of recognizing a frame frequency change from a first frame frequency to a second frame frequency lower than the first frame frequency, A GOE signal generation step 720 of extracting a second GOE setting value larger than a first GOE setting value corresponding to the frequency from the storage unit to generate a second GOE signal, And a gate clock signal changing step 730 for generating and outputting the modified second gate clock signal and the second GOE signal to the gate driver 740.

At this time, the pixel charging time is determined by the ON section width of the gate clock signal. The ON pulse width of the gate clock signal is determined by the ON pulse width (GOE, GOE 'in FIGS. 5 and 6) of the GOE signal, , GOE ", GOE " ').

Therefore, in the flow of the method, the second GOE setting value has a value larger than the first GOE setting value which is naturally increased according to the first GOE setting value or the frame frequency decrease, and consequently the ON pulse width (GOE " in FIG. 5, GOE '' in FIG. 6) is larger than the ON pulse width (GOE in FIG. 5) or its natural increment (GOE 'in FIG. 5) of the first GOE signal.

As a result, when there is a decrease in the frame frequency, the pixel charge time, which is the On interval width of the second gate clock signal, is kept the same, or the influence of the off current or the like is compensated, .

As described above, according to the embodiment of the present invention, in the display device including the timing control device such as the liquid crystal display device, when the refresh rate or the frame frequency is changed, It is possible to prevent a change in luminance and an image quality deterioration.

In addition, according to an embodiment of the present invention, when the frame frequency is changed to a low value for saving power consumption in a display device of a portable device such as a notebook computer, the ON pulse of the gate output enable signal The pixel charge time is uniformly maintained before and after changing the frame frequency by varying the width, thereby minimizing image degradation phenomena such as luminance change or flickering.

In addition, according to the embodiment of the present invention, the ON pulse width of the gate output enable signal may be appropriately adjusted according to the necessity This problem can be solved by varying. That is, there is an effect that the image quality degradation due to the panel-specific deviation can be appropriately tuned when the frame frequency is changed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

310: timing control device 320: gate driver
330: display panel 321: shift register
410: Frame frequency change confirmation unit 420: GOE setting value storage unit
430: GOE signal generating unit 440: Gate clock signal changing unit
450: signal output part GCLKi: i-th gate clock signal
GOE: gate output enable signal t, t ': pixel charge time

Claims (9)

A timing control device connected to a gate driver of a display device and controlling timing for a gate signal,
A frame frequency change confirmation unit for confirming a frame frequency change from a first frame frequency to a second frame frequency lower than the first frame frequency;
A storage unit storing a first GOE (Gate Output Enable) setting value corresponding to the first frame frequency and a second GOE setting value corresponding to a second frame frequency, the second GOE setting value being larger than the first GOE setting value;
A GOE signal generator for generating a second GOE signal using the second GOE setting value; And
A gate clock signal changing unit for changing the frame frequency from the first frame frequency to the second frame frequency to generate a second gate clock signal based on the second GOE signal;
And a timing controller for controlling the timing controller. The method according to claim 1,
The first and second GOE set values are each defined as a specific integer multiple of the basic driving clock (cycle) by the basic driving frequency, and the second integer multiple (J) for the second GOE setting value is defined as the first GOE setting value Is greater than a first integral multiple value (j) for the input signal. The method according to claim 1,
The ON period width of the second gate clock signal by the second GOE setting value is substantially equal to the ON period width of the first gate clock signal by the first GOE setting value, And the pixel charge time is maintained substantially the same even when the frequency is changed to the frequency. The method according to claim 1,
The ON interval width of the second gate clock signal according to the second GOE setting value is larger than the ON interval width of the first gate clock signal due to the first GOE setting value by a predetermined amount DELTA t, And a value that does not cause a change in luminance due to frequency reduction. The method according to claim 1,
Wherein the first frame frequency is 60 Hz and the second frame frequency is 40 Hz or 48 Hz. The method according to claim 1,
And a signal output unit for outputting the changed second gate clock signal and the second GOE signal to the gate driver. A timing control method for controlling a timing for a gate signal in connection with a gate driver of a display device,
Determining a frame frequency change from a first frame frequency to a second frame frequency lower than the first frame frequency;
A GOE signal generation step of extracting a second GOE setting value larger than a first GOE setting value corresponding to the first frame frequency from the storage unit and generating a second GOE signal; And
A gate clock signal changing step of generating a second gate clock signal based on the second GOE signal and outputting the second gate clock signal instead of the first gate clock signal;
And a timing controller for controlling the timing of the display device. 8. The method of claim 7,
Wherein the pixel charge time is determined by the ON interval width of the first and second gate clock signals, and the ON interval width of the first and second gate clock signals is determined by the first and second GOE setting values, And the ON pulse width of the second GOE signal. 9. The method of claim 8,
The second GOE setting value has a larger value than the first GOE setting value that is naturally increased according to the first GOE setting value or the frame frequency decrease, and the ON pulse width of the second GOE signal is greater than the ON setting value of the first GOE signal ON Pulse width or a natural increment thereof.

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