KR20190010822A - Display apparatus and method of driving the same - Google Patents

Abstract

A display device comprises a display panel, a gate driving unit, a data driving unit, a timing control unit and a gate clock signal compensation unit. The display panel displays images and comprises a gate line and a data line. The gate driving unit outputs a gate signal to the gate line. The data driving unit outputs a data signal to the data line. The timing control unit outputs a vertical start signal used in outputting the gate signal, and a gate clock signal. The gate clock signal compensation unit generates a clock signal based on the vertical start signal, selectively outputs the gate clock signal and the clock signal according to comparison of time difference between the gate clock signal and the clock signal with reference time which is an allowable reference of a jitter of the gate clock signal, and increases the intensity of the selected gate clock signal or an inner clock signal to output the same to the gate driving unit as a compensated gate clock signal. Accordingly, a display quality of the display device can be improved.

Description

DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display, and more particularly, to a display device and a driving method of the display device.

The display device includes a display panel and a display panel drive device.

The display panel includes a gate line, a data line, and a pixel defined by the gate line and the data line. When the display panel is a liquid crystal display panel, the pixel includes a thin film transistor, a liquid crystal capacitor, and a storage capacitor. The thin film transistor is electrically connected to the gate line and the data line. The liquid crystal capacitor and the storage capacitor are electrically connected to the thin film transistor.

The display panel driving apparatus includes a gate driver, a data driver, and a timing controller. The gate driver outputs a gate signal to the gate line. The data driver outputs a data signal to the data line. The timing controller outputs a gate clock signal to the gate driver, controls the timing of the gate driver, and outputs a data clock signal to the data driver to control the timing of the data driver.

When the gate clock signal has a time deviation in each of the frames, a horizontal line luminance deviation may occur in the image of the display panel. Therefore, if the gate clock signal has a jitter, the display quality of the display device may be degraded.

Accordingly, it is an object of the present invention to provide a display device capable of improving display quality of a display device.

Another object of the present invention is to provide a method of driving the display device.

According to an aspect of the present invention, a display device includes a display panel, a gate driver, a data driver, a timing controller, and a gate clock signal compensator. The display panel displays an image and includes a gate line and a data line. The gate driver outputs a gate signal to the gate line. The data driver outputs a data signal to the data line. The timing control unit outputs a vertical start signal and a gate clock signal used for outputting the gate signal. The gate clock signal compensator generates a clock signal based on the vertical start signal and compares a time difference between the gate clock signal and the clock signal and a reference time that is a jitter tolerance criterion of the gate clock signal And outputs the gate clock signal or the clock signal as a compensated gate clock signal to the gate driver to selectively output the gate clock signal and the clock signal according to the selected gate clock signal or the clock signal, do.

In one embodiment of the present invention, when the time difference between the gate clock signal and the clock signal is equal to or greater than the reference time, the gate clock signal compensator may select the clock signal from among the gate clock signal and the clock signal.

In one embodiment of the present invention, the gate clock signal compensator may include a lookup table unit for storing the reference time.

In one embodiment of the present invention, the gate clock signal compensator may include a lookup table unit for storing interval data of a clock signal based on the clock signal.

In one embodiment of the present invention, the gate clock signal compensator may include a signal generator for generating the clock base signal according to the vertical start signal and the interval data.

In one embodiment of the present invention, the interval data of the clock base signal includes a first interval from a rising time of the vertical start signal to a rise time of the clock base signal, a first interval from a rising time of the clock base signal, And a third period from a falling time of the clock base signal to a rise time of the clock base signal.

In one embodiment of the present invention, the gate clock signal compensator may include a clock signal generator for generating the clock signal in response to a rising edge of the clock base signal.

In one embodiment of the present invention, the gate clock signal compensator includes a comparator for comparing the gate clock signal and the clock signal, and comparing the time difference between the gate clock signal and the clock signal and the reference time .

In one embodiment of the present invention, when the time difference between the gate clock signal and the clock signal is less than the reference time, the gate clock signal compensator may select the gate clock signal from the gate clock signal and the clock signal .

In one embodiment of the present invention, the display device may further include a voltage manager for outputting a driving voltage to the data driver, and the gate clock signal compensator may be included in the voltage manager.

In one embodiment of the present invention, the display panel may be a liquid crystal display panel including liquid crystal, and the voltage management unit may further output a common voltage to the display panel.

According to an aspect of the present invention, a display device includes a display panel, a gate driver, a data driver, a timing controller, and a gate clock signal compensator. The display panel displays an image and includes a gate line and a data line. The gate driver outputs a gate signal to the gate line. The data driver outputs a data signal to the data line. The timing control unit outputs a vertical start signal and a gate clock signal used for outputting the gate signal. The gate clock signal compensator generates a clock signal based on the vertical start signal, raises the level of the clock signal, and outputs the raised clock signal to the gate driver as a compensating gate clock signal.

In one embodiment of the present invention, the gate clock signal compensator may include a lookup table unit for storing interval data of a clock signal based on the clock signal.

In one embodiment of the present invention, the gate clock signal compensator may include a signal generator for generating the clock base signal according to the vertical start signal and the interval data.

In one embodiment of the present invention, the interval data of the clock base signal includes a first interval from a rising time of the vertical start signal to a rise time of the clock base signal, a first interval from a rising time of the clock base signal, And a third period from a falling time of the clock base signal to a rise time of the clock base signal.

In one embodiment of the present invention, the gate clock signal compensator may include a clock signal generator for generating the clock signal in response to a rising edge of the clock base signal.

In one embodiment of the present invention, the display device may further include a voltage manager for outputting a driving voltage to the data driver, and the gate clock signal compensator may be included in the voltage manager.

In one embodiment of the present invention, the display panel may be a liquid crystal display panel including liquid crystal, and the voltage management unit may further output a common voltage to the display panel.

According to another aspect of the present invention, there is provided a method of driving a display device, including the steps of generating a clock base signal based on interval data of a clock base signal and a vertical start signal, Determining whether a time difference between the clock signal and the gate clock signal is equal to or greater than a reference time that is a jitter tolerance reference value of the gate clock signal and a time between the gate clock signal and the clock signal, Selecting a clock signal among the gate clock signal and the clock signal and outputting the selected clock signal as a selected clock signal when the difference is equal to or greater than the reference time; and if the time difference between the gate clock signal and the clock signal is less than the reference time, Clock signal and the internal clock signal Selecting a gate clock signal and outputting the selected clock signal as the selected clock signal; outputting the incremented selected clock signal as a compensated gate clock signal by increasing the level of the selected clock signal; And outputting the gate signal to the gate line of the display panel, and outputting the data signal to the data line of the display panel.

According to such a display device and a driving method thereof, the compensation gate clock signal can be outputted by compensating for the jitter included in the gate clock signal. Also, gate signals are generated using the compensation gate clock signal with compensated jitter. Therefore, in the image displayed on the display panel, the horizontal line luminance deviation displayed by the jitter can be reduced. Therefore, the display quality of the display device can be improved.

1 is a block diagram showing a display device according to an embodiment of the present invention.
2 is a block diagram showing the gate clock signal compensator of FIG.
3 is a timing diagram showing the vertical start signal and the internal clock base signal of FIG.
4 is a timing diagram showing the gate clock signals of FIGS. 1 and 2. FIG.
5 is a timing diagram showing the internal clock signal of FIG.
FIG. 6A is a timing chart showing the timing of the first gate clock signal and the first internal clock signal when the time difference between the first gate clock signal of FIG. 4 and the first internal clock signal of FIG. 5 is greater than the reference time of FIGS. .
6B is a timing chart showing the timing of the first gate clock signal and the first internal clock signal when the time difference between the first gate clock signal of FIG. 4 and the first internal clock signal of FIG. 5 is less than the reference time of FIGS. .
7 is a timing diagram illustrating the compensating gate clock signals of FIGS. 1 and 2. FIG.
8 is a flowchart showing a method of driving the display device of FIG.
9 is a block diagram illustrating a gate clock signal compensator according to an embodiment of the present invention.
10 is a flowchart showing a method of driving a display device including the gate clock signal compensator of FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1 is a block diagram showing a display device according to an embodiment of the present invention.

1, the display device 100 according to the present embodiment includes a display panel 110, a gate driver 130, a data driver 140, a timing controller 150, and a voltage manager 160 .

The display panel 110 receives the data signal DS from the data driver 140 and displays an image. The display panel 110 includes first to Nth (N is a natural number) gate lines GL1, GL2, ..., GLN, data lines DL and pixels 120. [

The first to Nth gate lines GL1, GL2, ..., GLN are arranged in a second direction D2 extending in a first direction D1 and substantially perpendicular to the first direction D1. do.

The data lines DL extend in the second direction D2 and are arranged in the first direction D1.

The first direction D1 may be substantially parallel to the long side of the display panel 110 and the second direction D2 may be substantially parallel to the short side of the display panel 110. [

The pixel 120 is defined by each of the first to Nth gate lines GL1, GL2, ..., GLN and each of the data lines DL. For example, the pixel 120 may include a thin film transistor, a liquid crystal capacitor electrically connected to the thin film transistor, and a storage capacitor. Accordingly, the display panel 110 may be a liquid crystal display panel including liquid crystal.

The gate driver 130, the data driver 140 and the timing controller 150 may be defined as a display panel driver for driving the display panel 110.

The gate driver 130 generates first to Nth gate signals GS1, GS2, ..., GSN using the compensation gate clock signal CGCLK provided from the voltage manager 160, And outputs the first to Nth gate signals GS1, GS2, ..., and GSN to the first to Nth gate lines GL1, GL2, ..., and GLN, respectively. The gate driver 130 may include a gate driver or a gate driver.

The data driver 140 receives the image data DATA from the timing controller 150 and generates the data signal DS using the image data DATA and provides the data signal DS from the timing controller 150 And outputs the data signal DS to the data line DL in response to a horizontal start signal STH and a data clock signal DCLK. The data driver 140 may include data driver ICs 145 that generate the data signals DS and output the data signals DS to the data lines DL. The data driver 140 may output the data signal DS to the data line DL using the driving voltage DRV provided from the voltage manager 160. [ The data driver 140 may include a data driver or a data driver.

The timing controller 150 receives the input video data IDATA and the control signal CON from the outside. The input image data IDATA may include red data R, green data G, and blue data B, for example. The control signal CON may include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a timing clock signal CLK. The timing controller 150 processes the input image data IDATA and outputs the image data DATA to the data driver 140. [ The timing controller 150 generates the horizontal start signal STH using the horizontal synchronizing signal Hsync and outputs the horizontal start signal STH to the data driver 140. [ The timing controller 150 generates the vertical start signal STV using the vertical synchronization signal Vsync and outputs the vertical start signal STV to the voltage manager 160. [ The timing controller 150 generates the gate clock signal GCLK and the data clock signal DCLK using the timing clock signal CLK and outputs the gate clock signal GCLK to the voltage manager And outputs the data clock signal DCLK to the data driver 140. The timing controller 150 may include a timing controller or a timing control circuit.

The voltage management unit 160 outputs the driving voltage DRV to the data driver 140. When the display panel 110 is a liquid crystal display panel, the voltage management unit 160 may output a common voltage VCOM to the display panel 110. The voltage management unit 160 may include a power management integrated circuit (PMIC).

The voltage management unit 160 may include a gate clock signal compensator 200. The gate clock signal compensator 200 compensates for the jitter of the gate clock signal GCLK and outputs the compensation gate clock signal CGCLK to the gate driver 130. The gate clock signal compensator 200 receives the vertical start signal STV and the gate clock signal GCLK from the timing controller 150 and outputs the reference time RT and the interval data PD And outputs the compensation gate clock signal CGCLK using the vertical start signal STV, the gate clock signal GCLK, the reference time RT and the interval data PD.

2 is a block diagram showing the gate clock signal compensator 200 of FIG.

1 and 2, the gate clock signal compensating unit 200 includes a lookup table unit 210, a signal generating unit 220, an internal clock signal generating unit 230, a comparing unit 240, (250).

The lookup table unit 210 receives and stores the reference time RT and the interval data PD. The reference time RT may be a jitter tolerance of the gate clock signal GCLK. The lookup table unit 210 may include a memory for receiving and storing the reference time RT and the interval data PD.

The signal generator 220 receives the vertical start signal STV from the timing controller 150 and receives the interval data PD from the lookup table unit 210. The signal generator 220 generates and outputs an internal clock base signal ICLKB using the vertical start signal STV and the interval data PD. The signal generator 220 may include a signal generator for generating and outputting the internal clock base signal ICLKB.

The internal clock signal generator 230 receives the internal clock base signal ICLKB from the signal generator 220 and generates an internal clock signal ICLK based on the internal clock base signal ICLKB And outputs it. The internal clock signal generator 230 may include a signal generator for generating and outputting the internal clock signal ICLK.

The comparator 240 receives the gate clock signal GCLK from the timing controller 150 and receives the internal clock signal ICLK from the internal clock signal generator 230 and outputs the internal clock signal ICLK to the lookup table unit 210 (RT) from the reference time (RT). The comparator 240 selects one of the gate clock signal GCLK and the internal clock signal ICLK based on the time difference between the gate clock signal GCLK and the internal clock signal ICLK And outputs it as the selected clock signal SCLK.

Specifically, when the time difference between the gate clock signal GCLK and the internal clock signal ICLK is equal to or greater than the reference time RT, the comparator 240 compares the gate clock signal GCLK and the internal clock signal ICLK ICLK, and outputs the internal clock signal ICLK as the selected clock signal SCLK. Alternatively, when the time difference between the gate clock signal GCLK and the internal clock signal ICLK is less than the reference time RT, the comparator 240 compares the gate clock signal GCLK and the internal clock signal ICLK, ICLK, and outputs the gate clock signal GCLK as the selected clock signal SCLK.

The comparator 240 compares the gate clock signal GCLK and the internal clock signal ICLK with each other, and a comparator 240 comparing a time difference between the gate clock signal GCLK and the internal clock signal ICLK, And a second comparator for comparing the reference time (RT).

The level shifter unit 250 increases the level of the selected clock signal SCLK and outputs the compensation gate clock signal CGCLK. Therefore, the level shifter 250 increases the level of the selected internal clock signal ICLK or the gate clock signal GCLK to output the compensation gate clock signal CGCLK. For example, the selected clock signal SCLK input to the level shifter 250 may have an amplitude of about 3.3 volts, and the compensation gate clock signal CLK output from the level shifter 250 CGCLK) may have an amplitude of about 30 volts. The level shifter unit 250 may include a level shifter for increasing the level of the selected clock signal SCLK.

3 is a timing chart showing the vertical start signal STV and the internal clock base signal ICLKB of FIG.

1 to 3, the internal clock base signal ICLKB includes a first interval P1, a second interval P2, and a third interval P3. The first interval P1 is from the rise time of the vertical start signal STV to the rise time of the internal clock base signal ICLKB. The second period P2 is from the rise time of the internal clock base signal ICLKB to the fall time of the internal clock base signal ICLKB. The third interval P3 is from the falling time of the internal clock base signal ICLKB to the rising time of the internal clock base signal ICLKB.

The first interval P1, the second interval P2 and the third interval P3 of the internal clock basic signal ICLKB may be included in the interval data PD and the gate clock signal GCLK As shown in FIG. Accordingly, the signal generator 220 can generate and output the internal clock base signal ICLKB using the vertical start signal STV and the interval data PD.

4 is a timing diagram showing the gate clock signal GCLK of Figs. 1 and 2. Fig.

1 to 4, the gate clock signal GCLK includes first to Nth gate clock signals for the timings of the first to Nth gate signals GS1, GS2, ..., GSN, (GCLK1, GCLK2, ..., GCLKN). Each of the first to Nth gate clock signals GCLK1, GCLK2, ..., GCLKN has a jitter. For example, the first gate clock signal GCLK1 has a time deviation in a plurality of frames. For example, the first gate clock signal GCLK1 may rise from a first frame in a first frame to a first point in a second frame, and may rise in a second frame earlier than the first point in time, And may rise at a third time point later than the first time point in three frames.

5 is a timing chart showing the internal clock signal ICLK of FIG.

Referring to FIGS. 1 to 5, the internal clock signal ICLK1 includes first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN. Each of the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN has no jitter. Each of the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN is generated based on the internal clock base signal ICLKB.

Specifically, each of the first to N-th internal clock signals ICLK1, ICLK2, ..., ICLKN may occur in response to a rising edge of the internal clock base signal ICLKB. For example, the first internal clock signal ICLK1 of the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN is supplied to the first rising edge of the internal clock base signal ICLKB And may have a high level during the second interval (P2) of the internal clock base signal (ICLKB). Also, for example, the second internal clock signal ICLK2 of the first to Nth internal clock signals ICLK1, ICLK2, ... ICLKN may be the second rising Edge and may have a high level during the second interval P2 of the internal clock base signal ICLKB. For example, the N-th internal clock signal ICLKN of the first to N-th internal clock signals ICLK1, ICLK2, ..., and ICLKN is the N-th rise of the internal clock base signal ICLKB Edge and may have a high level during the second interval P2 of the internal clock base signal ICLKB.

FIG. 6A is a timing diagram of the first gate clock signal GCLK1 of FIG. 4 when the time difference between the first gate clock signal GCLK1 of FIG. 4 and the first internal clock signal ICLK1 of FIG. 5 is greater than or equal to the reference time RT of FIGS. A clock signal GCLK1 and the first internal clock signal ICLK1.

1 to 6A, the time difference between the first gate clock signal GCLK1 and the first internal clock signal ICLK1 is larger than the reference time RT.

The comparator 240 of the gate clock signal compensator 200 compares the time difference between the gate clock signal GCLK and the internal clock signal ICLK and the reference time RT, The internal clock signal ICLK from the gate clock signal GCLK and the internal clock signal ICLK when the time difference between the clock signal GCLK and the internal clock signal ICLK is equal to or greater than the reference time RT And outputs it as the selected clock signal SCLK.

6A, when the time difference between the first gate clock signal GCLK1 and the first internal clock signal ICLK1 is greater than the reference time RT, the gate clock signal compensation The comparator 240 of the comparator 240 compares the first internal clock signal ICLK1 among the first gate clock signal GCLK1 and the first internal clock signal ICLK1 with the selected clock signal SCLK Can be output.

6B is a timing diagram of the first gate clock signal GCLK1 of FIG. 4 when the time difference between the first gate clock signal GCLK1 of FIG. 4 and the first internal clock signal ICLK1 of FIG. 5 is less than the reference time RT of FIGS. A clock signal GCLK1 and the first internal clock signal ICLK1.

1 to 5 and 6B, the time difference between the first gate clock signal GCLK1 and the first internal clock signal ICLK1 is smaller than the reference time RT.

The comparator 240 of the gate clock signal compensator 200 compares the time difference between the gate clock signal GCLK and the internal clock signal ICLK and the reference time RT, The gate clock signal GCLK from the gate clock signal GCLK and the internal clock signal ICLK when the time difference between the clock signal GCLK and the internal clock signal ICLK is less than the reference time RT And outputs it as the selected clock signal SCLK.

6B, when the time difference between the first gate clock signal GCLK1 and the first internal clock signal ICLK1 is smaller than the reference time RT, the gate clock signal compensation The comparing unit 240 of the comparator unit 200 may compare the first gate clock signal GCLK1 among the first gate clock signal GCLK1 and the first internal clock signal ICLK1 as the selected clock signal SCLK Can be output.

FIG. 7 is a timing diagram showing the compensation gate clock signal CGCLK of FIGS. 1 and 2. FIG.

1 to 7, the compensation gate clock signal CGCLK includes first to N-th compensation gate clocks for the timings of the first to N-th gate signals GS1, GS2, ..., GSN, Signals CGCLK1, CGCLK2, ..., GCLKN.

The level shifter unit 250 increases the level of the selected clock signal SCLK and outputs the compensation gate clock signal CGCLK. Therefore, the level shifter 250 increases the level of the selected internal clock signal ICLK or the gate clock signal GCLK to output the compensation gate clock signal CGCLK. For example, the selected clock signal SCLK input to the level shifter 250 may have an amplitude of about 3.3 volts, and the compensation gate clock signal CLK output from the level shifter 250 CGCLK) may have an amplitude of about 30 volts.

8 is a flowchart showing a driving method of the display device 100 of FIG.

Referring to FIGS. 1 to 8, the internal clock signal ICLKB is generated based on the interval data PD of the internal clock signal ICLK and the vertical start signal STV (step S110).

Specifically, the lookup table unit 210 receives and stores the reference time RT and the interval data PD. The lookup table unit 210 may include a memory for receiving and storing the reference time RT and the interval data PD.

The signal generator 220 receives the vertical start signal STV from the timing controller 150 and receives the interval data PD from the lookup table unit 210. The signal generator 220 generates and outputs the internal clock basic signal ICLKB using the vertical start signal STV and the interval data PD. The signal generator 220 may include a signal generator for generating and outputting the internal clock base signal ICLKB.

The internal clock base signal ICLKB includes the first interval P1, the second interval P2, and the third interval P3. The first interval P1 is from the rise time of the vertical start signal STV to the rise time of the internal clock base signal ICLKB. The second period P2 is from the rise time of the internal clock base signal ICLKB to the fall time of the internal clock base signal ICLKB. The third interval P3 is from the falling time of the internal clock base signal ICLKB to the rising time of the internal clock base signal ICLKB.

The first interval P1, the second interval P2 and the third interval P3 of the internal clock basic signal ICLKB may be included in the interval data PD and the gate clock signal GCLK As shown in FIG. Accordingly, the signal generator 220 can generate and output the internal clock base signal ICLKB using the vertical start signal STV and the interval data PD.

The internal clock signal ICLK is generated based on the internal clock basic signal ICLKB (step S120).

The internal clock signal generator 230 receives the internal clock signal ICLKB from the signal generator 220 and generates the internal clock signal ICLKB based on the internal clock signal ICLKB. ICLK). The internal clock signal generator 230 may include a signal generator for generating and outputting the internal clock signal ICLK.

The internal clock signal ICLK1 includes the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN. Each of the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN has no jitter. Each of the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN is generated based on the internal clock base signal ICLKB.

Specifically, each of the first to N-th internal clock signals ICLK1, ICLK2, ..., ICLKN may occur in response to a rising edge of the internal clock base signal ICLKB. For example, the first internal clock signal ICLK1 of the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN is supplied to the first rising edge of the internal clock base signal ICLKB And may have a high level during the second interval (P2) of the internal clock base signal (ICLKB). Also, for example, the second internal clock signal ICLK2 of the first to Nth internal clock signals ICLK1, ICLK2, ... ICLKN may be the second rising Edge and may have a high level during the second interval P2 of the internal clock base signal ICLKB. For example, the N-th internal clock signal ICLKN of the first to N-th internal clock signals ICLK1, ICLK2, ..., and ICLKN is the N-th rise of the internal clock base signal ICLKB Edge and may have a high level during the second interval P2 of the internal clock base signal ICLKB.

It is determined whether the time difference between the gate clock signal GCLK and the internal clock signal ICLK is equal to or greater than the reference time RT (step S130).

Specifically, the comparator 240 receives the gate clock signal GCLK from the timing controller 150, receives the internal clock signal ICLK from the internal clock signal generator 230, Unit 210 receives the reference time RT. The comparator 240 selects one of the gate clock signal GCLK and the internal clock signal ICLK based on the time difference between the gate clock signal GCLK and the internal clock signal ICLK And outputs it as the selected clock signal SCLK.

The comparator 240 compares the gate clock signal GCLK and the internal clock signal ICLK with each other, and a comparator 240 comparing a time difference between the gate clock signal GCLK and the internal clock signal ICLK, And a second comparator for comparing the reference time (RT).

The internal clock signal ICLK is selected to output the selected clock signal SCLK if the time difference between the gate clock signal GCLK and the internal clock signal ICLK is equal to or greater than the reference time RT S140).

Specifically, when the time difference between the gate clock signal GCLK and the internal clock signal ICLK is equal to or greater than the reference time RT, the comparator 240 compares the gate clock signal GCLK and the internal clock signal ICLK ICLK, and outputs the internal clock signal ICLK as the selected clock signal SCLK.

And selects the gate clock signal GCLK and outputs the selected clock signal SCLK when the time difference between the gate clock signal GCLK and the internal clock signal ICLK is less than the reference time RT S150).

If the time difference between the gate clock signal GCLK and the internal clock signal ICLK is less than the reference time RT, the comparator 240 compares the gate clock signal GCLK and the internal clock signal ICLK, ICLK, and outputs the gate clock signal GCLK as the selected clock signal SCLK.

And increases the level of the selected clock signal SCLK to output the compensation gate clock signal CGCLK (step S160).

Specifically, the level shifter 250 increases the level of the selected clock signal SCLK to output the compensation gate clock signal CGCLK. Therefore, the level shifter 250 increases the level of the selected internal clock signal ICLK or the gate clock signal GCLK to output the compensation gate clock signal CGCLK. For example, the selected clock signal SCLK input to the level shifter 250 may have an amplitude of about 3.3 volts, and the compensation gate clock signal CLK output from the level shifter 250 CGCLK) may have an amplitude of about 30 volts. The level shifter unit 250 may include a level shifter for increasing the level of the selected clock signal SCLK.

The first to Nth gate signals GS1, GS2, ..., GSN are generated using the compensation gate clock signal CGCLK, and the first to Nth gate signals GS1, GS2, , And GSN to the first to Nth gate lines GL1, GL2, ..., and GLN (step S170).

The gate driving unit 130 receives the first to Nth gate signals GS1, GS2, ..., GSN using the compensation gate clock signal CGCLK provided from the voltage manager 160, And outputs the first to Nth gate signals GS1, GS2, ..., GSN to the first to Nth gate lines GL1, GL2, ..., and GLN, respectively. The gate driver 130 may include a gate driver or a gate driver.

Generates the data signal DS using the data clock signal DCLK and outputs the data signal DS to the data line DL (step S180).

The data driver 140 receives the image data DATA from the timing controller 150 and generates the data signal DS using the image data DATA and outputs the data signal DS from the timing controller 150 And outputs the data signal DS to the data line DL in response to the provided horizontal start signal STH and the data clock signal DCLK. The data driver 140 may include the data driver ICs 145 that generate the data signals DS and output the data signals DS to the data lines DL. The data driver 140 may output the data signal DS to the data line DL by using the driving voltage DRV provided from the voltage manager 160. The data driver 140 may include a data driver or a data driver.

In the present embodiment, the gate clock signal compensating unit 200 is included in the voltage managing unit 160, but is not limited thereto. Therefore, the gate clock signal compensator 200 may be disposed outside the voltage manager 160.

Also, in this embodiment, the internal clock signal ICLK may be referred to as a clock signal, the internal clock signal ICLKB may be referred to as a clock based signal, and the internal clock signal ICLK may be generated The internal clock signal generator 230 may be referred to as a clock signal generator.

According to the present embodiment, the gate clock signal compensator 200 may compensate for the jitter included in the gate clock signal GCLK and output the compensation gate clock signal GCLK. The gate driver 130 generates the first to Nth gate signals GS1, GS2, ..., GSN using the compensated gate clock signal GCLK with compensated jitter. Therefore, in the image displayed on the display panel 110, the horizontal line luminance deviation displayed by the jitter can be reduced. Therefore, the display quality of the display device 100 can be improved.

Example 2

9 is a block diagram illustrating a gate clock signal compensator according to an embodiment of the present invention.

The gate clock signal compensator 300 according to the present embodiment shown in FIG. 9 may be included in the voltage manager 160 of the display device 100 according to the previous embodiment shown in FIG. The display device 100 including the gate clock signal compensator 300 according to the present embodiment shown in FIG. 9 is different from the display device 100 according to the previous embodiment shown in FIG. 1 And may be substantially the same except for the gate clock signal compensator 300. [ Therefore, the same members as those of the previous embodiment can be represented by the same reference numerals, and redundant detailed explanations can be omitted.

1 and 9, the gate clock signal compensator 300 includes a lookup table unit 310, a signal generator 320, an internal clock signal generator 330, and a level shifter 340 .

The lookup table unit 310 receives and stores the interval data PD. The lookup table unit 310 may include a memory for receiving and storing the interval data PD.

The signal generator 320 receives the vertical start signal STV from the timing controller 150 and receives the interval data PD from the lookup table unit 310. The signal generator 320 generates and outputs the internal clock base signal ICLKB using the vertical start signal STV and the interval data PD. The signal generator 320 may include a signal generator for generating and outputting the internal clock base signal ICLKB.

The internal clock signal generator 230 receives the internal clock base signal ICLKB from the signal generator 220 and generates the internal clock signal ICLK based on the internal clock base signal ICLKB And output. The internal clock signal generator 230 may include a signal generator for generating and outputting the internal clock signal ICLK.

The level shifter 340 increases the level of the internal clock signal ICLK and outputs the compensation gate clock signal CGCLK. For example, the internal clock signal ICLK input to the level shifter 340 may have an amplitude of about 3.3 volts, and the compensation gate clock signal < RTI ID = 0.0 > CGCLK) may have an amplitude of about 30 volts. The level shifter 340 may include a level shifter for increasing the level of the internal clock signal ICLK.

10 is a flowchart illustrating a method of driving the display device 100 including the gate clock signal compensator 300 of FIG.

1, 3 to 5, 7, 9 and 10, the internal clock base signal ICLKB is generated based on the interval data PD of the internal clock signal ICLK and the vertical start signal STV (Step S210).

Specifically, the lookup table unit 310 receives and stores the interval data PD. The lookup table unit 310 may include a memory for receiving and storing the interval data PD.

The signal generator 320 receives the vertical start signal STV from the timing controller 150 and receives the interval data PD from the lookup table unit 310. The signal generator 320 generates and outputs the internal clock base signal ICLKB using the vertical start signal STV and the interval data PD. The signal generator 320 may include a signal generator for generating and outputting the internal clock base signal ICLKB.

The internal clock base signal ICLKB includes the first interval P1, the second interval P2, and the third interval P3. The first interval P1 is from the rise time of the vertical start signal STV to the rise time of the internal clock base signal ICLKB. The second period P2 is from the rise time of the internal clock base signal ICLKB to the fall time of the internal clock base signal ICLKB. The third interval P3 is from the falling time of the internal clock base signal ICLKB to the rising time of the internal clock base signal ICLKB.

The first interval P1, the second interval P2 and the third interval P3 of the internal clock basic signal ICLKB may be included in the interval data PD and the gate clock signal GCLK As shown in FIG. Accordingly, the signal generator 320 may generate and output the internal clock base signal ICLKB using the vertical start signal STV and the interval data PD.

The internal clock signal ICLK is generated based on the internal clock basic signal ICLKB (step S220).

Specifically, the internal clock signal generator 330 receives the internal clock base signal ICLKB from the signal generator 320 and generates the internal clock signal ICLKB based on the internal clock base signal ICLKB. ICLK). The internal clock signal generator 330 may include a signal generator for generating and outputting the internal clock signal ICLK.

The internal clock signal ICLK1 includes the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN. Each of the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN has no jitter. Each of the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN is generated based on the internal clock base signal ICLKB.

Specifically, each of the first to N-th internal clock signals ICLK1, ICLK2, ..., ICLKN may occur in response to a rising edge of the internal clock base signal ICLKB. For example, the first internal clock signal ICLK1 of the first to Nth internal clock signals ICLK1, ICLK2, ..., ICLKN is supplied to the first rising edge of the internal clock base signal ICLKB And may have a high level during the second interval (P2) of the internal clock base signal (ICLKB). Also, for example, the second internal clock signal ICLK2 of the first to Nth internal clock signals ICLK1, ICLK2, ... ICLKN may be the second rising Edge and may have a high level during the second interval P2 of the internal clock base signal ICLKB. For example, the N-th internal clock signal ICLKN of the first to N-th internal clock signals ICLK1, ICLK2, ..., and ICLKN is the N-th rise of the internal clock base signal ICLKB Edge and may have a high level during the second interval P2 of the internal clock base signal ICLKB.

The level of the internal clock signal ICLK is increased to output the compensation gate clock signal CGCLK (step S230).

Specifically, the level shifter 340 increases the level of the internal clock signal ICLK and outputs the compensation gate clock signal CGCLK. For example, the internal clock signal ICLK input to the level shifter 340 may have an amplitude of about 3.3 volts, and the compensation gate clock signal < RTI ID = 0.0 > CGCLK) may have an amplitude of about 30 volts. The level shifter 340 may include a level shifter for increasing the level of the internal clock signal ICLK.

The first to Nth gate signals GS1, GS2, ..., GSN are generated using the compensation gate clock signal CGCLK, and the first to Nth gate signals GS1, GS2, , And GSN to the first to Nth gate lines GL1, GL2, ..., and GLN (step S240).

The gate driving unit 130 receives the first to Nth gate signals GS1, GS2, ..., GSN using the compensation gate clock signal CGCLK provided from the voltage manager 160, And outputs the first to Nth gate signals GS1, GS2, ..., GSN to the first to Nth gate lines GL1, GL2, ..., and GLN, respectively. The gate driver 130 may include a gate driver or a gate driver.

The data signal DS is generated using the data clock signal DCLK and the data signal DS is output to the data line DL in operation S250.

The data driver 140 receives the image data DATA from the timing controller 150 and generates the data signal DS using the image data DATA and outputs the data signal DS from the timing controller 150 And outputs the data signal DS to the data line DL in response to the provided horizontal start signal STH and the data clock signal DCLK. The data driver 140 may include the data driver ICs 145 that generate the data signals DS and output the data signals DS to the data lines DL. The data driver 140 may output the data signal DS to the data line DL by using the driving voltage DRV provided from the voltage manager 160. The data driver 140 may include a data driver or a data driver.

In the present embodiment, the gate clock signal compensating unit 300 is included in the voltage managing unit 160, but is not limited thereto. Therefore, the gate clock signal compensator 200 may be disposed outside the voltage manager 160.

Also, in the present embodiment, the internal clock signal ICLK may be referred to as a clock signal, the internal clock signal ICLKB may be referred to as a clock based signal, and the internal clock signal ICLK may be generated The internal clock signal generator 30 may be referred to as a clock signal generator.

According to the present embodiment, the gate clock signal compensator 300 may compensate for the jitter included in the gate clock signal GCLK and output the compensation gate clock signal GCLK. The gate driver 130 generates the first to Nth gate signals GS1, GS2, ..., GSN using the compensated gate clock signal GCLK with compensated jitter. Therefore, in the image displayed on the display panel 110, the horizontal line luminance deviation displayed by the jitter can be reduced. Therefore, the display quality of the display device 100 can be improved.

The present invention can be applied to all electronic apparatuses having a display device. For example, the present invention may be applied to a variety of portable devices such as televisions, computer monitors, notebooks, digital cameras, cell phones, smart phones, tablet PCs, smart pads, PDAs, , A camcorder, a portable game machine, and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. You will understand.

100: display device 110: display panel
130: Gate driver 140: Data driver
150: timing control unit 160:
200, 300: gate clock signal compensating unit
210, 310: lookup table unit 220, 320:
230, 330: Internal clock signal generator
240: comparator 250, 340: level shifter

Claims (20)

A display panel that displays an image and includes a gate line and a data line;
A gate driver for outputting a gate signal to the gate line;
A data driver for outputting a data signal to the data line;
A timing controller for outputting a vertical start signal and a gate clock signal used for outputting the gate signal; And
And generates a clock signal based on the vertical start signal and generates a clock signal based on a comparison of a time difference between the gate clock signal and the clock signal and a reference time which is a jitter tolerance standard of the gate clock signal, And a gate clock signal compensator for selectively outputting the clock signal and raising the level of the selected gate clock signal or clock signal to output the raised gate clock signal or clock signal as a compensated gate clock signal to the gate driver / RTI > The display device according to claim 1, wherein when the time difference between the gate clock signal and the clock signal is equal to or greater than the reference time, the gate clock signal compensator selects the clock signal from among the gate clock signal and the clock signal Device. 3. The display device of claim 2, wherein the gate clock signal compensator includes a lookup table unit for storing the reference time. The display device of claim 1, wherein the gate clock signal compensator includes a lookup table unit for storing interval data of a clock signal based on the clock signal. The display device of claim 4, wherein the gate clock signal compensator comprises a signal generator for generating the clock base signal in accordance with the vertical start signal and the interval data. The apparatus of claim 5, wherein the interval data of the clock base signal includes a first period from a rising time of the vertical start signal to a rise time of the clock base signal, a falling period of the clock base signal from a rising time of the clock base signal And a third period from a falling time of the clock base signal to a rise time of the clock base signal. The display device of claim 1, wherein the gate clock signal compensator comprises a clock signal generator for generating the clock signal in response to a rising edge of the clock base signal. The apparatus of claim 1, wherein the gate clock signal compensator includes a comparator that compares the gate clock signal and the clock signal, and compares a time difference between the gate clock signal and the clock signal and the reference time, / RTI > The apparatus of claim 1, wherein when the time difference between the gate clock signal and the clock signal is less than the reference time, the gate clock signal compensator selects the gate clock signal from among the gate clock signal and the clock signal Display device. The method according to claim 1,
And a voltage management unit for outputting a driving voltage to the data driver,
And the gate clock signal compensating unit is included in the voltage managing unit. The display device according to claim 10, wherein the display panel is a liquid crystal display panel including a liquid crystal, and the voltage management unit further outputs a common voltage to the display panel. A display panel that displays an image and includes a gate line and a data line;
A gate driver for outputting a gate signal to the gate line;
A data driver for outputting a data signal to the data line;
A timing controller for outputting a vertical start signal and a gate clock signal used for outputting the gate signal; And
And a gate clock signal compensator for generating a clock signal based on the vertical start signal and raising the level of the clock signal and outputting the raised clock signal as a compensated gate clock signal to the gate driver. 13. The display device of claim 12, wherein the gate clock signal compensator includes a lookup table unit for storing interval data of a clock signal based on the clock signal. 14. The display device according to claim 13, wherein the gate clock signal compensator comprises a signal generator for generating the clock base signal in accordance with the vertical start signal and the interval data. 15. The method of claim 14, wherein the interval data of the clock base signal includes a first period from a rise time of the vertical start signal to a rise time of the clock base signal, And a third period from a falling time of the clock base signal to a rise time of the clock base signal. 13. The display device according to claim 12, wherein the gate clock signal compensator includes a clock signal generator for generating the clock signal in response to a rising edge of the clock base signal. 13. The method of claim 12,
And a voltage management unit for outputting a driving voltage to the data driver,
And the gate clock signal compensating unit is included in the voltage managing unit. 18. The display device according to claim 17, wherein the display panel is a liquid crystal display panel including liquid crystal, and the voltage management unit further outputs a common voltage to the display panel. 13. The display device according to claim 12, wherein the gate clock signal has a jitter. Generating a clock based signal based on the interval data of the clock based signal and the vertical start signal;
Generating a clock signal based on the clock based signal;
Determining whether a time difference between the clock signal and the gate clock signal is equal to or greater than a reference time that is a jitter tolerance criterion of the gate clock signal;
Selecting the clock signal from among the gate clock signal and the clock signal and outputting the clock signal as a selected clock signal when the time difference between the gate clock signal and the clock signal is equal to or greater than the reference time;
Selecting the gate clock signal among the gate clock signal and the clock signal and outputting the selected clock signal as the selected clock signal when the time difference between the gate clock signal and the clock signal is less than the reference time;
Increasing the level of the selected clock signal and outputting the increased selected clock signal as a compensating gate clock signal;
Generating a gate signal using the compensation gate clock signal and outputting the gate signal to a gate line of the display panel; And
And outputting a data signal to a data line of the display panel.

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