KR20080000918A - Liquid crystal display and method for driving the same - Google Patents

Abstract

An LCD device and a driving method thereof are provided to improve image quality by stabilizing the output characteristics of scan signals causing brightness line noises and image deterioration. An LCD(Liquid Crystal Display) device includes a liquid crystal panel(200), a timing controller(230), and gate and data drivers(210,220). The liquid crystal panel includes plural pixels disposed gate and data lines in matrix. The timing controller receives spread clock signals within a frequency range based on a spread spectrum scheme, generates reference gate and data control signals using the spread clock signals, and generates modulation gate control signals by adjusting the reference gate control signal so as to have a pulse width. The gate driver drives the gate lines according to the modulation gate control signals. The data driver drives the data lines according to the data control signal.

Description

Liquid crystal display and method for driving the same {Liquid crystal display and method for driving the same}

1 is a configuration diagram of a liquid crystal display according to the prior art.

2A to 2C are signal waveform diagrams illustrating a pixel charging time of FIG. 1.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a detailed configuration diagram of the timing controller shown in FIG. 3.

5 is a signal waveform diagram illustrating a pixel charge time of FIG. 3.

6 is a configuration diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

7 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

200: liquid crystal panel 210: gate driver

220: data driver 230: timing controller

231: interface unit 232: timing unit

233: modulator 234: oscillator

235: data processor 240: system

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device using a spread spectrum and a driving method thereof.

The liquid crystal display device forms a liquid crystal layer having anisotropic dielectric constant between upper and lower substrates, which are transparent insulating substrates, and then adjusts the intensity of the electric field formed in the liquid crystal layer to change the molecular arrangement of the liquid crystal material, thereby The display device expresses a desired image by adjusting the amount of light transmitted through the upper substrate. As the liquid crystal display, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

1 is a configuration diagram of a liquid crystal display according to the prior art.

Referring to FIG. 1, the liquid crystal display according to the related art includes a liquid crystal panel 100, a gate driver 110, a data driver 120, a timing controller 130, a spread spectrum IC 140, and the like.

The liquid crystal panel 100 includes a plurality of pixels P divided into gate lines GL1, GL2,..., GLn, and data lines DL1, DL2..., DLm that cross each other. Thin film transistors having a gate electrode, an active layer, a source electrode, and a drain electrode are disposed at the intersections of the gate lines GL1, GL2, ..., GLn and the data lines DL1, DL2, ..., DLm. Is placed.

Each pixel P is filled with a liquid crystal material equivalent to the liquid crystal cell Clc, and a storage capacitor Cst is formed to maintain a constant voltage charged in the liquid crystal cell Clc.

The liquid crystal panel 100 may be configured according to scan signals supplied through the gate lines GL1, GL2,..., And GLn and analog pixel signals supplied through the data lines DL1, DL2,..., And DLm. An image is displayed on the pixel P.

The thin film transistor TFT provided for each pixel P is turned on when the gate high voltage of the scan signal from the gate lines GL1, GL2,..., GLn is supplied, thereby turning on the data lines DL1, DL2, ..., analog pixel signals from DLm are supplied to the liquid crystal cell Clc. When the gate low voltage is supplied from the gate lines GL1, GL2,..., GLn, the signal is turned off to maintain the analog pixel signal charged in the liquid crystal cell Clc.

The gate driver 110 sequentially supplies scan signals to the gate lines GL1, GL2,..., GLn according to the gate control signal GCS0 supplied from the timing controller 130. The gate control signal GCS0 includes a gate start pulse signal GSP, a gate shift clock signal GSC, a gate output enable signal GOE, and the like.

The data driver 120 analogizes the red, green, and blue pixel data R, G, and B input from the timing controller 130 in response to the data control signal DCS supplied from the timing controller 23. It converts the pixel signal and supplies it to the data lines DL1, DL2, ..., DLm.

The data control signal includes a source start pulse SSP, a source shift clock SSC, a source output enable SOC, a polarity signal POL, and the like. The gamma voltage is selected corresponding to the green and blue pixel data (R, G, B).

The timing controller 130 receives various clock signals DE0, H0, V0, and DCLK together with the red, green, and blue pixel data R, G, and B input from the external system 150. By using this, a gate control signal GCS0 and a data control signal DCS for controlling driving timings of the gate driver 110 and the data driver 120 are generated.

The clock signals transmitted from the system 150 to the timing controller 130 include data enable signals DE0, horizontal and vertical synchronization signals H0 and V0, and data clock signals DCLK.

The spread spectrum IC 140 spreads and modulates a clock signal having a constant frequency for frequency spread, and adjusts an oscillation frequency using a phase-locked loop (PLL) circuit according to the modulated frequency. As a result, the clock signal SCLK is changed at regular intervals within a specific frequency range.

As such, the spread spectrum IC 140 generates the clock signal SCLK, which is frequency spread within a specific frequency range, and supplies the generated spread signal to the timing controller 130 according to a spread spectrum scheme.

Accordingly, the frequencies of the control signals GCS0 and DCS generated by the timing controller 130 are not kept constant, but within a specific frequency range along the clock signal SCLK transmitted from the spread spectrum IC 140. It has a shaky form in.

As a result, a frequency at which electromagnetic interference between various control signals GCS0 and DCS and pixel data R, G, and B transmitted from the timing controller 130 to the gate driver 110 and the data driver 120 is shaken. The effect of offsetting and decreasing can be obtained.

2A to 2C are signal waveform diagrams illustrating the pixel charging time of FIG. 1, and illustrate waveforms of scan signals when the gate output enable signal GOE changes to GOE_1, GOE_2, and GOE_3 by applying a spread spectrum. have.

Since the spreading period of the clock signal SCLK changing within a specific frequency range is not synchronized with the horizontal period signal Hsync, a control signal generated by counting the clock signal SCLK based on the horizontal synchronization signal Hsync The pulse width of the field GCS0 is changed for each horizontal period.

2A to 2C, in any k-th, k-1th, k + 1th frame, the gate output enable signal GOE is changed to a signal of GOE_1, GOE_2, and GOE_3 having different pulse widths, respectively. . As a result, as shown by the waveforms of Gate Out_1, Gate Out_2, and Gate Out_3, the pixel charge time T1 <T0 <T2 corresponding to the high period of the scan signal output from the gate driver 110 varies depending on the frame. Able to know.

That is, the control signals GCS0 and DCS are shaken while the clock signal SCLK is input from the spread spectrum IC 140 of FIG. 1 to the timing controller 130. At this time, as the gate control signal GCS0 controlling the gate driver 110 is shaken, the output characteristic of the gate driver 120 is changed, and thus the luminance is not uniform as the pixel charging times T0, T1, and T2 are changed. There was a problem.

In particular, when excessive spread spectrum is used or when device characteristics of the spread spectrum IC 140 and the timing controller 130 are not well matched, a line noise or a waterfall noise that causes the screen to flow down like a waterfall may occur. The image quality was severely degraded.

Accordingly, an object of the present invention is to provide a liquid crystal display device which can improve image quality by stabilizing output characteristics of a scan signal which causes degradation of image quality such as bright line / line noise when using a spread spectrum.

Another object of the present invention is to provide a method of driving a liquid crystal display device capable of efficiently driving such a liquid crystal display device.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

The liquid crystal display according to the present invention for achieving the above technical problem is a liquid crystal panel having a plurality of pixels in which the gate lines and the data lines are arranged in a matrix form, within a predetermined frequency range according to a spread spectrum method Receives a frequency spread spread clock signal, generates a reference gate control signal and a data control signal using the spread clock signal, and generates a modulated gate control signal by varying the reference gate control signal to have a constant pulse width A timing controller unit, a gate driver driving the gate lines according to the modulation gate control signal, and a data driver driving the data lines according to the data control signal.

The spread clock signal may be a signal such as a data enable signal DE, a horizontal sync signal Hsync, a vertical sync signal Vsync, and a data clock signal CLK.

The timing controller unit includes a timing unit generating the data control signal and the reference gate control signal using the spread clock signal, an oscillator unit oscillating a reference clock signal, and in response to the reference clock signal output from the oscillator unit. And a modulator configured to modulate a reference gate control signal into the modulated gate control signal.

The modulation gate control signal may be a signal such as a gate shift clock signal GSC, a gate start pulse signal GSP, a gate output enable signal GOE, a gate modulation control signal FLK, and the like.

In addition, the liquid crystal display according to the present invention is a liquid crystal panel having a plurality of pixels in which the gate lines and the data lines are arranged in a matrix form, and a spread clock having a frequency spread within a predetermined frequency range according to a spread spectrum method. A timing controller unit receiving a signal and generating a reference gate control signal and a data control signal using the spread clock signal, an oscillator unit generating a reference clock signal, and fixing the reference gate control signal using the reference clock signal A modulation unit generating a modulation gate control signal by varying a pulse width, a gate driver driving the gate lines according to the modulation gate control signal, and a data driver driving the data lines according to the data control signal. have.

The spread clock signal may be a signal such as a data enable signal DE, a horizontal sync signal Hsync, a vertical sync signal Vsync, and a data clock signal CLK.

The modulation gate control signal may be a signal such as a gate shift clock signal GSC, a gate start pulse signal GSP, a gate output enable signal GOE, a gate modulation control signal FLK, and the like.

In addition, the driving method of the liquid crystal display according to the present invention comprises the steps of: (a) receiving a spread clock signal frequency spread within a predetermined frequency range according to a spread spectrum method from the outside, (b) the spread clock Generating a reference gate control signal and a data control signal by using a signal, (c) generating a modulation gate control signal by varying the reference gate control signal to have a constant pulse width, and (d) the modulation gate control signal (E) supplying an analog pixel signal according to the data control signal, and (f) displaying an image on pixels of the liquid crystal panel by the scan signal and the analog pixel signal. It includes.

The spread clock signal of step (a) may be a signal such as a data enable signal DE, a horizontal sync signal Hsync, a vertical sync signal Vsync, and a data clock signal CLK.

The step (c) may include generating a reference clock signal having a predetermined frequency, and converting the reference gate control signal into the modulated gate control signal having a constant pulse width in response to the reference clock signal. have.

The modulation gate control signal of step (c) may be a signal such as a gate shift clock signal GSC, a gate start pulse signal GSP, a gate output enable signal GOE, a gate modulation control signal FLK, and the like.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, a liquid crystal display according to an exemplary embodiment and another exemplary embodiment will be described in detail with reference to FIGS. 3 to 6.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 200 having a plurality of pixels P arranged in a matrix form, and gate lines GL1 and GL2 of the liquid crystal panel 200. ,..., GLn and gate driver 210 and data driver 220 for driving the data lines DL1, DL2,..., DLm, respectively, and a timing controller 230 for controlling driving timing thereof. ), And the like.

The liquid crystal panel 200 includes pixels P formed for each region defined by the cross arrangement of the gate lines GL1, GL2,..., GLn and the data lines DL1, DL2..., DLm. Have Each pixel P includes a liquid crystal cell Clc for adjusting light transmittance according to an analog pixel signal, a thin film transistor TFT for driving the liquid crystal cell Clc, and an analog pixel signal charged in the liquid crystal cell Clc. A storage capacitor Cst or the like is configured to keep the analog pixel signal stable until it is charged.

The thin film transistor TFT is turned on when the gate high voltage of the scan signal is supplied from the gate lines GL1, GL2,..., GLn and the analog from the data lines DL1, DL2,. The pixel signal is supplied to the liquid crystal cell Clc. When the gate low voltage of the scan signal is supplied from the gate lines GL1, GL2,..., GLn, the analog pixel signal charged in the liquid crystal cell Clc is maintained.

The scan signal is sequentially shifted and supplied to each gate line GL1, GL2, ..., GLn for one horizontal period, and the liquid crystal cell Clc is anisotropic in accordance with the analog pixel signal charged through the thin film transistor TFT. Gray level is realized by adjusting the light transmittance while the arrangement of the liquid crystal having the dielectric constant is changed.

The gate driver 210 supplies a scan signal to the gate lines GL1, GL2,... GLn of the liquid crystal panel 200 in response to the modulation gate control signal GCS. The modulation gate control signal GCS includes a gate start pulse signal GSP, a gate shift clock signal GSC, a gate output enable signal GOE, a gate modulation control signal FLK, and the like (see FIG. 4). .

More specifically, the gate driver 210 shifts the gate start pulse signal GSP from the timing controller 230 according to the gate shift clock signal GSC to gate lines GL1, GL2,... The scan signals are sequentially supplied to GLn). Here, the gate driver 210 modulates the scan signal by controlling the pulse width of the scan signal or the falling time of the gate high voltage according to the gate output enable signal GOE or the gate modulation control signal FLK. do.

The data driver 220 drives the data lines DL1, DL2,..., DLm in response to the data control signal DCS. The data control signal DCS includes a source start pulse signal SSP, a source shift clock signal SSC, a source output enable signal SOC, a polarity control signal POL, and the like.

More specifically, the data driver 220 shifts the source start pulse signal SSP from the timing controller 230 according to the source shift clock signal SSC to generate a sampling signal. Then, the red, green, and blue pixel data R, G, and B input from the external system 240 are latched according to the sampling signal according to the source shift clock signal SSC, and then the source output enable signal SOE is latched. In line by line).

The pixel data R, G, and B supplied in line units are converted into analog pixel signals using gamma voltages, and then supplied to the data lines DL1, DL2, ..., DLm. When converting the pixel data R, G, and B into an analog pixel signal, the polarity of the corresponding signal is determined in response to the polarity control signal POL from the timing controller 230. The data driver 220 determines a period during which the analog pixel signal is supplied to the data lines DL1, DL2,..., DLm in response to the source output enable signal SOE.

The timing controller 230 receives the red, green, and blue pixel data R, G, and B from the system 240 and transmits the data to the data driver 220, and various clock signals DE, Hsync, Vsync, CLK is used to generate a modulation gate control signal GCS and a data control signal DCS.

Here, the clock signals DE, Hsync, Vsync, and CLK output from the system 240 to the timing controller 230 are spread clock signals frequency-spread within a specific frequency range according to a spread spectrum method. .

The system 240 spreads clock signals of a constant frequency to change with a certain spreading period within a specific frequency range to generate clock signals DE, Hsync, Vsync, and CLK for controlling the timing controller 230. The clock signals DE, Hsync, Vsync, and CLK are transmitted to the timing controller 230. For example, when a clock signal having a frequency of 65 MHz is used, the spread clock signal has a frequency that increases and decreases with a constant spread period between 62.25 MHz and 67.25 MHz.

In some devices such as notebook computers, it is efficient to make the overall structure as simple as possible by not having a separate spread spectrum IC, thereby making the device light in weight.

In this case, a spread clock signal frequency spread by a spread spectrum method is generated and transmitted on the system 240 without having a separate spread spectrum IC.

However, when the output characteristics of the liquid crystal display and the system 240 do not match well or the spread spectrum is excessively applied, clocks that control the driving timing of the data driver 220 or the gate driver 210 are shaken, and the line / line noise Defects may appear. In particular, when the driving timing of the gate driver 210 is shaken, the image quality may be seriously degraded due to side effects such as insufficient pixel charging time.

According to the present invention, in order to solve this problem, a modulation gate control signal (GCS) is used to secure a pixel charging time in spread spectrum application. As a result, despite the application of the spread spectrum, the output characteristics of the gate driver 210 are stabilized, thereby realizing the effect of canceling the electromagnetic interference and improving the image quality at the same time.

4 is a detailed configuration diagram of the timing controller shown in FIG. 3.

The timing controller 230 receives various clock signals DE, Hsync, Vsync, and CLK frequency-spread by an spread spectrum method from an external system 240, and receives the received clock signals DE, Hsync, and Vsync. , The reference gate control signal GCS1 and the data control signal DCS are generated using the CLK. The reference gate control signal GCS1 is varied to have a constant pulse width to generate a modulation gate control signal GCS.

Referring to FIG. 4, the timing controller 230 includes an interface unit 231, a timing unit 232, a modulator 233, an oscillator unit 234, a data processor unit 235, and the like.

The interface unit 231 receives red, green, and blue pixel data R, G, and B and frequency-spread various clock signals DE, Hsync, Vsync, and CLK input from an external system 240. Transfer to each component.

The timing unit 232 combines the vertical and horizontal synchronization signals Vsync and Hsync, the data enable signal DE, and the data clock signal CLK to combine the data control signal DCS and the reference gate control signal GCS1. Create

The modulator 233 generates a modulated gate control signal GCS that has a predetermined pulse width from the reference gate control signal GCS1 in response to the reference clock signal ACLK input from the oscillator unit 234.

As the reference gate control signal GCS1 and the modulation gate control signal GCS, gate shift clock signals GSC1 and GSC, gate start pulse signals GSP1 and GSP, gate output enable signals GOE1 and GOE, and gate modulation control. Signals FLK1, FLK, and the like.

The oscillator unit 234 oscillates the reference clock signal ACLK having a constant frequency.

The data processor 235 receives and latches and outputs red, green, and blue pixel data R, G, and B through the interface unit 231.

As such, the timing controller 230 generates the reference gate control signal GCS2 and the data control signal DCS by using the clock signals DE, Hsync, Vsync, and CLK having been spread with frequency. .

In addition, the data control signal DCS is directly output through the timing unit 232, and the reference gate control signal GCS1 may have a serious adverse effect on the output characteristic of the gate driver 210 due to the occurrence of shaking due to frequency diffusion. The variable is converted into a stable modulation gate control signal GCS via the modulator 233 and then transmitted to the gate driver 210.

FIG. 5 is a signal waveform diagram illustrating the pixel charging time of FIG. 3, and illustrates an example of a scan signal Gate Out with respect to the gate output enable signal GOE.

In any k-th, k-1 th, k + 1 th frame, the pulse width of the gate output enable signal GOE is stabilized as shown in the waveform of FIG. 5, and as a result, the scan signal Gate Out The pixel charging time T corresponding to the high period of may be constant in every frame.

That is, even when the clock signals DE, Hsync, Vsync, and CLK whose frequencies change according to the diffusion period are input to the timing controller 230, the modulation gate control signal GCS in which the pulse width is kept constant is obtained. In this way, the output characteristics of the gate driver 210 may be stabilized, and the pixel charging time T may be secured to uniform the luminance.

6 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention, wherein a modulator 233 and an oscillator 234 for modulating the reference gate control signal GCS1 are integrated with the timing controller 230. It is shown that the case is configured separately without being integrated into.

Referring to FIG. 6, a liquid crystal display according to another exemplary embodiment of the present invention includes a liquid crystal panel 200, a gate driver 210, a data driver 220, a timing controller 230, a modulator 233, and an oscillator. Section 234 and the like.

The liquid crystal panel 200 has a plurality of pixels in which the gate lines GL1, GL2,..., GLn and the data lines DL1, DL2,..., DLm are arranged in a matrix form.

The timing controller 230 receives various clock signals DE, Hsync, Vsync, and CLK, which are frequency-spread from the outside, and generates a reference gate control signal GCS1 and a data control signal DCS using the clock signals DE, Hsync, Vsync, and CLK.

The modulator 233 generates a modulated gate control signal GCS by modulating the reference gate control signal GCS1 to have a predetermined pulse width using the reference clock signal ACLK, and transmits the modulated gate control signal GCS to the gate driver 210. .

The gate driver 210 drives the gate lines GL1, GL2,..., GLn according to the modulation gate control signal GCS.

The data driver 220 drives the data lines DL1, DL2,..., DLm according to the data control signal DCS.

Since each component of FIG. 6 is matched with the components of FIG. 5, a detailed description thereof will be omitted.

In the case of FIG. 6, without changing the configuration of the timing controller 230 implemented in a chip form, the modulation unit 233 and the oscillator unit 234 are separately configured so that the modulation gate control signal GCS and the gate driver accordingly The output characteristic of 210 can be stabilized.

Hereinafter, a driving method of a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 7.

7 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

First, in operation S100, various clock signals DE, Hsync, Vsync, and CLK are transmitted from the system 240 to the timing controller 230. Here, the clock signals DE, Hsync, Vsync, and CLK are spread clock signals frequency-spread within a predetermined frequency range according to a spread spectrum scheme.

Next, in step S110, the timing controller 230 generates the reference gate control signal GCS1 and the data control signal DCS using the received clock signals DE, Hsync, Vsync, and CLK.

Next, in step S120, the modulator 233 modulates the reference gate control signal GCS1 into a modulation gate control signal GCS having a constant pulse width. In step S120, in step S121 in which the oscillator unit 234 generates the reference clock signal ACLK having a predetermined frequency, the modulator 233 sets the reference gate control signal GCS1 in response to the reference clock signal ACLK. It can be subdivided in step S122, which varies with a modulation gate control signal GCS having a pulse width.

In this case, the modulation gate control signal GCS is an output of the gate driver 210 such as a gate shift clock signal GSC, a gate start pulse signal GSP, a gate output enable signal GOE, a gate modulation control signal FLK, and the like. The control signal associated with the characteristic.

Next, in step S130, the gate driver 210 sequentially supplies scan signals to the gate lines GL1, GL2,... GLn of the liquid crystal panel 200 in response to the modulation gate control signal GCS. do.

Next, in step S140, the data driver 220 responds to the data control signal DCS and the analog pixel signal corresponding to one line to the data lines DL1, DL2,..., DLm of the liquid crystal panel 200. To supply.

Next, in step S150, the liquid crystal panel corresponding to the scan signal and the analog pixel signal supplied to the gate lines GL1, GL2,..., GLn and the data lines DL1, DL2,..., DLm. An image is displayed in each pixel P of 200.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that.

Therefore, since the embodiments described above are provided to completely inform the scope of the invention to those skilled in the art, it should be understood that they are exemplary in all respects and not limited. The invention is only defined by the scope of the claims.

When the spread spectrum is used, the liquid crystal display according to the exemplary embodiments of the present invention may improve image quality by stabilizing output characteristics of a scan signal that causes degradation of image quality, such as bright lines / line noise.

The driving method of the liquid crystal display according to the exemplary embodiment of the present invention can efficiently drive such a liquid crystal display.

Claims (11)

A liquid crystal panel having a plurality of pixels in which gate lines and data lines are arranged in a matrix; Receives a spread clock signal frequency spread within a predetermined frequency range according to a spread spectrum method, generates a reference gate control signal and a data control signal using the spread clock signal, and the reference gate control signal is A timing controller unit configured to generate a modulated gate control signal by varying the pulse width to have a constant pulse width; A gate driver driving the gate lines according to the modulation gate control signal; And And a data driver driving the data lines according to the data control signal. The method of claim 1, The spread clock signal is, And at least one of a data enable signal (DE), a horizontal sync signal (Hsync), a vertical sync signal (Vsync), and a data clock signal (CLK). The method of claim 1, The timing controller unit, A timing unit configured to generate the data control signal and the reference gate control signal using the spread clock signal; An oscillator unit for oscillating a reference clock signal; And And a modulation unit configured to modulate the reference gate control signal into the modulation gate control signal in response to the reference clock signal output from the oscillator unit. The method of claim 1, The modulation gate control signal, And at least one of a gate shift clock signal (GSC), a gate start pulse signal (GSP), a gate output enable signal (GOE), and a gate modulation control signal (FLK). A liquid crystal panel having a plurality of pixels in which gate lines and data lines are arranged in a matrix; A timing controller unit which receives a spread clock signal frequency spread within a predetermined frequency range according to a spread spectrum method and generates a reference gate control signal and a data control signal using the spread clock signal; An oscillator unit generating a reference clock signal; A modulator configured to generate a modulated gate control signal by varying the reference gate control signal to have a constant pulse width using the reference clock signal; A gate driver driving the gate lines according to the modulation gate control signal; And And a data driver driving the data lines according to the data control signal. The method of claim 5, The spread clock signal is, And at least one of a data enable signal (DE), a horizontal sync signal (Hsync), a vertical sync signal (Vsync), and a data clock signal (CLK). The method of claim 5, The modulation gate control signal, And at least one of a gate shift clock signal (GSC), a gate start pulse signal (GSP), a gate output enable signal (GOE), and a gate modulation control signal (FLK). (a) receiving a spread clock signal frequency-spread within a predetermined frequency range according to a spread spectrum scheme from the outside; (b) generating a reference gate control signal and a data control signal using the spread clock signal;  (c) varying the reference gate control signal to have a constant pulse width to generate a modulated gate control signal; (d) supplying a scan signal according to the modulation gate control signal; (e) supplying an analog pixel signal according to the data control signal; And and (f) displaying an image on pixels of a liquid crystal panel by the scan signal and the analog pixel signal. The method of claim 8, The spread clock signal of step (a), And at least one of a data enable signal (DE), a horizontal sync signal (Hsync), a vertical sync signal (Vsync), and a data clock signal (CLK). The method of claim 8, In step (c), Generating a reference clock signal having a predetermined frequency; And And varying the reference gate control signal into the modulated gate control signal having a constant pulse width in response to the reference clock signal. The method of claim 8, The modulation gate control signal of step (c), And a gate shift clock signal (GSC), a gate start pulse signal (GSP), a gate output enable signal (GOE), and a gate modulation control signal (FLK).

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