KR20170097255A - Display panel driving apparatus, method of driving display panel using the same and display apparatus having the same - Google Patents

Display panel driving apparatus, method of driving display panel using the same and display apparatus having the same Download PDF

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KR20170097255A
KR20170097255A KR1020160018376A KR20160018376A KR20170097255A KR 20170097255 A KR20170097255 A KR 20170097255A KR 1020160018376 A KR1020160018376 A KR 1020160018376A KR 20160018376 A KR20160018376 A KR 20160018376A KR 20170097255 A KR20170097255 A KR 20170097255A
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South Korea
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gate
data
time
signal
display panel
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KR1020160018376A
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Korean (ko)
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안익현
김윤구
박봉임
조행우
황현식
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삼성디스플레이 주식회사
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Priority to KR1020160018376A priority Critical patent/KR20170097255A/en
Publication of KR20170097255A publication Critical patent/KR20170097255A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

A display panel driving device includes a data driving unit and a gate driving unit. The data driving unit generates a data signal on the basis of image data, increases an activation time of the data signal in accordance with an increase in RC of the data line included in the display panel, and outputs the data signal to the data line. The gate driving unit increases an activation time of a gate signal in accordance with an increase in RC of the data line, and outputs the gate signal to the gate line of the display panel. Thus, the display quality of the display device can be improved.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel driving apparatus, a display panel driving method using the same, and a display device including the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel driving apparatus, a display panel driving method using the same, and a display apparatus including the same, and more particularly to a display panel driving apparatus for driving a display panel including gate lines and data lines, And a display device including the same.

The display device includes a display panel and a display panel drive device.

The display panel includes a gate line, a data line, and a pixel.

The display panel driving apparatus includes a gate driver and a data driver. The gate driver outputs a gate signal to the gate line. The data driver outputs a data signal to the data line.

The load of the data line increases with an increase in distance from the data driver, and accordingly, the RC delay of the data signal increases with an increase in the distance from the data driver.

Accordingly, it is an object of the present invention to provide a display panel driving apparatus capable of improving the display quality of a display apparatus.

Another object of the present invention is to provide a display panel driving method using the display panel driving apparatus.

It is still another object of the present invention to provide a display device including the display panel drive device.

According to an aspect of the present invention, a display panel driving apparatus includes a data driver and a gate driver. The data driver generates a data signal based on the image data and increases the activation time of the data signal according to an increase in RC of the data line included in the display panel to output the data signal to the data line. The gate driver increases the activation time of the gate signal according to the increase of the RC of the data line, and outputs the gate signal to the gate line of the display panel.

In one embodiment of the present invention, the data driver may gradually increase the activation time of the data signal according to an increase in RC of the data line.

In one embodiment of the present invention, the data driver may linearly increase the activation time of the data signal according to an increase in RC of the data line.

In one embodiment of the present invention, the gate driver may gradually increase the activation time of the gate signal according to an increase in RC of the data line.

In one embodiment of the present invention, the gate driver may linearly increase the activation time of the gate signal according to an increase in RC of the data line.

In one embodiment of the present invention, the horizontal blank time may increase with an increase in the RC of the data line.

In one embodiment of the present invention, the horizontal blank time may gradually increase with an increase in the RC of the data line.

In one embodiment of the present invention, the horizontal blank time may linearly increase with an increase in the RC of the data line.

In one embodiment of the present invention, the gate lines may include first to Nth gate lines (N is a natural number of 4 or more), and the gate signals may be respectively output to the first to Nth gate lines And the first to the Nth gate signals, and when the first gate signal is activated among the gate signals, the time when the data voltage is charged to the pixel connected to the first gate line may be a first time , A time when the data voltage is charged to the pixel connected to the Kth gate line may be a second time longer than the first time when K (K is N / 2) th gate signal among the gate signals is activated The time when the data voltage is charged to the pixel connected to the N-th gate line when the N-th gate signal is activated among the gate signals, It can be a long third time.

In an embodiment of the present invention, the time difference between the second time and the first time may be equal to the time difference between the third time and the second time.

In one embodiment of the present invention, the display panel driving apparatus may further include a timing control unit. The timing controller may output a first clock signal for controlling the timing of the gate signal to the gate driver and a second clock signal for controlling the timing of the data signal to the data driver. The timing controller may include a memory for storing the image data.

In one embodiment of the present invention, the gate driver may be disposed on the display panel.

In one embodiment of the present invention, the gate driver may be an amorphous silicon gate (ASG).

According to another aspect of the present invention, there is provided a display panel driving method for increasing the activation time of a data signal according to an increase in RC of a data line included in a display panel, And outputting the gate signal to the gate line of the display panel by increasing an activation time of the gate signal in accordance with an increase in RC of the data line.

According to an embodiment of the present invention, the step of increasing the activation time of the data signal according to the increase of the RC of the data line may include gradually increasing the activation time of the data signal according to an increase in RC of the data line, . ≪ / RTI >

According to an embodiment of the present invention, the step of increasing the activation time of the gate signal according to the increase of the RC of the data line may include gradually increasing the activation time of the gate signal according to an increase in RC of the data line, . ≪ / RTI >

In one embodiment of the present invention, the display panel driving method may further include a step of increasing the horizontal blank time according to an increase in RC of the data line.

In one embodiment of the present invention, the step of increasing the horizontal blanking time in accordance with the increase of the RC of the data line includes a step of gradually increasing the horizontal blanking time in accordance with an increase in RC of the data line . ≪ / RTI >

According to an aspect of the present invention, a display device includes a display panel and a display panel drive device. The display panel displays an image and includes a gate line and a data line. Wherein the display panel driving device generates a data signal based on the image data and increases the activation time of the data signal according to an increase in RC of the data line included in the display panel, And a gate driver for outputting the gate signal to the gate line of the display panel by increasing an activation time of the gate signal in accordance with an increase in RC of the data line.

According to the display panel driving apparatus, the display panel driving method using the same, and the display device including the same, the activation time of the gate signals increases and the activation time of the data signals increases as the RC of the data line increases. Therefore, even if the RC delay of the data line increases with an increase in the distance between the data driver and the data line, the data charging rate of the pixel can be improved. Therefore, the display quality of the display device can be improved.

1 is a block diagram showing a display device according to an embodiment of the present invention.
2 is a plan view showing the display panel of Fig.
3 is a circuit diagram showing the pixel of Fig.
FIG. 4 is a graph showing the horizontal time according to the distance between the data driver and the data lines of FIG. 1;
5A is a waveform diagram showing the first gate signal and the data signal of FIG.
5B is a waveform diagram showing a K-th gate signal and a data signal of FIG.
5C is a waveform diagram showing the N-th gate signal and the data signal of FIG.
6 is a timing chart showing one frame of the video data of Fig.
7 is a flowchart showing a method of driving a display panel using the display panel driving apparatus of FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a display device according to an embodiment of the present invention.

Referring to FIG. 1, the display device 100 includes a display panel 110, a gate driver 130, a data driver 140, and a timing controller 150.

The display panel 110 receives the data signal DS based on the image data DATA provided from the timing controller 150 and displays the image.

The display panel 110 includes a display area DA and a peripheral area PA. The display area DA includes gate lines GL1, GL2, ..., GLK, ..., GL (N-1), GLN, data lines DL and pixels 120. Here, 'N' may be a natural number and 'K' may be N / 2. For example, 'N' may be 2160 and 'K' may be 1080. The gate lines GL1, GL2, ..., GLK, ..., GL (N-1), GLN extend in the first direction D1 and extend in the second direction perpendicular to the first direction D1. (D2). The data lines DL extend in the second direction D2 and are arranged in the first direction D1. The first direction D1 may be parallel to the long side of the display panel 110 and the second direction D2 may be parallel to the short side of the display panel 110. [ The peripheral region PA includes the gate driver 130.

2 is a plan view showing the display panel 110 of FIG.

Referring to FIGS. 1 and 2, the display panel 110 includes the pixels 120. The pixel 120 may include a red pixel R, a green pixel G, and a blue pixel B, for example. The red pixel R, the green pixel G and the blue pixel B may be sequentially and repeatedly arranged in the first direction D1. Each of the red pixel R, the green pixel G and the blue pixel B may be arranged in the second direction D2. The length of the pixel 120 in the first direction D1 may be longer than the length of the pixel 120 in the second direction D2.

3 is a circuit diagram showing the pixel 120 of FIG.

1 to 3, the pixels 120 are connected to each of the gate lines GL1, GL2, ..., GLK, ..., GL (N-1), GLN, (DL). For example, the pixel 120 includes a thin film transistor 121 electrically connected to the gate line GL and the data lines DL, a liquid crystal capacitor 123 connected to the thin film transistor 121, and a storage capacitor 125). Accordingly, the display panel 110 may be a liquid crystal display panel. The gate line GL may be any one of the gate lines GL1, GL2, ..., GLK, ..., GL (N-1), GLN.

Referring to FIG. 1 again, the gate driver 130, the data driver 140, and the timing controller 150 may be defined as a display panel driver for driving the display panel 110.

The gate driver 130 generates the gate signals GS1, GS2, ..., GSK, ... in response to the vertical start signal STV and the first clock signal CLK1 provided from the timing controller 150. [ ..., GSN ... GS (N-1), GSN) to the gate lines GL1, GL2, ..., GLK, ..., GL (N-1), GLN. The gate driver 130 may be disposed in the peripheral area PA of the display panel 110. For example, the gate driver 130 may be an amorphous silicon gate (ASG).

The data driver 140 receives the image data DATA from the timing controller 150 and generates the data signal DS based on the image data DATA. And outputs the data signal DS to the data line DL in response to the horizontal start signal STH and the second clock signal CLK2 provided from the data line DL.

The timing controller 150 receives the video data DATA and the control signal CON from the outside. The control signal CON may include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal CLK. The timing controller 150 generates the horizontal start signal STH using the horizontal synchronizing signal Hsync and outputs the horizontal start signal STH to the data driver 140. [ The timing controller 150 generates the vertical start signal STV using the vertical synchronization signal Vsync and then outputs the vertical start signal STV to the gate driver 130. [ The timing controller 150 generates the first clock signal CLK1 and the second clock signal CLK2 using the clock signal CLK and then outputs the first clock signal CLK1 To the gate driver 130 and outputs the second clock signal CLK2 to the data driver 140. [ The timing controller 150 may include a memory 160. The memory 160 stores the image data (DATA). The memory 160 may store and output the image data (DATA) on a frame-by-frame basis. Thus, the memory 160 may be referred to as a frame memory.

The load of the data line DL increases as the distance between the data line DL and the data driver 140 increases. Therefore, the RC of the data line DL increases as the distance between the data line DL and the data driver 140 increases. Therefore, the RC delay of the data signal DS may increase with an increase in the distance between the data line DL and the data driver 140.

The gate driver 130 may control the gate voltages of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN according to the RC increase of the data line DL. Increase the activation time. ., GS (N-1),..., GS (N-1), and the gate signals GS1, GSN) is gradually increased. The second gate signal GS2 is greater than the activation time of the first gate signal GS1 among the gate signals GS1, GS2, ..., GSK, ..., GS (N-1) The activation time of the Kth gate signal GSK is longer than the activation time of the second gate signal GS and the activation time of the Kth gate signal GSK is longer than the activation time of the Kth gate signal GSK, Th gate signal GS (N-1) is longer and the activation time of the N-th gate signal GSN is longer than the activation time of the (N-1) th gate signal GS (N-1) . The gate driver 130 may control the gate voltages of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN according to the RC increase of the data line DL. The activation time can be linearly increased. The gate driver 130 supplies the activation time of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN to the timing controller 150, 1 clock signal CLK1.

The data driver 140 increases the activation time of the data signal DS according to an increase in RC of the data line DL. Specifically, the data driver 140 gradually increases the activation time of the data signal DS according to an increase in RC of the data line DL. Therefore, when the first gate signal GS1 is activated, the second gate signal GS2 may be activated longer than the activation time of the data signal DS applied to the data line DL corresponding to the first gate line GL1 When the activation time of the data signal DS applied to the data line DL corresponding to the second gate line GL2 is long and the activation time of the second gate signal GS2 is long, (DL) corresponding to the K-th gate line (GLK) when the K-th gate signal (GSK) is activated than the activation time of the data signal (DS) applied to the data line The activation time of the data signal DS applied to the data line DL corresponding to the K-th gate line GLK is long and the activation time of the data signal DS applied to the data line DL corresponding to the K- Signal (DS 1) th gate line GL (N-1) when the (N-1) th gate signal GS (N-1) (N-1) th gate line GL (N-1) when the activation time of the data signal DS applied to the (N-1) th gate signal GS (DL) corresponding to the N-th gate line GLN when the N-th gate signal GSN is activated than the activation time of the data signal DS applied to the data line DL corresponding to the N-th gate line GLN, The activation time of the data signal DS applied thereto is long. The data driver 140 may linearly increase the activation time of the data signal DS according to an increase in RC of the data line DL. The data driver 140 may control the activation time of the data signals DS according to the second clock signal CLK2 provided from the timing controller 150. [

The gate driver 130 may control the gate voltages of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN according to the RC increase of the data line DL. The activation time is increased and the data driver 140 increases the activation time of the data signal DS according to the increase of the RC of the data line DL so that the data voltage is charged to the pixel 120 The horizontal time increases with an increase (RC) of the data line DL.

4 is a graph showing the horizontal time according to the distance between the data driver 140 and the data line DL in FIG.

Referring to FIGS. 1 and 4, the horizontal time increases as the distance between the data driver 140 and the data line DL increases. Therefore, the horizontal time increases as the RC of the data line DL increases. The horizontal time may gradually increase with an increase in RC of the data line DL. In addition, the horizontal time may linearly increase with an increase in RC of the data line DL. For example, the horizontal time when the first gate signal GS1 is applied to the first gate line GL1 may be about 1.7 μs, and the horizontal time of the Kth gate signal The horizontal time when the gate signal GSK is applied may be about 2.5 μs and the horizontal time when the N-th gate signal GSN is applied to the N-th gate line GLN may be about 3.3 μs. Therefore, when the first gate signal GS1 is applied to the first gate line GL1 and the horizontal time when the Kth gate signal GSK is applied to the Kth gate line GLK, The difference in the horizontal time is a difference between the horizontal time when the Nth gate signal GSN is applied to the Nth gate line GLN and the Kth gate signal GSK to the Kth gate line GLK And may be substantially the same as the difference of the horizontal time when it is applied.

5A is a waveform diagram showing the first gate signal GS1 and the data signal DS of FIG.

1, 4 and 5A, the horizontal time when the first gate signal GS1 is applied to the first gate line GL1 may be a first time T1. For example, the first time T1 may be about 1.7 microseconds.

5B is a waveform diagram showing the K-th gate signal GSK and the data signal DS of FIG.

1 and 4 to 5B, the horizontal time when the K-th gate signal GSK is applied to the K-th gate line GLK may be a second time T2. For example, the second time T2 may be about 2.5 microseconds.

The data driver 140 and the data line DL intersecting with the data driver 140 and the data line DL intersecting the data line DL intersect the data driver 140 and the first gate line GL1. DL) is long. Therefore, the data driver 140 and the K-th gate line GLK (not shown) may be connected to the data driver 140 and the data line DL between the data driver 140 and the data line DL crossing the first gate line GL1. (RC) between the points of the data lines DL that intersect with the data lines DL. Therefore, the activation time of the K-th gate signal GSK is longer than the activation time of the first gate signal GS1. In addition, the activation time of the data signal DS when the K-th gate signal GSK is activated is longer than the activation time of the data signal DS when the first gate signal GS1 is activated. Therefore, the horizontal time when the K-th gate signal GSK is applied to the K-th gate line GLK is the horizontal time when the first gate signal GS1 is applied to the first gate line GL1 Is longer than the horizontal time.

5C is a waveform diagram showing the N-th gate signal GSN and the data signal DS of FIG.

Referring to FIGS. 1 and 4 to 5C, the horizontal time when the N-th gate signal GSN is applied to the N-th gate line GLN may be a third time T3. For example, the third time T3 may be about 3.3 microseconds.

The data driver 140 and the data line DL intersecting with the data driver 140 and the Nth gate line GLN are connected to the data driver 140 and the data line DL intersecting with the Kth gate line GLK, DL) is long. Therefore, the data driving unit 140 and the N-th gate line GLN (N) are connected to the data line DL between the data driver 140 and the data line DL intersecting the K-th gate line GLK. (RC) between the points of the data lines DL that intersect with the data lines DL. Therefore, the activation time of the N-th gate signal GSN is longer than the activation time of the K-th gate signal GSK. In addition, the activation time of the data signal DS when the N-th gate signal GSN is activated is longer than the activation time of the data signal DS when the K-th gate signal GSK is activated. Therefore, the horizontal time when the N-th gate signal GSN is applied to the N-th gate line GLN is the horizontal time when the K-th gate signal GSK is applied to the K-th gate line GLK Is longer than the horizontal time.

The activation time of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN increases linearly with increase in RC of the data line DL And the activation time of the data signal DS linearly increases so that the time difference between the second time T2 and the first time T1 is shorter than the third time T3 and the second time T2 ) ≪ / RTI >

6 is a timing chart showing one frame of the video data (DATA) in Fig.

Referring to FIGS. 1 and 6, the frequency of the frame may be about 60 Hz, and the period of the frame may be about 16.67 ms. The timing controller 150 may store the image data DATA in the memory 160 and output the image data DATA to the data driver 140. [

The horizontal time increases as the distance between the data driver 140 and the data line DL increases. Therefore, the horizontal time increases as the RC of the data line DL increases. The horizontal time may gradually increase with an increase in RC of the data line DL. In addition, the horizontal time may linearly increase with an increase in RC of the data line DL. For example, the horizontal time when the first gate signal GS1 is applied to the first gate line GL1 may be about 1.7 μs, and the horizontal time of the Kth gate signal The horizontal time when the gate signal GSK is applied may be about 2.5 μs and the horizontal time when the N-th gate signal GSN is applied to the N-th gate line GLN may be about 3.3 μs.

In addition, the horizontal blank time increases as the distance between the data driver 140 and the data line DL increases. Accordingly, the horizontal blank time increases with an increase in RC of the data line DL. The horizontal blank time may gradually increase in accordance with an increase in RC of the data line DL. Also, the horizontal blank time may linearly increase with an increase in RC of the data line DL.

7 is a flowchart showing a method of driving a display panel using the display panel driving apparatus of FIG.

1 and 4 to 7, the activation time of the data signal DS is increased in accordance with an increase in RC of the data line DL, and the data signal DS is applied to the display panel 110 And outputs it to the data line DL (step S110). Specifically, the data driver 140 receives the image data DATA from the timing controller 150, generates the data signal DS based on the image data DATA, (DS) to the data line (DL) in response to the horizontal start signal (STH) and the second clock signal (CLK2) provided from the data driver (150).

The data driver 140 increases the activation time of the data signal DS according to an increase in RC of the data line DL. Specifically, the data driver 140 gradually increases the activation time of the data signal DS according to an increase in RC of the data line DL. Therefore, the activation time of the data signal DS applied to the data line DL corresponding to the first gate line GL1 when the first gate signal GS1 is activated is greater than the activation time of the data signal DS applied to the data line DL corresponding to the first gate line GL1. When the activation time of the data signal DS applied to the data line DL corresponding to the second gate line GL2 is long when the first gate signal GS2 is activated and when the second gate signal GS2 is activated, When the K-th gate signal GSK is activated than the activation time of the data signal DS applied to the data line DL corresponding to the gate line GL2, The activation time of the data signal DS applied to the data line DL is long and the data line DL corresponding to the Kth gate line GLK when the Kth gate signal GSK is activated, ) 1) th gate line GL (N-1) when the (N-1) th gate signal GS (N-1) is activated than the activation time of the applied data signal DS, (N-1) th gate signal GS (N-1) is activated when the activation time of the data signal DS applied to the data line DL corresponding to the When the N-th gate signal GSN is activated than the activation time of the data signal DS applied to the data line DL corresponding to the gate line GL (N-1) The activation time of the data signal DS applied to the data line DL corresponding to the data lines GLN is long. The data driver 140 may linearly increase the activation time of the data signal DS according to an increase in RC of the data line DL. The data driver 140 may control the activation time of the data signals DS according to the second clock signal CLK2 provided from the timing controller 150. [

The activation time of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN is increased in accordance with an increase in RC of the data line DL, (GL1, GL2, ..., GLK, ..., GSN) of the display panel 110. The gate lines GL1, GL2, ..., GSK, ..., GS (N-1) ..., GL (N-1), GLN. In detail, the gate driver 130 generates the gate signals GS1, GS2, ... in response to the vertical start signal STV and the first clock signal CLK1 provided from the timing controller 150. [ ..., GSN, ..., GS (N-1), GSN), and generates the gate signals GS1, GS2, To the gate lines GL1, GL2, ..., GLK, ..., GL (N-1), GLN.

The gate driver 130 may control the gate voltages of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN according to the RC increase of the data line DL. Increase the activation time. ., GS (N-1),..., GS (N-1), and the gate signals GS1, GSN) is gradually increased. Accordingly, the second gate signal (GS1, GS2, ..., GSN, GS2, ..., GSN) GS2 is longer than the activation time of the second gate signal GS and the activation time of the Kth gate signal GSK is longer than the activation time of the second gate signal GS, 1) -th gate signal GS (N-1) is longer than the activation time of the (N-1) -th gate signal GS (N-1) Activation time is long. The gate driver 130 may control the gate voltages of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN according to the RC increase of the data line DL. The activation time can be linearly increased. The gate driver 130 supplies the activation time of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN to the timing controller 150, 1 clock signal CLK1.

The gate driver 130 may control the gate voltages of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN according to the RC increase of the data line DL. The activation time is increased and the data driver 140 increases the activation time of the data signal DS according to the increase of the RC of the data line DL so that the data voltage is charged to the pixel 120 The horizontal time increases with an increase (RC) of the data line DL. The horizontal time may gradually increase with an increase in RC of the data line DL. In addition, the horizontal time may linearly increase with an increase in RC of the data line DL.

In addition, the horizontal blank time may increase with an increase in RC of the data line DL. The horizontal blank time may gradually increase with an increase in RC of the data line DL and the horizontal blank time may linearly increase with an increase in RC of the data line DL .

In this embodiment, the gate driver 130 is disposed on the display panel 110, but the present invention is not limited thereto. For example, the gate driver 130 may be disposed outside the display panel 110.

..., GS (N-1), GSN (N-1), ..., GSN) according to the RC increase of the data line DL, And to increase the activation time of the data signal DS according to an increase in the RC of the data line DL, the data driver 140 may increase the activation time of the data signal DS, If the signal CON is provided to the timing controller 150, the timing controller 150 may not include the memory 160.

According to the present embodiment, the activation of the gate signals GS1, GS2, ..., GSK, ..., GS (N-1), GSN in accordance with the RC increase of the data line DL, The time increases and the activation time of the data signal DS increases. Therefore, even if the RC delay of the data line DL increases as the distance between the data driver 140 and the data line DL increases, the data charging rate of the pixel 120 can be improved . Therefore, the display quality of the display device 100 can be improved.

The present invention can be applied to all electronic apparatuses having a display device. For example, the present invention may be applied to a variety of portable devices such as televisions, computer monitors, notebooks, digital cameras, cell phones, smart phones, tablet PCs, smart pads, PDAs, , A camcorder, a portable game machine, and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. You will understand.

100: display device 110: display panel
120: pixel 130: gate driver
140: Data driver 150: Timing controller
160: Memory

Claims (20)

A data driver for generating a data signal based on the image data and outputting the data signal to the data line by increasing an activation time of the data signal according to an increase in RC of the data line included in the display panel; And
And a gate driver for increasing the activation time of the gate signal according to an increase in RC of the data line and outputting the gate signal to the gate line of the display panel. 2. The display panel drive apparatus according to claim 1, wherein the data driver gradually increases the activation time of the data signal according to an increase in RC of the data line. 3. The display panel drive apparatus according to claim 2, wherein the data driver linearly increases an activation time of the data signal according to an increase in RC of the data line. 2. The display panel drive device according to claim 1, wherein the gate driver gradually increases the activation time of the gate signal according to an increase (RC) of the data line. 5. The display panel drive apparatus according to claim 4, wherein the gate driver linearly increases the activation time of the gate signal according to an increase (RC) of the data line. 2. The display panel drive apparatus according to claim 1, wherein the horizontal blank time is increased according to an increase in RC of the data line. 7. The display panel drive apparatus according to claim 6, wherein the horizontal blank time gradually increases in accordance with an increase in RC of the data line. The display panel drive apparatus according to claim 7, wherein the horizontal blank time increases linearly with an increase in RC of the data line. The method of claim 1, wherein the gate lines include first to Nth gate lines (N is a natural number of 4 or more)
Wherein the gate signals include first through N-th gate signals respectively output to the first through N-th gate lines,
The time when the data voltage is charged to the pixel connected to the first gate line is the first time when the first gate signal is activated among the gate signals,
A time when the data voltage is charged to the pixel connected to the Kth gate line is a second time longer than the first time when K (K is N / 2) th gate signal of the gate signals is activated,
Wherein the time when the data voltage is charged to the pixel connected to the Nth gate line when the Nth gate signal is activated among the gate signals is a third time longer than the second time. The display panel drive apparatus according to claim 9, wherein a time difference between the second time and the first time is equal to a time difference between the third time and the second time. The method according to claim 1,
A memory for outputting a first clock signal for controlling the timing of the gate signal to the gate driver, a second clock signal for controlling the timing of the data signal to the data driver, and storing the image data And a timing controller for driving the display panel. The display panel drive device according to claim 1, wherein the gate driver is disposed on the display panel. 13. The display panel drive apparatus according to claim 12, wherein the gate driver is an amorphous silicon gate (ASG). Increasing the activation time of the data signal in accordance with an increase (RC) of the data line included in the display panel and outputting the data signal to the data line; And
And increasing the activation time of the gate signal according to an increase in RC of the data line to output the gate signal to the gate line of the display panel. 15. The method of claim 14, wherein increasing the activation time of the data signal in accordance with an increase in the RC of the data line gradually increases the activation time of the data signal in accordance with an increase in RC of the data line The method comprising the steps of: 15. The method of claim 14, wherein increasing the activation time of the gate signal according to an increase in RC of the data line gradually increases the activation time of the gate signal according to an increase in RC of the data line The method comprising the steps of: 15. The method of claim 14,
Further comprising increasing the horizontal blank time according to an increase in RC of the data line. 18. The method of claim 17, wherein increasing the horizontal blank time in response to an increase in the RC of the data line comprises incrementally increasing the horizontal blank time in response to an increase in RC of the data line And the display panel driving method. A display panel that displays an image and includes a gate line and a data line; And
A data driver for generating a data signal based on the image data and outputting the data signal to the data line by increasing an activation time of the data signal according to an increase in RC of the data line included in the display panel, And a gate driver for increasing an activation time of the gate signal according to an increase in RC of the data line and outputting the gate signal to the gate line of the display panel. 20. The display device according to claim 19, wherein the display panel further comprises a pixel defined by the gate line and the data line,
Wherein the gate line extends in a first direction and the data line extends in a second direction perpendicular to the first direction,
And the length of the pixel in the first direction is longer than the length in the second direction.
KR1020160018376A 2016-02-17 2016-02-17 Display panel driving apparatus, method of driving display panel using the same and display apparatus having the same KR20170097255A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10923061B2 (en) 2018-07-25 2021-02-16 Samsung Display Co., Ltd. Gate driving circuit with reduced power consumption and display device including the same
US10997885B2 (en) 2018-02-20 2021-05-04 Samsung Display Co., Ltd. Display device and method of driving the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10997885B2 (en) 2018-02-20 2021-05-04 Samsung Display Co., Ltd. Display device and method of driving the same
US10923061B2 (en) 2018-07-25 2021-02-16 Samsung Display Co., Ltd. Gate driving circuit with reduced power consumption and display device including the same

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