KR102633163B1 - Display apparatus and method of driving the same - Google Patents

Abstract

A display device includes first and second data lines, a display panel that displays an image, and outputs data voltages having a first polarity to the first data line in synchronization with a first clock signal in a k-th horizontal section. , and a data driver that outputs data voltages having a second polarity different from the first polarity to the second data line in synchronization with a second clock signal different from the first clock signal in the k-th horizontal section. The second polarity may be negative, and the pulse of the second clock signal corresponding to the k-th horizontal section may be slower than the pulse of the first clock signal corresponding to the k-th horizontal section.

Description

Display device and driving method thereof {DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME}

The present invention relates to a display device, and more specifically, to a display device capable of improving display quality and a method of driving the same.

Generally, a liquid crystal display device includes a first substrate including a pixel electrode, a second substrate including a common electrode, and a liquid crystal layer interposed between the substrates. A voltage is applied to the two electrodes to generate an electric field in the liquid crystal layer, and the intensity of this electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

A liquid crystal display device includes a display panel and a panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines. The panel driver includes a gate driver that provides a gate signal to the gate lines and a data driver that provides a data voltage to the data lines.

The gate driver includes a plurality of switching elements. The switching elements are controlled by a clock signal or the like to generate the gate signal. Delay occurs in the gate signal due to RC delay depending on the relative position within the display panel.

Accordingly, the technical problem of the present invention was conceived from this point, and the purpose of the present invention is to provide a display device that improves display quality.

Another object of the present invention is to provide a method of driving the display device.

A display device according to embodiments for realizing the object of the present invention described above includes a display panel including first and second data lines and displaying an image, and a display panel that is synchronized with a first clock signal in a k-th horizontal section. Data voltages having a first polarity are output to a first data line, and a second voltage different from the first polarity is output to the second data line in synchronization with a second clock signal different from the first clock signal in the k-th horizontal section. It includes a data driver that outputs data voltages having polarity.

In one embodiment of the present invention, the second polarity is negative, and the pulse of the second clock signal corresponding to the k-th horizontal section is greater than the pulse of the first clock signal corresponding to the k-th horizontal section. It can be slow.

In one embodiment of the present invention, the data driver further includes a timing controller that generates a setting signal that controls the timing of the first clock signal and the timing of the second clock signal, and the data driver generates the setting signal based on the setting signal. First and second clock signals may be generated.

In one embodiment of the present invention, the timing controller determines the timing of the pulse of the first clock signal corresponding to the k-th horizontal section and the k-th pulse based on input image data corresponding to the k-1th horizontal section. The timing of the pulse of the second clock signal corresponding to the horizontal section can be determined.

In one embodiment of the present invention, the k-1th horizontal section may be a previous horizontal section of the kth horizontal section.

In one embodiment of the present invention, the second polarity is negative, and the timing controller corresponds to the k-th horizontal section according to input image data corresponding to the k-1 horizontal section and the second data line. The timing of the pulses of the second clock signal can be adjusted.

In one embodiment of the present invention, the timing controller determines that the higher the gray level of the input image data corresponding to the k-1th horizontal section and the second data line, the higher the gray level of the input image data corresponding to the k-1th horizontal section and the second data line. The delay time of the signal pulse can be increased.

In one embodiment of the present invention, the timing controller may fix the timing of the first clock signal.

In one embodiment of the present invention, the timing controller stores timings of pulses of the first and second clock signals corresponding to the k-th horizontal section according to input image data corresponding to the k-1th horizontal section. You can refer to the lookup table.

In one embodiment of the present invention, the setting signal is 6 bits, and the timing controller can set 64 different timings for each of the first and second clock signals.

In one embodiment of the present invention, the second data line may be an even-numbered data line, and the first data line may be an odd-numbered data line.

In one embodiment of the present invention, the display panel further includes a gate driver, wherein the display panel includes a k-th gate line, a first pixel connected to the k-th gate line and the first data line, and a k-th gate line and It may further include a second pixel connected to the second data line, and the gate driver may output a k-th gate signal to the k-th gate line in the k-th horizontal section.

A method of driving a display device according to embodiments for realizing another object of the present invention described above includes outputting data voltages having a first polarity to a first data line in synchronization with a first clock signal in the k-th horizontal section. , and outputting data voltages having a second polarity different from the first polarity to a second data line in synchronization with a second clock signal different from the first clock signal in the k-th horizontal section.

In one embodiment of the present invention, the second polarity is negative, and the pulse of the second clock signal corresponding to the k-th horizontal section is greater than the pulse of the first clock signal corresponding to the k-th horizontal section. It can be slow.

In one embodiment of the present invention, generating a setting signal for controlling the timing of the first clock signal and the timing of the second clock signal, and generating the first and second clock signals based on the setting signal. A generating step may be further included.

In one embodiment of the present invention, the step of generating the setup signal is based on the input image data corresponding to the k-1th horizontal section before the kth horizontal section, and the It may include determining the timing of the pulse of the first clock signal and the timing of the pulse of the second clock signal corresponding to the k-th horizontal section.

In one embodiment of the present invention, the second polarity is negative, and determining the timing of the pulse of the second clock signal corresponding to the k-th horizontal section includes the k-1 horizontal section and the It may include adjusting the timing of pulses of the second clock signal corresponding to the k-th horizontal section according to input image data corresponding to the second data line.

In one embodiment of the present invention, adjusting the timing of the pulse of the second clock signal corresponding to the k-th horizontal section includes input image data corresponding to the k-1th horizontal section and the second data line. As the gray level of , the step of increasing the delay time of the pulse of the second clock signal corresponding to the k-th horizontal section may be included.

In one embodiment of the present invention, determining the timing of the pulse of the first clock signal corresponding to the k-th horizontal section may include fixing the timing of the first clock signal.

In one embodiment of the present invention, determining timings of pulses of the first and second clock signals corresponding to the k-th horizontal section may include determining the timing of the pulses of the first and second clock signals according to the input image data corresponding to the k-1 horizontal section. It may include referencing a lookup table that stores timings of pulses of the first and second clock signals corresponding to the k-th horizontal section.

According to the display device and its driving method according to embodiments of the present invention, two different clock signals each have independent timing on a data line to which positive data voltages are applied and a data line to which negative polarity data voltages are applied. By matching, it is possible to improve the problem of a timing difference occurring between negative data voltages and the corresponding gate signal due to the delay of the gate signal. Accordingly, the display quality of the display device can be improved.

1 is a block diagram showing a display device according to embodiments of the present invention.
Figure 2 is a block diagram showing a display panel included in a display device according to embodiments of the present invention.
FIG. 3 is a diagram illustrating signals output from a timing controller included in a display device according to embodiments of the present invention.
FIG. 4 is a diagram showing clock signals generated in a data driver included in a display device according to embodiments of the present invention.
FIG. 5 is a diagram illustrating an example of signals generated in a data driver and a gate driver included in a display device according to embodiments of the present invention.
FIG. 6 is a diagram illustrating another example of signals generated in a data driver and a gate driver included in a display device according to embodiments of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the attached drawings.

1 is a block diagram showing a display device according to embodiments of the present invention.

Referring to FIG. 1, the display device includes a display panel 100 and a driver. The driver includes a timing controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

The display panel 100 includes a display portion that displays an image and a peripheral portion disposed adjacent to the display portion.

The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels electrically connected to each of the gate lines GL and the data lines DL. do. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 that intersects the first direction D1.

Each of the pixels may include a switching element (not shown), a liquid crystal capacitor (not shown) and a storage capacitor (not shown) electrically connected to the switching element. The pixels may be arranged in a matrix form.

The display panel 100 will be described in detail later with reference to FIG. 2 .

The timing controller 200 receives input image data (RGB) and input control signal (CONT) from an external device (not shown). The input image data (RGB) may include red image data (R), green image data (G), and blue image data (B). The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

The timing controller 200 generates a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3) and data based on the input image data (RGB) and the input control signal (CONT). Generates a signal (DAT).

The timing controller 200 generates the first control signal CONT1 to control the operation of the gate driver 300 based on the input control signal CONT. The timing controller 200 outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

The timing controller 200 generates the second control signal CONT2 to control the operation of the data driver 500 based on the input control signal CONT. The timing controller 200 outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal. The second control signal CONT2 may further include a setting signal.

The second control signal CONT2 will be described in detail later with reference to FIGS. 3 and 4.

The timing controller 200 generates the data signal (DAT) based on the input image data (RGB). The timing controller 200 outputs the data signal DAT to the data driver 500. The data signal DAT may be image data substantially the same as the input image data RGB, or may be corrected image data generated by correcting the input image data RGB. For example, the timing controller 200 performs image quality correction, spot correction, color characteristic compensation (Adaptive Color Correction, hereinafter referred to as ACC), and/or active capacitance compensation for the input image data (RGB). , hereinafter referred to as DCC) can be selectively performed to generate the data signal (DAT).

The timing controller 200 generates the third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT. The timing controller 200 outputs the third control signal CONT3 to the gamma reference voltage generator 400.

The gate driver 300 generates gate signals for driving the gate lines GL in response to the first control signal CONT1 received from the timing controller 200. The gate driver 300 sequentially outputs the gate signals to the gate lines GL.

The gate driver 300 may be mounted directly on the display panel 100 or may be connected to the display panel 100 in the form of a tape carrier package (TCP). Meanwhile, the gate driver 300 may be integrated into the peripheral portion of the display panel 100.

The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the timing controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage (VGREF) to the data driver 500. The gamma reference voltage (VGREF) has a value corresponding to each data signal (DAT).

In one embodiment of the present invention, the gamma reference voltage generator 400 may be disposed within the timing controller 200 or within the data driver 500.

The data driver 500 receives the second control signal (CONT2) and the data signal (DAT) from the timing controller 200, and generates the gamma reference voltage (VGREF) from the gamma reference voltage generator 400. receives input. The data driver 500 converts the data signal DAT into analog data voltages using the gamma reference voltage VGREF. The data driver 500 outputs the data voltages to the data lines DL.

The data driver 500 may be directly mounted on the display panel 100 or may be connected to the display panel 100 in the form of a tape carrier package (TCP). Meanwhile, the data driver 500 may be integrated into the peripheral portion of the display panel 100.

The data driver 500 will be described in detail later with reference to FIGS. 4 to 6.

Figure 2 is a block diagram showing a display panel included in a display device according to embodiments of the present invention.

Referring to FIGS. 1 and 2, the display panel 100 includes first to nth gate lines (GL1 to GLk-1, GLk to GLn) and first to mth data lines (DL1, DL2, DL3, DL4 ~ DLm). Each of the first to nth gate lines GL1 to GLn corresponds to each of the first to nth horizontal sections.

Each of the pixels (not shown) is electrically connected to one of the first to nth gate lines (GL1 to GLn) and one of the first to mth data lines (DL1 to DLm).

During the first to nth horizontal sections of the first frame, positive polarity data voltages may be output to odd-numbered data lines, and negative polarity data voltages may be output to even-numbered data lines. During the first to nth horizontal sections of the second frame after the first frame, negative polarity data voltages may be output to the odd-numbered data lines, and positive polarity data voltages may be output to the even-numbered data lines. there is.

For example, positive data voltages are output to the first and third data lines DL1 and DL3 during the first to nth horizontal sections of the first frame, and the second and fourth data lines Negative data voltages may be output to the fields DL2 and DL4. During the first to nth horizontal sections of the second frame, negative data voltages are output to the first and third data lines DL1 and DL3, and the second and fourth data lines DL2 , DL4), data voltages of positive polarity may be output.

In contrast, positive data voltages are output to the first and second data lines DL1 and DL2 during the first to nth horizontal sections of the first frame, and the third and fourth data lines Negative data voltages may be output to (DL3, DL4). During the first to nth horizontal sections of the second frame, negative data voltages are output to the first and second data lines DL1 and DL2, and the third and fourth data lines DL3 , DL4), data voltages of positive polarity can be output.

FIG. 3 is a diagram illustrating signals output from a timing controller included in a display device according to embodiments of the present invention. FIG. 4 is a diagram showing clock signals generated in a data driver included in a display device according to embodiments of the present invention.

1 to 4, the timing controller 200 generates the second control signal CONT2 that controls the operation of the data driver 500 and outputs it to the data driver 500.

The second control signal (CONT2) sends a horizontal section start signal (SOL) and a setting signal (CON) corresponding to each of the first to nth horizontal sections (1H to (k-1)H, kH to nH). It can be included.

The setting signal CON controls the timing of the clock signal in the data driver 500. The setting signal CON may independently control the timing of pulses of the clock signal corresponding to each of the first to nth horizontal sections 1H to nH. Specifically, the setting signal (CON) can control the rising edge timing of the pulse of the clock signal. The part of the setting signal (CON) that controls the timing of the rising edge of the pulse of the clock signal may be composed of 6 bits. That is, the setting signal (CON) can adjust the rising edge timing of the pulse of the clock signal to 64 different types.

The timing controller 200 outputs the data signal DAT to the data driver 500 in response to each of the first to nth horizontal sections 1H to nH.

The data driver 500 has a horizontal blank section (HBP) after receiving the data signal (DAT) corresponding to each of the first to nth horizontal sections (1H to nH). The data driver 500 outputs a clock signal corresponding to the horizontal blank section (HBP). Specifically, the data driver 500 outputs the clock signal corresponding to the horizontal section during the horizontal blank section (HBP) based on the setting signal (CON) received in the horizontal section.

The data driver 500 receives a setting signal (CON) corresponding to the k-th horizontal section (kH) in the k-th horizontal section (kH). The setting signal CON corresponding to the k-th horizontal section (kH) includes information about the timing of pulses of the clock signal corresponding to the k-th horizontal section (kH). The data driver 500 generates a pulse of a clock signal corresponding to the k-th horizontal section (kH) in the horizontal blank section (HBP) of the k-th horizontal section (kH) based on the setting signal (CON). .

The timing controller 200 may generate first and second setting signals. The first setting signal may set the timing of the pulse of the clock signal to a first timing, and the second setting signal may set the timing of the pulse of the clock signal to a second timing different from the first timing.

The data driver 500 generates a clock signal based on the first setting signal for data lines outputting data voltages of the first polarity, and outputs data voltages of a second polarity different from the first polarity. For data lines, a clock signal may be generated based on the second setting signal. As a result, the timing of the clock signal corresponding to the data lines outputting data voltages of the first polarity may be different from the timing of the clock signal corresponding to the data lines outputting data voltages of the second polarity. . For example, the first polarity is positive polarity, the second polarity is negative polarity, and the timing of the clock signal corresponding to the data lines outputting data voltages of the second polarity is of the first polarity. The timing of the clock signal corresponding to the data lines outputting data voltages may be slower.

During the first to nth horizontal sections of the first frame, positive polarity data voltages are output to the first and third data lines DL1 and DL3, and the second and fourth data lines DL2, Negative data voltages may be output to DL4). During the first to nth horizontal sections of the second frame, negative data voltages are output to the first and third data lines DL1 and DL3, and the second and fourth data lines DL2 , DL4), data voltages of positive polarity can be output.

In this case, in the first frame, the data driver 500 generates the first signal for the first and third data lines DL1 and DL3 based on the first set signal in the kth horizontal section (kH). A first clock signal CLK1 having a delay time TL1 may be generated. The data driver 500 sets a delay time different from the first delay time TL1 for the second and fourth data lines DL2 and DL4 based on the second set signal in the kth horizontal section kH. A second clock signal CLK2 having a second delay time TL2 may be generated. The first and second delay times TL1 and TL2 are times when the pulse of each clock signal is delayed from the start of the horizontal blank period HBP. The second delay time TL2 may be longer than the first delay time TL1 by the time difference TD. That is, the second clock signal CLK2 may be slower than the first clock signal CLK1 by the time difference TD.

In this case, in the second frame, the data driver 500 operates on the first and third data lines DL1 and DL3 based on the second set signal in the kth horizontal section (kH). The second clock signal (CLK2) having a delay time (TL2) of 2 may be generated. The data driver 500 has the first delay time TL1 based on the first setting signal in the kth horizontal section (kH) for the second and fourth data lines DL2 and DL4. The first clock signal CLK1 may be generated. The second delay time TL2 may be longer than the first delay time TL1 by the time difference TD. That is, the second clock signal CLK2 may be slower than the first clock signal CLK1 by the time difference TD.

FIG. 5 is a diagram illustrating an example of signals generated in a data driver and a gate driver included in a display device according to embodiments of the present invention.

Referring to Figures 1 to 5, the gate driver 300 outputs the k-1th gate signal (GSk-1) in response to the k-1th horizontal section ((k-1)H). Delay may occur in the k-1th gate signal (GSk-1).

The data driver 500 outputs a data voltage synchronized to the pulse of the clock signal corresponding to the horizontal section in each horizontal section. That is, the rising edge time of the data voltage output in each horizontal section is substantially the same as the rising edge time of the pulse of the clock signal corresponding to the corresponding horizontal section.

For data lines on which positive polarity data voltages (VDL+) are output, the data driver 500 generates the first clock signal (CLK1). The rising edge of the pulse of the first clock signal CLK1 corresponding to the k-th horizontal section (kH) is after the gate of the pixel corresponding to the k-1 horizontal section is closed (T1).

For data lines on which negative data voltages (VDL-) are output, the data driver 500 generates the second clock signal (CLK2). The rising edge of the pulse of the second clock signal CLK2 corresponding to the k-th horizontal section (kH) is after the gate of the pixel corresponding to the k-1 horizontal section is closed (T2).

For example, in the first frame, positive data voltages are output to odd-numbered data lines, negative data voltages are output to even-numbered data lines, and negative polarity data voltages are output to odd-numbered data lines in the second frame. In the case of the column inversion driving method in which positive polarity data voltages are output to the even-numbered data lines, the first clock signal CLK1 is generated for the odd-numbered data lines in the first frame and the even-numbered data lines are output. The second clock signal CLK2 is generated for the data lines, and in the second frame, the second clock signal CLK2 is generated for the odd-numbered data lines, and the second clock signal CLK2 is generated for the even-numbered data lines. 1 A clock signal (CLK1) can be generated.

FIG. 6 is a diagram illustrating another example of signals generated in a data driver and a gate driver included in a display device according to embodiments of the present invention. Descriptions overlapping with FIG. 5 are omitted.

Referring to FIGS. 1 to 6, the timing controller 200 generates a signal corresponding to the kth horizontal section (kH) based on input image data corresponding to the k-1th horizontal section ((k-1)H). A configuration signal (CON) can be generated.

The timing controller 200 may output a setting signal that prevents the timing of the clock signal from changing for data lines on which positive polarity data voltages are output.

The timing controller 200 operates the k-th horizontal section ((k-1)H) based on input image data corresponding to the k-1th horizontal section ((k-1)H) for data lines on which negative data voltages are output. A setting signal that changes the timing of the pulse of the clock signal corresponding to kH) can be output.

For example, the timing controller 200 determines the input image data corresponding to the k-1 horizontal section ((k-1) H) of all data lines, The timing of the pulse of the clock signal can be determined. In contrast, the timing controller 200 operates the kth horizontal section based on input image data corresponding to the k-1th horizontal section ((k-1)H) of all data lines through which negative data voltages are output. The timing of the pulse of the clock signal corresponding to the section (kH) can be determined. In contrast, the timing controller 200 outputs an input image with the highest gray level among input image data corresponding to the k-1th horizontal section ((k-1)H) of all data lines on which negative data voltages are output. Based on the data, the timing of the pulse of the clock signal corresponding to the k-th horizontal section (kH) can be determined.

The timing controller 200 controls the second clock signal corresponding to the k-th horizontal section (kH) as the gray level of the input image data corresponding to the k-1th horizontal section ((k-1)H) increases. The delay time of the (CLK) pulse can be increased. For example, if the voltage level corresponding to the input image data corresponding to the k-1th horizontal section ((k-1)H) is the first voltage level (VL1), the timing controller 200 The pulse of the second clock signal CLK2 corresponding to the horizontal section kH may be delayed by a first time difference TD1 compared to the pulse of the first clock signal CLK1. In this case, the rising edge point of the pulse of the second clock signal CLK2 corresponding to the k-th horizontal section (kH) is the gate of the pixel corresponding to the k-1th horizontal section ((k-1)H). This is after the closed point (T2_1). If the voltage level corresponding to the input image data corresponding to the k-1th horizontal section ((k-1)H) is the second voltage level (VL2), the timing controller 200 operates in the k-th horizontal section (kH ) may be delayed by a second time difference (TD2) compared to the pulse of the first clock signal (CLK1). In this case, the rising edge point of the pulse of the second clock signal CLK2 corresponding to the k-th horizontal section (kH) is the gate of the pixel corresponding to the k-1th horizontal section ((k-1)H). This is after the closed point (T2_2). When the first voltage level (VL1) is higher than the second voltage level (VL2), the first time difference (TD1) may be greater than the second time difference (TD2).

The timing controller 200 may refer to a lookup table. The lookup table stores information about the timings of pulses of the clock signal corresponding to the k-th horizontal section (kH) according to the input image data corresponding to the k-1th horizontal section ((k-1)H). You can.

The data driver 500 may generate a data voltage corresponding to the k-th horizontal section (kH) in synchronization with a pulse of a clock signal corresponding to the k-th horizontal section (kH).

The present invention can be applied to display devices and various devices and systems including the same. Therefore, the present invention is applicable to mobile phones, smart phones, PDAs, PMPs, digital cameras, camcorders, PCs, server computers, workstations, laptops, digital TVs, set-top boxes, music players, portable game consoles, navigation systems, smart cards, and printers. It can be usefully used in various electronic devices such as the like.

Although the description has been made with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will be able to.

100: display panel 200: timing controller
300: Gate driver 400: Gamma reference voltage generator
500: data driving unit

Claims (20)

a display panel including first and second data lines and displaying an image; and
Data voltages having a first polarity are output to the first data line in synchronization with a first clock signal in the k-th horizontal section, and output data voltages having a first polarity in the k-th horizontal section in synchronization with a second clock signal different from the first clock signal. A data driver outputting data voltages having a second polarity different from the first polarity to a second data line,
It further includes a timing controller that generates a setting signal that controls the timing of the first clock signal and the timing of the second clock signal,
The data driver generates the first and second clock signals based on the setting signal,
The timing controller determines the timing of the pulse of the first clock signal corresponding to the k-th horizontal section and the second clock corresponding to the k-th horizontal section based on the input image data corresponding to the k-1th horizontal section. A display device characterized by determining the timing of pulses of a signal. According to paragraph 1,
The second polarity is negative,
A display device, wherein a pulse of the second clock signal corresponding to the k-th horizontal section is slower than a pulse of the first clock signal corresponding to the k-th horizontal section. delete delete According to paragraph 1,
The k-1th horizontal section is a horizontal section preceding the kth horizontal section. According to paragraph 1,
The second polarity is negative,
The timing controller adjusts the timing of pulses of the second clock signal corresponding to the k-th horizontal section according to input image data corresponding to the k-1 horizontal section and the second data line. Device. According to clause 6,
The timing controller increases the delay time of the pulse of the second clock signal corresponding to the k-th horizontal section as the gray level of the input image data corresponding to the k-1 horizontal section and the second data line increases. A display device characterized in that. According to clause 6,
The timing controller is configured to fix the timing of the first clock signal. According to paragraph 1,
The timing controller refers to a lookup table that stores timings of pulses of the first and second clock signals corresponding to the k-th horizontal section according to input image data corresponding to the k-1th horizontal section. display device. According to paragraph 1,
The setup signal is 6 bits,
The timing controller is capable of setting 64 different timings for each of the first and second clock signals. According to paragraph 1,
The display device wherein the second data line is an even-numbered data line, and the first data line is an odd-numbered data line. According to paragraph 1,
Further comprising a gate driver,
The display panel further includes a k-th gate line, a first pixel connected to the k-th gate line and the first data line, and a second pixel connected to the k-th gate line and the second data line,
The display device wherein the gate driver outputs a k-th gate signal to the k-th gate line in the k-th horizontal section. outputting data voltages having a first polarity to a first data line in synchronization with a first clock signal in a k-th horizontal section; and
Outputting data voltages having a second polarity different from the first polarity to a second data line in synchronization with a second clock signal different from the first clock signal in the k-th horizontal section,
generating a setting signal that controls the timing of the first clock signal and the timing of the second clock signal; and
Further comprising generating the first and second clock signals based on the setting signal,
The step of generating the setting signal is
Based on the input image data corresponding to the k-1th horizontal section before the kth horizontal section, the timing of the pulse of the first clock signal corresponding to the kth horizontal section and the A method of driving a display device, comprising determining the timing of pulses of a second clock signal. According to clause 13,
The second polarity is negative,
A method of driving a display device, wherein the pulse of the second clock signal corresponding to the k-th horizontal section is slower than the pulse of the first clock signal corresponding to the k-th horizontal section. delete delete According to clause 13,
The second polarity is negative,
The step of determining the timing of the pulse of the second clock signal corresponding to the k-th horizontal section is
A display comprising the step of adjusting the timing of pulses of the second clock signal corresponding to the k-th horizontal section according to input image data corresponding to the k-1th horizontal section and the second data line. How the device operates. According to clause 17,
The step of adjusting the timing of the pulse of the second clock signal corresponding to the k-th horizontal section is
As the gray level of the input image data corresponding to the k-1th horizontal section and the second data line increases, increasing the delay time of the pulse of the second clock signal corresponding to the kth horizontal section. A method of driving a display device, characterized in that. According to clause 17,
The step of determining the timing of the pulse of the first clock signal corresponding to the k-th horizontal section is
A method of driving a display device, comprising fixing the timing of the first clock signal. According to clause 13,
Determining the timings of pulses of the first and second clock signals corresponding to the k-th horizontal section
Characterized by referencing a lookup table storing timings of pulses of the first and second clock signals corresponding to the k-th horizontal section according to the input image data corresponding to the k-1th horizontal section. A method of driving a display device.

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