JP2012003122A - Timing controller, display device using the same, and method for generating driver control signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress disturbance in an image caused by fluctuation in frequencies of a pixel clock.SOLUTION: A first OE generator 32 counts a pixel clock signal CLK a number of times prescribed by a predetermined setting parameter, and generates a first OE signal OE1. A pulse width measuring unit 34 measures the pulse width of the first OE signal OE1 using a system clock signal CLKosc with a fixed frequency and retains the pulse width data D1 indicating the pulse width. A second OE generator 36 regenerates a second OE signal OE2 having the pulse width indicated by the pulse width data D1, using the system clock signal CLK. When the pixel clock signal CLK has a first frequency, a timing controller 100 outputs the first OE signal OE1 and, when the pixel clock signal CLK has the second frequency, outputs the second OE signal OE2.

Description

  The present invention relates to a display panel driving technique, and more particularly to a timing controller (LCD controller) for supplying signals to a scan driver (gate driver) and a data driver (source driver).

  FIG. 1 is a block diagram showing a configuration of a general liquid crystal display (LCD) 300. The LCD 300 includes an LCD panel 302, a source driver 304, a gate driver 306, and a timing controller 200. The LCD panel 302 includes a plurality of data lines DL, a plurality of scanning lines SL arranged so as to be orthogonal to the data lines DL, and a plurality of TFTs arranged in a matrix at intersections of the data lines DL and the scanning lines SL ( Thin Film Transistor). The source driver 304 applies a voltage corresponding to the luminance to each data line DL. The gate driver 306 selects a plurality of scanning lines SL in order.

  The timing controller 200 receives image data to be displayed on the LCD panel 302 from the image source 308. Then, a driver control signal (timing pulse) corresponding to the panel resolution is generated and supplied to the source driver 304 and the gate driver 306 together with the image data. The timing controller 200 includes an input interface unit 202, a logic unit 204, a timing signal generator 206, and output interface units 208 and 210.

  The input interface unit 202 is connected to an image source 308 such as a graphics processor via a serial bus BUS1. The input interface unit 202 receives a signal from the image source 308 and receives differential RGB data RGBP / N of each pixel, a differential pixel clock signal CLKP / N, a data enable signal DE, a vertical synchronization signal Vsync, The horizontal synchronization signal Hsync is acquired and output to the logic unit 204. The logic unit 204 performs necessary signal processing on the image data RGBP / N and outputs the processed signal to the output interface unit 208. The output interface unit 208 is connected to the source driver 304 via an RSDS standard (Reduced Swing Differential Signaling) or LVDS standard (Low Voltage Differential Signaling) bus, and outputs image data.

The timing signal generator 206 receives the reference signal REF generated by the logic unit 204. The timing signal generator 206 generates, for example, the following driver control signal based on the reference signal REF.
・ Start pulse (STH)
・ Latch pulse (LOAD)
・ AC signal (POL)
・ Vertical shift direction input / output signal (STV)
・ Vertical transfer clock (CPV)
・ Output enable (OE)

  These driver control signals are supplied to the source driver 304 and the gate driver 306 via the output interface unit 210.

  The pulse widths and generation timings of various driver control signals generated by the timing signal generator 206 are determined to specific values according to the panel resolution (SVGA, XGA, etc.). A conventional timing controller holds a table that defines the relationship between the resolution of each panel, the pulse width of each driver control signal, and the edge timing in an internal or external ROM (Read Only Memory) 212. The timing signal generator 206 receives a signal indicating the resolution of the LCD panel 302 (resolution setting signal), reads the data indicating the pulse width and edge timing by referring to the ROM 212, and generates each driver control signal. It was.

JP 2007-206231 A JP 2000-314868 A JP 2002-268612 A JP 2005-122062 A

  In recent years, technologies for changing the refresh rate according to the content of image data have been introduced for the purpose of power saving. That is, when displaying a normal image with motion, image data is input to the timing controller 200 at a refresh rate of 60 Hz, and when displaying an image with small motion, the refresh rate is as low as 50 Hz or 40 Hz. The As the refresh rate changes, the frequency of the pixel clock signal CLKP / N changes accordingly.

  On the other hand, the setting parameters that define the pulse width and edge timing of each driver control signal are described in units of the period of the pixel clock signal CLKP / N. Therefore, when the frequency of the pixel clock signal CLKP / N dynamically changes, the pulse width and timing of the driver control signal generated based on the same setting parameter dynamically change accordingly.

  However, some driver control signals preferably have their pulse width and timing not varying with frequency. Specifically, when the pulse width (asserted period) of the output enable (OE) varies, an image displayed on the display panel may be disturbed.

  The present invention has been made in view of such a situation, and one of exemplary objects of an aspect thereof is to provide a timing controller capable of suppressing image disturbance due to a change in the frequency of a pixel clock.

  An aspect of the present invention relates to a timing controller that receives a data signal and a pixel clock signal from an image source and generates a driver control signal to be supplied to a data driver and a scan driver that drive a display panel. The timing controller counts the pixel clock signal a number of times specified by a predetermined setting parameter, thereby generating a first timing signal generator that generates a first driver control signal, and a system clock signal having a fixed frequency. Measures the pulse width of one driver control signal and regenerates the second driver control signal having the pulse width indicated by the pulse width data by using the system clock signal and the pulse width measuring unit holding the pulse width data indicating the pulse width. A second timing signal generator. A first driver control signal is output when the pixel clock signal has a first frequency, and a second driver control signal is output when the pixel clock signal has a second frequency different from the first frequency.

  According to this aspect, the pulse width of the driver control signal can be maintained even if the frequency of the pixel clock signal changes. As a result, it is possible to prevent image disturbance due to fluctuations in the frequency of the pixel clock.

  A timing controller according to an aspect receives first and second driver control signals and receives a first driver control signal when the pixel clock signal has a first frequency and a second driver control signal when the pixel clock signal has a second frequency. May be further provided.

  The timing controller according to an aspect may further include a memory that stores setting parameters.

  The pixel clock signal may be generated by adjusting a clock signal embedded in the data signal based on timing information in the data signal.

  The first and second driver control signals may be output enable (OE) signals.

  Another embodiment of the present invention is a display device. The apparatus receives the data from the display panel, the data driver and scan driver for driving the display panel, and the image source, generates a plurality of driver control signals, and supplies the driver and the scan driver together with the image data. A timing controller.

  Yet another aspect of the present invention relates to a method for generating a driver control signal to be supplied to a data driver and a scan driver for driving a display panel based on a data signal and a pixel clock signal from an image source. The method generates a first driver control signal by generating a system clock signal and counting the pixel clock signal a number of times defined by a predetermined setting parameter when the pixel clock signal has a first frequency. Measuring the pulse width of the first driver control signal using the system clock signal and holding pulse width data indicating the pulse width; and when the pixel clock signal has a second frequency different from the first frequency And regenerating a second driver control signal having a pulse width indicated by the pulse width data using the system clock signal.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the timing controller of an aspect of the present invention, it is possible to prevent image disturbance due to fluctuations in the frequency of the pixel clock.

It is a block diagram which shows the structure of a general liquid crystal display. It is a block diagram which shows the structure of a display apparatus provided with the timing controller which concerns on embodiment. 3A and 3B are time charts showing the operation of the timing controller of FIG. It is a block diagram which shows the structure of a part of input interface part of the timing controller which concerns on a modification.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 2 is a block diagram illustrating a configuration of the display device 1 including the timing controller 100 according to the embodiment. The display device 1 includes an LCD panel 2, a source driver 4, a gate driver 6, and a timing controller 100.

  The LCD panel 2 includes a plurality of data lines DL, a plurality of scanning lines SL arranged so as to be orthogonal to the data lines DL, and a plurality of TFTs arranged in a matrix at intersections of the data lines DL and the scanning lines SL ( Thin Film Transistor). The source driver 4 applies a voltage corresponding to the luminance to each data line. The gate driver 6 selects a plurality of scanning lines in order.

  The display device 1 is connected to a graphics processor of a personal computer and an image source 8 including a tuner unit of a television receiver via a digital interface such as HDMI standard, DVI standard, DisplayPort standard. Then, image data to be displayed on the LCD panel 2 is transmitted from the image source 8 to the display device 1 by two-line serial transmission via the clock line and the data line.

  The timing controller 100 of the display device 1 receives image data to be displayed on the LCD panel 302 from the image source 8. The timing controller 100 generates a driver control signal (timing pulse) corresponding to the resolution of the LCD panel 2 and supplies it to the gate driver 6 and the source driver 4 together with the image data.

  The timing controller 100 includes a ROM 10, an input interface unit 12, a logic unit 14, an image output interface unit 16, an oscillator 18, a timing signal generator 30, and an output interface unit 24.

The oscillator 18 oscillates at a predetermined frequency and generates a system clock signal CLK _OSC .

  The input interface unit 12 receives image data from the image source 8 and receives RGB image data RGBP / N, a pixel clock signal CLKP / N (hereinafter also simply referred to as CLK), a data enable signal DE, a vertical synchronization signal Vsync, The horizontal synchronization signal Hsync is acquired and output to the logic unit 14. The logic unit 14 performs necessary signal processing on the image data RGBP / N and outputs the processed signal to the output interface unit 16.

Here, the refresh rate of the image data from the image source 8 changes at a normal frequency of 60 Hz and a lower frequency (for example, 50 Hz or 40 Hz).
The frequency of the pixel clock signal CLK changes according to the refresh rate. Specifically, the frequency of the pixel clock signal CLK can take either a first frequency f ₁ corresponding to a normal refresh rate of 60 Hz or a second frequency f ₂ corresponding to a decrease in the refresh rate.

  The image output interface unit 16 is connected to the source driver 4 via an RSDS standard (Reduced Swing Differential Signaling) or LVDS standard (Low Voltage Differential Signaling) bus, and receives image data (RGB data) for each pixel. Output sequentially.

  Based on the input signal, the logic unit 14 generates a reference signal (start trigger) REF that is asserted at a predetermined timing of each frame, and outputs it to the timing signal generator 30.

  The timing signal generator 30 generates the following driver control signals. Those skilled in the art understand that the names and symbols of each driver control signal may differ depending on the manufacturer and vendor.

1. Driver control signal for source driver 1.1 Start pulse (STH)
A plurality of source drivers 4 and gate drivers 6 are cascade-connected in accordance with the panel size (resolution) of the LCD panel 2. The image data and the driver control signal output from the timing controller 100 sequentially pass through the plurality of source drivers 4. The plurality of source drivers 4 sequentially advance the start pulse STH like a shift register. The source driver 4 to which the start pulse STH is input takes in the image data.

1.2 Latch pulse (LOAD)
The latch pulse LOAD is asserted for each scanning line. When the latch pulse LOAD is asserted, the source driver 4 captures image data for one scanning line.

1.3 AC signal (POL)
The source driver 4 drives the LCD panel 2 while inverting the polarity alternately. The polarity of the source driver 4 is determined by the AC signal POL.

2. Driver control signal for gate driver 2.1 Vertical shift direction input / output signal (STV)
It is supplied to a plurality of gate drivers 6 connected in cascade. The vertical shift direction input / output signal STV is sequentially shifted by the plurality of gate drivers 6.

2.2 Vertical transfer clock (CPV)
Each gate driver 6 takes in the inputted vertical shift direction input / output signal STV at the timing of the positive edge of the vertical transfer clock CPV.

2.3 Output enable (OE)
Data for controlling the state of the output terminal of the gate driver 6. When the output enable OE is asserted, a driving voltage is applied to the scanning line SL, and when negated, the potential of the scanning line SL is fixed.

  The pulse width and generation timing of the driver control signal are set to specific values according to the resolution of the panel. The driver control signal is supplied to the source driver 4 and the gate driver 6 via the output interface unit 24.

  The resolution of the panel may be given as data from the outside, or may be detected by the timing controller 100 based on the data from the image source 8.

  The ROM 10 stores setting parameters necessary for generating each driver control signal for each resolution. This setting parameter defines the pulse width of each driver control signal, the timing of the positive edge, the timing of the negative edge, the slope of the positive edge, the slope of the negative edge, etc. in units of the period of the input clock. The setting parameter may be calculated by calculation.

  A setting parameter corresponding to the resolution of the currently connected LCD panel 2 is read from the ROM 10 to the timing signal generator 30.

  The timing signal generator 30 uses the setting parameter PRM from the ROM 10 to generate each driver control signal. The timing signal generator 30 includes a counter (timer) that counts the pixel clock signal CLK.

  The output interface unit 24 outputs the driver control signal generated by the timing signal generator 30 to the source driver 4 and the gate driver 6.

  Next, the configuration of the timing signal generator 30 will be described. The timing signal generator 30 in FIG. 2 shows only a block that generates an output enable signal (hereinafter referred to as OE signal), and other blocks that generate a driver control signal are omitted.

  The timing signal generator 30 includes a first timing signal generator (hereinafter referred to as a first OE generator) 32, a pulse width measuring unit 34, a second timing signal generator (hereinafter referred to as a second OE generator) 36, a selector 38, A frequency detection unit 40 is provided.

The first OE generator 32 receives setting parameters PRM1 and PRM2 necessary for generating an OE signal from the ROM 10. Configuration parameters PRM1 is time τ1 from start trigger STH to timing the OE signal is asserted (negative edge), defining the normal period _{T CLK1} of the pixel clock signal CLK as a unit. A normal period T _CLK1 of the pixel clock signal CLK is a period when data from the image source 8 is input at a normal refresh rate, specifically, a refresh rate of 60 Hz, and T _CLK1 = 1 / f _1. It is. When the value of the configuration parameter PRM1 is _{Y 1,}
τ ₁ = T _CLK1 × Y ₁
Given in. The period T _CLK2 of the pixel clock signal CLK when the refresh rate is reduced is given by T _CLK2 = 1 / f ₂ , and τ _{1 at} that time is
τ ₁ = T _CLK2 × Y ₁
It becomes.

The setting parameter PRM2 defines the period τ ₂ during which the OE signal is asserted (low level), that is, the pulse width of the OE signal, with the normal period T _CLK1 of the pixel clock signal CLK as a unit. When the value of the configuration parameter PRM2 is _{Y 2,}
τ ₂ = T _CLK1 × Y ₂
Given in.

  The first OE generator 32 generates the first OE signal OE1 by counting the pixel clock signal CLK a number of times specified by the setting parameters PRM1 and PRM2.

The pulse width measurement unit 34 measures the pulse width of the first OE signal OE1 using the system clock signal CLK _OSC having a fixed frequency, and holds pulse width data D1 indicating the pulse width.

The second OE generator 36 reproduces the second OE signal OE2 having the pulse width indicated by the pulse width data D1 using the system clock signal CLK _OSC . Note that the timing at which the second OE signal OE2 transitions to the low level is generated using the parameter PRM1 and the pixel clock signal CLK.

The frequency detector 40 receives the pixel clock signal CLK and detects its frequency. For example, the frequency detection unit 40 may be a counter that counts the period of the pixel clock signal CLK using the system clock signal CLK _OSC . The frequency detection unit 40 outputs data D2 indicating the frequency of the pixel clock signal CLK.

The selector 38 receives the first OE signal OE1 and the second OE signal OE2. The selector 38, when the pixel clock signal CLK has a first frequency _{f 1,} a second 1OE signal OE1, and outputs a first 2OE signal OE2 when pixel clock signal CLK has a second frequency _{f 2.}

  The OE signal selected by the output interface unit 24 is output to the gate driver 6 via the output interface unit 24.

The above is the configuration of the timing controller 100. Next, the operation will be described.
3A and 3B are time charts showing the operation of the timing controller 100 of FIG. FIG. 3A shows a case where the refresh rate is normal, and FIG. 3B shows a case where the refresh rate is lowered.

If the refresh rate is normal 60 Hz, the frequency of the clock signal CLK is detected to be f ₁ by the frequency detector 40. The first OE generator 32 asserts the _first OE signal OE1 (low level) after τ ₁ = T _CLK1 × Y ₁ after the start pulse STH is asserted. Then, the first OE generator 32 negates the first OE signal OE1 (high level) after τ ₂ = T _CLK1 × Y _{2 has} elapsed. The selector 38 outputs the first OE signal OE1 generated in this way.

The pulse width τ _{2 of the first} OE signal OE 1 at this time is measured by the pulse width measuring unit 34 using the system clock signal CLK _OSC . The value Y _{3 of the} data D1 indicating the pulse width τ ₂ is obtained by using the cycle T _OSC (= 1 / f _OSC ) of the system clock signal CLK _OSC .
Y ₃ = τ ₂ / T _OSC
Given in. This data D1 is retained.

The operation when the refresh rate decreases will be described with reference to FIG. The decrease in the refresh rate is detected by the frequency detector 40. The second OE generator 36 asserts the second OE signal OE2 (low level) after τ ₁ = T _CLK2 × Y ₁ after the start pulse STH is asserted. Then, the second OE generator 36 negates (high level) the second OE signal OE2 after τ ₂ ′ = T _OSC × Y _{3 has} elapsed.
The selector 38 outputs the second OE signal OE2 generated in this way.

The above is the operation of the timing controller 100.
As described above, according to the timing controller 100 according to the embodiment, even when the refresh rate is changed, the pulse width τ ₂ of the OE signal can be kept constant, so that image disturbance can be suppressed.

In order to keep the pulse width τ ₂ constant regardless of the refresh rate, it may be possible to store the setting parameter PRM2 in the ROM 10 for each frequency of the pixel clock signal CLK corresponding to a plurality of refresh rates. However, if the refresh rate at the time of decrease is changed due to a platform change, the setting parameter of the ROM needs to be rewritten. Further, it cannot cope with an application in which the refresh rate continuously changes.

On the other hand, according to the timing controller 100 according to the embodiment, it is not necessary to rewrite the setting parameter regardless of how the refresh rate changes, and the pulse width τ ₂ can be kept constant.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

  In the embodiment, the case where the image data RGBP / N and the pixel clock signal CLKP / N are separately input has been described, but the present invention is not limited thereto. For example, the present invention is also effective when a clock signal is embedded in image data, such as an interface of the DisplayPort standard.

FIG. 4 is a block diagram illustrating a partial configuration of the input interface unit of the timing controller according to the modification. The input interface unit 12a in FIG. 4 corresponds to a DisplayPort interface, for example. A clock signal CLK _SYS is embedded in differential input data DATA from an image source (not shown). The frequency of the clock signal CLK _SYS is fixed regardless of the refresh rate. A CDR (Clock Data Recovery) circuit 42 extracts and reproduces the clock signal CLK _SYS . The regenerated clock signal CLK _SYS is used as a system clock of the timing controller 100a.

The latch circuit 44 latches the input data DATA using the regenerated clock signal CLK _SYS . The input data DATA includes various timing information. The parameter detection unit 46 extracts timing information from the input data DATA.

The timing information includes a frequency setting value D3. A PLL (Phase Locked Loop) circuit 48 adjusts the frequency of the clock signal CLK _SYS based on the clock signal CLK _SYS and the set value D3, and generates the pixel clock signal CLK having the frequency f ₁ or f ₂ according to the refresh rate. To do. Since the set value D3 changes according to the clock signal CLK _SYS , the parameter detection unit 46 also functions as the frequency detection unit 40 in FIG.

  By changing the configuration of the input interface unit 12 in this way, the timing controller 100 according to the embodiment can receive image data transmitted in various formats. Even when the refresh rate of the image data is changed, the pulse width of the OE signal can be fixed, so that image disturbance can be prevented.

  In the embodiment, the OE signal is described as an example of the driver control signal whose pulse width should be fixed regardless of the change of the refresh rate. However, in addition to the OE signal, there is a signal whose pulse width should be fixed. A similar architecture can be applied to the signal.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments are defined in the claims. Needless to say, many modifications and changes in arrangement are allowed without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 2 ... LCD panel, 4 ... Source driver, 6 ... Gate driver, 8 ... Image source, 100 ... Timing controller, 10 ... ROM, 12 ... Input interface part, 14 ... Logic part, 16 ... Output interface part , 18 ... Oscillator, 24 ... Output interface unit, 30 ... Timing signal generator, 32 ... First OE generator, 34 ... Pulse width measurement unit, 36 ... Second OE generator, 38 ... Selector, 40 ... Frequency detection unit, 42 ... CDR circuit, 44 ... PLL circuit.

Claims (7)

A timing controller that receives a data signal and a pixel clock signal from an image source and generates a driver control signal to be supplied to a data driver and a scan driver for driving a display panel,
A first timing signal generator for generating a first driver control signal by counting the pixel clock signal a number of times defined by a predetermined setting parameter;
A pulse width measuring unit that measures a pulse width of the first driver control signal using a system clock signal having a fixed frequency, and holds pulse width data indicating the pulse width;
A second timing signal generator for regenerating a second driver control signal having a pulse width indicated by the pulse width data using the system clock signal;
With
The first driver control signal is output when the pixel clock signal has a first frequency, and the second driver control signal is output when the pixel clock signal has a second frequency different from the first frequency. Timing controller.   Receiving the first and second driver control signals, the first driver control signal when the pixel clock signal has the first frequency, and the second driver control signal when the pixel clock signal has the second frequency. The timing controller according to claim 1, further comprising: a selector that outputs.   The timing controller according to claim 1, further comprising a memory that stores the setting parameter.   3. The timing controller according to claim 1, wherein the pixel clock signal is generated by adjusting a clock signal embedded in the data signal based on timing information in the data signal. .   The timing controller according to claim 1, wherein the first and second driver control signals are output enable signals. A display panel;
A data driver and a scan driver for driving the display panel;
5. The timing controller according to claim 1, which receives data from an image source, generates a plurality of driver control signals, and supplies the driver and the scan driver together with image data;
A display device comprising: A method for generating a driver control signal to be supplied to a data driver and a scan driver for driving a display panel based on a data signal and a pixel clock signal from an image source,
Generating a system clock signal; and
Generating a first driver control signal by counting the pixel clock signal a number of times defined by a predetermined setting parameter when the pixel clock signal has a first frequency;
Measuring the pulse width of the first driver control signal using the system clock signal and holding pulse width data indicating the pulse width;
Regenerating a second driver control signal having a pulse width indicated by the pulse width data using the system clock signal when the pixel clock signal has a second frequency different from the first frequency;
A method comprising the steps of:

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