JP2008225894A - Sdram controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SDRAM controller excellent in versatility capable of controlling an SDRAM conforming to specifications of each interface when the SDRAM is used as a data buffer between interfaces. <P>SOLUTION: In the SDRAM controller 111, when a request signal and a write/read start address are inputted, a buffer control part 21 refers to the priority and correspondence relations recorded in a recording part 24, and controls FIFO 113-116 based on the reference result. A control command generation part 22 generates a control command based on the request signal and sends it to the SDRAM 12, and an address generation part 23 increments the address value by an input start address, generates a write/read address, and sends it to the SDRAM 12, thereby performing the write/read of data to the SDRAM 12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an SDRAM controller that controls, for example, an SDRAM (Synchronous Dynamic Random Access Memory) used as a temporary storage buffer for data.

  The SDRAM is used in various devices as a data buffer device for temporarily storing data, in addition to being used as a main memory of a CPU (Central Processing Unit). For example, the data transmission speed between the interfaces is adjusted by temporarily storing data transmitted from one interface to the other interface in the SDRAM. Such a data buffer device includes an SDRAM controller for using the SDRAM as a data buffer, and the controller outputs a control command signal and a write / read address signal to the SDRAM, thereby writing / reading data to / from the SDRAM. Control.

  By the way, in the data buffer device using the SDRAM as described above, a dedicated SDRAM controller has been developed for each device to be used. As described above, the development of the SDRAM controller every time the device is developed is a major factor that hinders the efficiency of design and the shortening of the development period, resulting in a significant increase in manufacturing cost.

In addition, there is an example in which the controller of the storage medium is separated from the CPU and the storage medium, and the storage medium is controlled by the controller, thereby freely combining the CPU and the storage medium (for example, see Patent Document 1) ). In addition, by installing an interface circuit in the controller and arbitrating multiple access requests from the access source by this interface circuit and extracting blocks to be accessed in the storage medium, application changes, access factor changes, There is also an example that flexibly responds to changes in SDRAM timing parameters (see, for example, Patent Document 2).
JP 2001-265647 A JP 2002-328837 A

  As described above, the conventional SDRAM controller has been developed for each device to be used, and has been a factor that hinders the efficiency of design and the shortening of the development period, leading to a significant increase in manufacturing cost.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly versatile SDRAM capable of controlling the SDRAM in accordance with the specifications of each interface when the SDRAM is used as a data buffer between interfaces. To provide a controller.

  To achieve the above object, the present invention provides an SDRAM that temporarily stores data transmitted and received between a plurality of interfaces, and a data transmission between the interfaces and the SDRAM, which is provided corresponding to each of the plurality of interfaces. In an SDRAM controller that is used in a data buffer device including a plurality of buffer buffers for adjusting speed, and controls data writing / reading of the SDRAM and data input / output of the plurality of buffer buffers according to instructions from an external device, The external device receives a request signal for instructing data input / output processing of each of the plurality of buffer buffers, and a write / read start address signal for instructing a write / read start address for the SDRAM according to the request signal. Priority of data write / read processing between the SDRAM and the plurality of interfaces, data write / read processing of the data, and data input / output processing of each buffer buffer indicated by the request signal A registration unit in which correspondence is registered in advance, a buffer buffer control unit that controls the operation of the buffer buffer according to the request signal, and a control command that instructs writing / reading to the SDRAM based on the request signal are generated A control command generation unit that sets the write / read start address signal and generates an address generation unit that generates a write / read address signal to the SDRAM in accordance with the data input / output processing indicated by the request signal The buffer buffer control unit When the request signal is input, it is determined whether or not processing other than the writing / reading processing corresponding to the processing instructed by the request signal is performed by referring to the correspondence relationship. If the process is being performed, the process with the higher priority is completed first with reference to the priority.

  By taking such means, when a request signal is input from an external device, the priority and target relationships registered in advance are referred to, the buffer buffer control unit controls the buffer buffer based on the reference result, and the control is performed. Since the command generation unit and the address generation unit control the writing / reading of the SDRAM, it is possible to easily write / read the data to / from the SDRAM in accordance with the interface specifications according to the instruction from the external device. . In addition, since the priority order and the correspondence relationship are updated according to the number of interfaces, the number of interfaces can be easily handled. As a result, even if the number of interfaces changes, it becomes possible to flexibly cope with the change, and the versatility is greatly improved. As a result, the design efficiency and the development period can be shortened, and the manufacturing cost can be drastically reduced.

  As described above, according to the configuration of the present invention, even if the number of interfaces changes, it is possible to flexibly cope with the change, and the versatility is greatly improved. As a result, the design efficiency and the development period can be shortened, and the manufacturing cost can be drastically reduced. Therefore, according to the present invention, when an SDRAM is used as a data buffer between interfaces, it is possible to provide a highly versatile SDRAM controller that can freely control the SDRAM according to the specifications of each interface. Can do.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a data buffer device using an SDRAM controller according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a data buffer device. The data buffer device 1 follows an instruction from a CPU (Central Processing Unit) 2 and an interface (here, a bus interface) A and an interface (here, a flash memory as an example). A data processor 11 using an FPGA (Field Programmable Gate Array) for managing input / output data between the interfaces A and B, and the data And SDRAM 12 for temporarily storing input / output data managed by the processing device 11.

  The FPGA data processor 11 includes an SDRAM controller 111, a CPU interface module 112 connected to the CPU 2, an input FIFO (First In First Out) memory 113 serving as a buffer buffer between the bus interface A and the SDRAM 12, and an output. FIFO memory 114, and an input FIFO memory 115 and an output FIFO memory 116 that serve as buffer buffers between the flash memory interface B-SDRAM 12.

The CPU interface module 112 is a request signal that instructs the CPU 2 to write data to the input FIFO memory (hereinafter referred to as input FIFO) 113 and 115 and the output FIFO memory (hereinafter referred to as output FIFO) 114 and 116.
A_W_REQ (data write instruction to the input FIFO 113),
A_R_REQ (data write instruction to the output FIFO 114),
B_W_REQ (data write signal to the input FIFO 115),
B_R_REQ (data write signal to the output FIFO 116),
Is output to the SDRAM controller 111. Although not shown, each request signal is output to the input FIFOs 113 and 115 and the output FIFOs 114 and 116 that are the target of the request signal.

Further, the module 112 receives a write / read start address signal for the SDRAM 12 from the CPU.
A_W_ADRS (data write address from the input FIFO 113),
A_R_ADRS (data read address to output FIFO 114),
B_W_ADRS (data write address from the input FIFO 115),
B_R_ADRS (data read address to output FIFO 116),
Is output to the SDRAM controller 111.

  The input FIFO 113 is for adjusting the data transmission speed from the bus interface A to the SDRAM 12, and starts writing data output from the bus interface A when receiving a request signal A_W_REQ from the CPU interface module 112. When the accumulated data amount exceeds the specified value, an OK signal is output to the SDRAM controller 111, and when a write enable signal WE (Write Enable) is received from the SDRAM controller 111, the accumulated data is output to the SDRAM 12.

  The output FIFO 114 is for adjusting the data transmission speed from the SDRAM 12 to the bus I / F 3. When receiving the A_R_REQ request signal from the CPU interface module 112, the output FIFO 114 starts writing and storing the data output from the SDRAM 12. When the amount of data exceeds a specified value, an OK signal is output to the SDRAM controller 111. When a read permission signal RE (Read Enable) is received from the SDRAM controller 111, the accumulated data is output to the bus interface A.

  The input FIFO 115 is for adjusting the data transmission speed from the flash memory interface B to the SDRAM 12. When the B_W_REQ request signal is received from the CPU interface module 112, the data output from the flash memory interface B is written. When the amount of accumulated data exceeds a specified value, an OK signal is output to the SDRAM controller 111. When the write permission signal WE is received from the SDRAM controller 111, the accumulated data is output to the SDRAM 12.

  The output FIFO 116 is for adjusting the data transmission speed from the SDRAM 12 to the flash memory interface B. Upon receiving a B_R_REQ request signal from the CPU interface module 112, the output FIFO 116 starts writing data output from the SDRAM 12. When the amount of accumulated data exceeds a specified value, an OK signal is output to the SDRAM controller 111, and when the read permission signal RE is received from the SDRAM controller 111, the accumulated data is output to the flash memory interface B.

  In the SDRAM controller 111, the receiving unit 20 receives the request signal and the write / read start address signal from the CPU interface module 112, notifies the buffer controller 21 and the control command generator 22 of the request signal, The address generation unit 23 is notified.

  The recording unit 24 includes a data write status to the SDRAM 12 from the bus interface A, a data read status to the bus interface A, a data write status from the flash memory interface B4, and a data read status to the flash memory interface B. Each priority is registered in advance. Also, the correspondence between the status and the request signal is registered in advance. In this embodiment, the data write status from the bus interface A to the SDRAM 12 corresponds to A_W_REQ, the data read status to the bus interface A of the SDRAM 12 corresponds to A_R_REQ, and the data write from the flash memory interface B to the SDRAM 12 is performed. The status corresponds to B_W_REQ, and the data read status to the flash memory interface B of the SDRAM 12 corresponds to B_R_REQ. Furthermore, when the number of used interfaces increases or decreases, the recording unit 24 can update the priority order and the corresponding relationship according to the increase or decrease of the status number.

  When the buffer control unit 21 receives the request signal from the receiving unit 20, the buffer control unit 21 refers to the correspondence recorded in the recording unit 24, and determines whether a status other than the status corresponding to the request signal is being executed. Determine whether. When a status other than the status corresponding to the request signal is not executed, the presence / absence of an OK signal from the FIFO corresponding to the request signal is determined. When a status other than the status corresponding to the request signal is being executed, the priority order recorded in the recording unit 24 is referred to, and the status with the highest priority is prioritized. At this time, the input request signal waits until the priority status is completed. Also, when a plurality of request signals are received at a time, the priority order is referred to, and the request signal corresponding to the highest priority status is given priority. At this time, other than the priority request signal, the system waits until the status corresponding to the request signal is completed. Further, when the buffer control unit 21 receives the OK signal from each FIFO, the buffer control unit 21 outputs the write permission signal WE or the read permission signal RE to the FIFO that has output the OK signal.

  The control command generation unit 22 generates a control command signal for writing to and reading from the SDRAM 12 based on the request signal, and outputs the control command signal to the SDRAM 12. These control command signals include NOP (no control), PAL (precharge), MRA (mode register set), REF (refresh), ACT (bank active), RDA (auto read), and WRA (auto write). There are types. When there is no request signal, REF is generated.

  The address generation unit 23 includes the same number of address counters as the number of statuses, and corresponds to the input write / read start address. The address generation unit 23 receives a write / read start address signal from a corresponding address counter, and generates a write / read address signal for the SDRAM 12 by sequentially incrementing from the start address. Then, the generated write / read address signal is output to the SDRAM 12. When the status is temporarily suspended by the control of the buffer control unit 21, the address increment is temporarily suspended, and the write / read address of the suspended status is held. When the priority status is completed, the increment of the suspended address is resumed and a write / read address signal is generated. The address generator 23 uses the FPGA function to easily increase or decrease the number of address counters by rearranging the logic of the gate array in accordance with the increase or decrease of the number of statuses accompanying the increase or decrease of the number of interfaces. be able to.

  Next, the processing operation of the SDRAM controller 111 in the above configuration will be described.

  The SDRAM controller 111 in this embodiment can be applied to a data buffer device of a flash memory information storage device.

  FIG. 2 is a flowchart showing the processing operation of the SDRAM controller 111 according to an embodiment of the present invention when video and audio material data is recorded from the bus to the flash memory. At this time, the priority of the status recorded in the recording unit 24 is the first place for writing data from the bus interface A to the SDRAM 12 and the second place for reading the data of the SDRAM 12 to the flash memory interface B. Suppose there is.

  The SDRAM controller 111 first receives A_W_REQ and A_W_ADRS and B_R_REQ and B_R_REQ from the CPU interface module 112 (step ST2a). At this time, A_W_REQ and B_R_REQ are output from the CPU interface module 112 to the input FIFO 113 and the output FIFO 116, respectively. When the input FIFO 113 receives A_W_REQ, it starts writing data from the bus interface A.

  Subsequently, the priority of the statuses corresponding to the two request signals is referred to (step ST2b), A_W_REQ having a higher priority is selected, and B_R_REQ is waited (step ST2c). When A_W_REQ is selected, it is determined whether or not another status is executed when this signal is selected (step ST2d). If another status is not executed (No in step ST2d), A_W_REQ is determined for SDRAM12. It is determined whether it is writing or reading (step ST2e).

  When another status is being executed (No in step ST2d), the priority order is referred to (step ST2f), and it is determined whether the priority order of the other status being executed is lower than the status corresponding to A_W_REQ. (Step ST2g). If the priority is low (Yes in step ST2g), the processing operation proceeds to ST2e. If the priority is high (No in step ST2g), the other statuses being executed are completed (step ST2h), and the processing operation proceeds to ST2d.

  In the determination at ST2e, A_W_REQ corresponds to the status of writing data to the SDRAM 12 (Yes at step ST2e), so the processing operation proceeds to ST2i, and whether there is an OK signal from the input FIFO 113 that is the target of A_W_REQ. Determine whether. If there is an OK signal from the target input FIFO 113, the write enable signal WE is output to the input FIFO 113 and at the same time the WRA and the write address signal are output to the SDRAM 12 (step ST2j) to determine whether there is a waiting request signal. Is determined (step ST2k). At this time, since B_R_REQ is on standby, this standby B_R_REQ is selected (step ST2l).

  Subsequently, the operation process proceeds to ST2e. In the determination in ST2e, B_R_REQ corresponds to the status of reading data from the SDRAM 12 (No in step ST2e), so the processing operation proceeds to ST2m, and the RDA and the read address signal are output to the SDRAM 12. When a certain amount of material data (for example, the minimum writing unit of the flash memory 4) is accumulated in the SDRAM 12 by this RDA, writing of the accumulated material data to the output FIFO 116 that is the target of B_R_REQ is started. . Subsequently, it is determined whether or not there is an OK signal from the output FIFO 116 (step ST2m). If there is an OK signal (Yes in step ST2n), RE is output to the output FIFO 116 (step ST2o). When RE is output, the processing operation proceeds to ST2k.

  As a result of the determination in step ST2k, since there is no request signal waiting (No in step ST2k), the processing operation is terminated.

  On the contrary, when reproducing the material data recorded in the flash memory interface B, the SDRAM controller 111 first saves the material data stored in the flash memory interface B once in the SDRAM 12 via the input FIFO 115. To do. Subsequently, when a certain amount of material data (for example, ECC packet unit) is accumulated in the SDRAM 12, it is output to the bus interface A of the apparatus via the output FIFO 114.

  As described above, in the above embodiment, when a request signal is input to the SDRAM controller 111, the priority order and the correspondence relationship recorded in the recording unit 24 are referred to, and the buffer control unit 21 controls the FIFOs 113 to 116. The control command generation unit 22 and the address generation unit 23 control the writing / reading of the SDRAM 12 to temporarily store the transmission data by the SDRAM 12. At this time, the write / read address signal to the SDRAM 12 is generated by incrementing the address counter by the address generator 23 with the input write / read start address signal. In addition, the SDRAM controller 111 can easily increase or decrease the number of interface connections by increasing or decreasing the number of the address counters according to the number of interfaces used and updating the priority and correspondence of the status of the recording unit 24. It is possible to correspond to.

  Therefore, since it is possible to easily cope with the increase / decrease in the number of interfaces, it is possible to provide a general-purpose SDRAM controller that controls SDRAM for temporary storage of data and can be used in various devices. Efficiency and shortening the development period.

  The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the data buffer device 1 is used for data transmission between the two interfaces of the bus interface A and the flash memory interface B has been described. However, the data buffer device 1 is installed between two or more interfaces. Even in the case of, it can be similarly implemented.

  In the above embodiment, an example in which the write / read start address signal is received from the CPU interface module 112 has been described. However, the present invention can be similarly implemented even when the address start signal is set in the address generation unit 23 from the beginning.

  Furthermore, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment.

The block diagram which shows the structure of the data buffer apparatus using the SDRAM controller which concerns on one Embodiment of this invention. 2 is a flowchart showing a processing operation of the SDRAM controller of the embodiment shown in FIG. 1.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Data buffer device, 2 ... CPU, 11 ... FPGA, 12 ... SDRAM, 111 ... SDRAM controller, 112 ... CPU interface module, 113, 115 ... Input FIFO memory, 114, 116 ... Output FIFO memory, 20 ... Receive Reference numeral 21, Buffer controller, 22 Control command generator, 23 Address generator, 24 Recording unit, A Bus interface, B Flash memory interface

Claims (10)

SDRAM (Synchronous Dynamic Random-Access Memory) that temporarily stores data transmitted and received between multiple interfaces, and corresponding to each of the multiple interfaces, and adjusts the data transmission speed between the interfaces and the SDRAM In an SDRAM controller that is used in a data buffer device including a plurality of buffer buffers, and that controls data writing / reading of the SDRAM and data input / output of the plurality of buffer buffers according to instructions from an external device,
The external device receives a request signal for instructing data input / output processing of each of the plurality of buffer buffers, and a write / read start address signal for instructing a write / read start address for the SDRAM in accordance with the request signal. A receiving part;
The priorities of data write / read processing between the SDRAM and the plurality of interfaces, and the correspondence between the data write / read processing and the data input / output processing of each buffer buffer indicated by the request signal are preliminarily determined. A registration department to be registered;
A buffer control unit for controlling the operation of the buffer buffer according to the request signal;
A control command generator for generating a control command for instructing writing / reading to / from the SDRAM based on the request signal;
An address generation unit that sets the write / read start address signal and generates a write / read address signal to the SDRAM according to the data input / output processing indicated by the request signal;
The buffer buffer control unit determines whether or not processing other than the write / read processing corresponding to the processing instructed by the request signal is performed with reference to the correspondence relationship when the request signal is input. An SDRAM controller characterized in that when a process other than the corresponding process is being performed, the higher priority process is completed first with reference to the priority order. The address generation unit includes a plurality of address counters for generating a write / read address signal for the SDRAM for writing / reading data between the SDRAM and each of the plurality of interfaces. 2. The SDRAM controller according to claim 1, wherein an address counter corresponding to is selected, the write / read address start signal is set in the counter, and address generation is started. 2. The buffer buffer control unit according to claim 1, wherein when a plurality of request signals are received together in the receiving unit, the buffer buffer control unit determines a processing order of the plurality of request signals based on the priority order. SDRAM controller. The reception unit, registration unit, buffer buffer control unit, control command generation unit, and address generation unit are formed by an FPGA (Field Programmable Gate Array), and the number of buffer buffers used based on parameters given from the external device 2. The SDRAM controller according to claim 1, wherein the gate array is controlled so as to correspond to. 2. The SDRAM controller according to claim 1, wherein the priority order and the correspondence relationship are updated according to the number of buffer buffers used. SDRAM (Synchronous Dynamic Random-Access Memory) that temporarily stores data transmitted and received between multiple interfaces, and corresponding to each of the multiple interfaces, and adjusts the data transmission speed between the interfaces and the SDRAM In an SDRAM control method using an SDRAM controller, which is used in a data buffer device including a plurality of buffer buffers, and controls data writing / reading of the SDRAM and data input / output of the buffer buffers according to instructions from an external device ,
The external device receives a request signal for instructing data input / output processing of each of the plurality of buffer buffers, and a write / read start address signal for instructing a write / read start address for the SDRAM in accordance with the request signal. ,
Priorities of data writing / reading processing between the SDRAM and the plurality of interfaces, and correspondence between the data writing / reading processing and the data input / output processing of each buffer buffer indicated by the request signal in advance Register,
Controlling the operation of the buffer buffer according to the request signal;
Based on the request signal, a control command for instructing writing / reading to / from the SDRAM is generated,
Set the write / read start address signal to generate a write / read address signal to the SDRAM according to the data input / output processing indicated by the request signal,
Control of the operation of the buffer buffer refers to whether or not processing other than the write / read processing corresponding to the processing instructed by the request signal is performed with reference to the correspondence relationship when the request signal is input. The SDRAM control method is characterized in that when a process other than the corresponding process is performed, the process with the higher priority is completed first with reference to the priority. As the write / read address signal for the SDRAM for writing / reading data between the SDRAM and each of the plurality of interfaces, an address counter corresponding to the instruction of the request signal is selected from a plurality of address counters. 7. The SDRAM control method according to claim 6, wherein the generation is started by setting the write / read address start signal in the counter. 7. The SDRAM according to claim 6, wherein the control of the operation of the buffer buffer determines the processing order of the plurality of request signals based on the priority when the plurality of request signals are received together. Control method. Receiving the request signal and the write / read start address signal, registering the priority order and the correspondence relationship, controlling the operation of the buffer buffer, generating the control command and generating the write / read address signal, 7. The gate array is controlled to be rearranged so as to correspond to the number of used buffer buffers based on a parameter formed by a field program gate array and given from the external device. The SDRAM control method described in 1. 7. The SDRAM control method according to claim 6, wherein the priority order and the correspondence relationship are updated in accordance with the number of buffer buffers used.

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