JP4107278B2 - Processor control circuit and information processing apparatus - Google Patents

Description

  The present invention relates to a processor control circuit that controls an operating state of a processor during execution of a predetermined process without using a processor, and an information processing apparatus that executes the predetermined process without using a processor.

Conventionally, this type of technology has stopped the supply of the clock signal to the processor during execution of the DMA processing mode by the DMA (Direct Memory Access) controller, that is, during the DMA processing by the I / O unit and the memory. A technique for reducing electric power is known (see, for example, Patent Document 1).
JP-A-8-83133

However, in the above prior art, during the DMA processing, the supply of the clock signal to the processor is always stopped. Therefore, the processing cannot be performed by the processor during the DMA processing. There was a risk that the processing efficiency would decrease.
An object of the present invention is to solve the above-mentioned unsolved problems of the prior art, and a processor control circuit capable of reducing power consumption by a processor while preventing a decrease in processing efficiency by the processor. It is another object of the present invention to provide an information processing apparatus.

In order to solve the above-described problem, the processor control circuit according to the first invention includes a functional unit capable of executing a predetermined process without using a processor, and after the execution of the predetermined process is started in the functional unit, An inquiry detection unit that detects whether or not the processor has inquired about an operation state of the function unit, an end detection unit that detects the end of the predetermined process in the function unit, and execution of the predetermined process in the function unit is started. The operation state of the processor is maintained, and when the inquiry detection unit detects that the processor has inquired about the operation state of the function unit, the end detection unit performs the predetermined process in the function unit. End until is detected, and a suppressor for suppressing unit operations related query operating state of the functional unit by the processor And said that there were pictures.

As a method for suppressing the operation related to the inquiry about the operation state of the functional unit, a method for reducing the frequency of inquiries, a method for prohibiting inquiries, and the like can be given.
The processor control circuit according to a second aspect of the present invention is the processor control circuit, wherein when the inquiry detecting unit detects that the processor has inquired about the operating state of the functional unit, the termination detecting unit detects the functional unit. Until the end of the predetermined process is detected, the operation relating to the inquiry about the operation state of the functional unit by the processor is delayed.

The processor control circuit according to a third aspect of the present invention is the processor control circuit according to the present invention, wherein when the inquiry detecting unit detects that the processor has inquired about the operating state of the functional unit, the termination detecting unit detects the functional unit. The frequency of the clock signal supplied to the processor is lowered until the end of the predetermined processing is detected .
According to the first to third aspects of the invention, even if the predetermined process is executed in the functional unit, the processor can continue the process until the processor inquires about the operating state of the functional unit. When an inquiry about the operating state of a functional unit is made by the processor, the inquiry about the operating state of the functional unit by the processor is suppressed, thereby reducing power consumption by the processor while preventing a decrease in processing efficiency by the processor. Can do.

The processor control circuit according to a fourth aspect of the present invention is the processor control circuit, wherein when the inquiry detecting unit detects that the processor has inquired about the operating state of the functional unit, the termination detecting unit detects the functional unit. The supply of the clock signal to the processor is stopped until the end of the predetermined processing is detected .
According to the fourth aspect of the invention, the switching operation of the transistors constituting the inside of the processor is stopped, and the power consumption by the processor can be further reduced.

The processor control circuit according to a fifth aspect of the invention is characterized in that the supply of the clock signal can be temporarily resumed when the supply of the clock signal is stopped.
Furthermore, in the processor control circuit according to a sixth aspect of the present invention, the functional unit can execute DMA processing, and the suppression unit transfers data of a predetermined length when the supply of the clock signal is stopped. It is characterized in that the supply of the clock signal is temporarily resumed every time it is performed.

According to the fifth and sixth inventions, for example, even if the supply of the clock signal to the processor is stopped during the DMA processing, the clock signal is supplied before the DMA processing is completed, that is, during the DMA processing. You can resume temporarily.
In the processor control circuit according to a seventh aspect of the invention, the functional unit stores a state storage unit that stores execution state information indicating an operation state of the functional unit, and the processor outputs a read signal of the execution state information. When the inquiry detection unit detects that the operation state of the function unit has been inquired, the execution state corresponds to the end detection unit detecting the end of the predetermined process in the function unit. And a status notification unit that notifies the processor that the predetermined processing in the functional unit is completed by outputting a read completion signal indicating that the reading of information is completed to the processor.

According to the seventh aspect of the invention, since the operation state can be inquired by the execution state information read operation by the processor, the programming for the process of detecting the execution state of the predetermined process is facilitated. be able to.
In order to solve the above-described problem, an information processing apparatus according to an eighth invention includes a processor that executes predetermined arithmetic processing, a functional unit that can execute the predetermined processing without using the processor,
After the execution of the predetermined process is started in the functional unit, an inquiry detection unit that detects whether or not the processor has inquired about an operation state of the functional unit, and an end that detects the end of the predetermined process in the functional unit When the execution of the predetermined process is started in the detection unit and the function unit, the operation state of the processor is maintained, and further, the inquiry detection unit detects that the processor inquires about the operation state of the function unit A suppression unit that suppresses an operation related to an inquiry about an operation state of the functional unit by the processor until the end detection unit detects the end of the predetermined process in the functional unit. To do.

Note that, as a method of suppressing the operation related to the inquiry about the operation state of the functional unit, a method of reducing the frequency of inquiries, a method of prohibiting inquiries, and the like can be cited as in the first invention.
Further, in the information processing device according to the ninth invention, when the suppression unit detects that the processor has inquired about an operating state of the function unit, the end detection unit detects the function unit. Until the end of the predetermined process is detected, the operation relating to the inquiry about the operation state of the functional unit by the processor is delayed.

Furthermore, in the information processing apparatus according to the tenth aspect of the invention, when the suppression unit detects that the processor has inquired about the operating state of the function unit, the end detection unit detects the function unit. The frequency of the clock signal supplied to the processor is lowered until the end of the predetermined processing is detected .
According to the eighth to tenth inventions, even if a predetermined process is executed in the functional unit, the processor can continue the process until the processor inquires about the operating state of the functional unit. When an inquiry about the operating state of a functional unit is made by the processor, the inquiry about the operating state of the functional unit by the processor is suppressed, thereby reducing power consumption by the processor while preventing a decrease in processing efficiency by the processor. Can do.

The information processing apparatus according to an eleventh aspect of the present invention is the information processing apparatus, wherein when the inquiry detecting unit detects that the processor has inquired about an operating state of the function unit, the end detecting unit detects the function unit. The supply of the clock signal to the processor is stopped until the end of the predetermined processing is detected .
According to the eleventh aspect, the switching operation of the transistors constituting the inside of the processor is stopped, and the power consumption by the processor can be further reduced.

The information processing apparatus according to a twelfth aspect of the invention is characterized in that the suppression unit can temporarily resume the supply of the clock signal when the supply of the clock signal is stopped.
In the information processing apparatus according to a thirteenth aspect of the present invention, the functional unit can execute DMA processing, and the suppression unit transfers data of a predetermined length by DMA transfer when the supply of the clock signal is stopped. It is characterized in that the supply of the clock signal is temporarily resumed every time it is performed.

According to these twelfth and thirteenth inventions, for example, even if the supply of the clock signal to the processor is stopped during the DMA processing, the clock signal is supplied before the DMA processing ends, that is, during the DMA processing. You can resume temporarily.
The information processing apparatus according to a fourteenth aspect of the present invention is that the functional unit includes a detection condition storage unit that stores detection condition information indicating a detection condition related to an operation state of the function unit, and the processor detects the operation state. The operation condition is inquired by outputting a write signal to the detection condition storage section of the detection condition information in which the predetermined condition is set, and the function section indicates the operation condition indicated by the detection condition information. A state notifying unit for notifying the processor that a predetermined process has been completed by outputting a write completion signal indicating that the writing of the detection condition information has been completed to the processor when a condition is satisfied. It is characterized by providing .

Furthermore, in the information processing apparatus according to the fifteenth aspect, the functional unit can execute a plurality of the predetermined processes, and the processor can execute information between each of the predetermined processes and a plurality of the predetermined processes. by outputting a write signal to the detection condition storing unit of the detection condition information including the detection condition of the set operation condition, inquires of the operating state, the state notification unit in the functional unit, the When the operation state coincides with the detection condition between the predetermined processes indicated in the detection condition information, the write completion signal is output to the processor to notify the processor that the predetermined process in the functional unit is completed. It is characterized by that.

  According to these fourteenth and fifteenth inventions, when the processor inquires about the operation state of the functional unit, detection condition information indicating a detection condition related to the operation state is written in the detection condition storage unit. Therefore, when a plurality of predetermined processes are executed in the functional unit, such as when there are a plurality of DMA channels, it is possible to set an intricate condition between them and inquire about the operation state, so that the efficient software Execution control can be performed.

  As described above, according to the present invention, it is possible to provide a processor control circuit and an information processing apparatus capable of reducing power consumption by a processor while preventing a decrease in processing efficiency by the processor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
First, an embodiment of the processor control circuit of the present invention will be described.
FIG. 1 is a block diagram showing a schematic configuration of an information processing apparatus 1 including a processor control circuit according to the first embodiment of the present invention. As shown in FIG. 1, the information processing apparatus 1 includes a processor 2, a RAM (Random Access Memory) 3, a DMA (Direct Memory Access) controller 4 having a state notification register 7, and a clock control unit 5. Each unit except the clock control unit 5 is connected to the data bus 6 so as to be able to exchange data.

Among these, the processor 2 reads various programs and data such as a basic control program and application program stored in a storage device (not shown), and develops and executes these various programs and data in a work area provided in the RAM 3. And various processes, such as control of each part with which the information processing apparatus 1 is provided, and arithmetic processing, are performed.
Further, as shown in the flowchart of FIG. 2, the processor 2 sets a parameter (DMA parameter) for DMA processing (step S101), and outputs a DMA start command for causing the DMA controller 4 to start DMA processing (step S101). S102). Then, a status notification register read request signal is output to the DMA controller 4 in order to acquire the DMA operation status. Thereafter, when a DMA execution status flag indicating that DMA processing is not in progress is read from the DMA controller 4, the output of the status notification register read request signal is stopped, and the reading of the status notification register is completed (step S103). Note that the processor 2 continues to output the status notification register read request signal even if the supply of the clock signal is stopped during the output of the status notification register read request signal.

The RAM 3 forms a work area for developing various programs when the processor 2 executes the above-described processing according to various programs, and also has a memory area for developing data related to various processes executed by the processor 2. Form.
Furthermore, when the DMA start command is output from the processor 2, the DMA controller 4 starts the DMA processing.

  When the status notification register read request signal is input from the processor 2, the DMA controller 4 determines whether or not DMA processing is in progress. If the DMA processing is not in progress, it is stored in the status notification register 7. A DMA execution status flag indicating that DMA processing is not in progress is read out by the processor 2, and when DMA processing is in progress, a WAIT signal that causes the supply of the clock signal to the processor 2 to be stopped is output to the clock controller 5. To do.

Further, the clock control unit 5 determines whether or not the WAIT signal is output from the DMA controller 4, and when the WAIT signal is not output, supplies the clock signal to the processor 2 and outputs the WAIT signal. If so, the supply of the clock signal is stopped.
Next, the operation of the information processing apparatus 1 according to the present embodiment will be described in detail.
First, as shown in FIG. 3, it is assumed that a DMA request signal for requesting the DMA controller 4 to start DMA is output in the cycle “2”. Then, in cycle “3”, the DMA controller 4 outputs a signal notifying that DMA transfer processing is in progress. As shown in FIG. 2, the processor 2 executes predetermined processing. First, in step S101, a DMA parameter is set. In step S102, a DMA start command is sent to the DMA controller 4 as shown in FIG. Is output. Then, in cycle “3”, as shown in FIG. 3C, the operation state of the DMA controller is set to “in operation”, and the DMA processing is started by the DMA controller 4.

  Further, while the DMA processing is continued, through cycles “4” to “6”, in cycle “7”, as shown in FIG. 3D, the processor 2 sends a status notification register read request to the DMA controller 4. A signal is output. Then, in cycle “8”, as shown in FIG. 3F, a high level WAIT signal is output from the DMA controller 4 to the clock controller 5, and in cycle “9”, as shown in FIG. In addition, the operation clock signal supplied to the processor 2 by the clock controller 5 is stopped.

Furthermore, it is assumed that the operation state of the DMA controller 4 is set to the low level and the DMA processing is completed in the cycle “14” through the cycles “10” to “13” as shown in FIG. 3C.
Then, in cycle “15”, the DMA execution state flag indicating that the DMA processing is not in progress is read to the processor 2 by the DMA controller 4, the WAIT signal is stopped, and the clock signal from the clock control unit 5 to the processor 2 is read. When the DMA execution status flag is read, the status notification register read request signal is stopped, and the processing of the processor 2 is restarted in cycle “16”.

  Thus, according to the information processing apparatus 1 of the present embodiment, even if the DMA processing is executed by the DMA controller 4, the processor 2 inquires about the operation state of the DMA controller 4, that is, the state notification register read request signal is transmitted. Until the output, the processor 2 can continue the processing so far, and when the processor 2 outputs the status notification register read request signal, the supply of the clock signal to the processor 2 is stopped. The power consumption by the processor 2 can be reduced while preventing the processing efficiency by the processor 2 from being lowered.

In addition, since the supply of the clock signal is stopped until the DMA processing is completed, it is possible to prevent the inquiry about the operation state of the DMA controller 4 from being performed many times during the execution of the DMA processing. Power consumption can be further reduced.
Incidentally, as shown in FIG. 15, in the conventional method of causing the processor 2 to stop its own operation when the DMA processing is being executed, an inquiry about the operating state of the DMA controller 4 is made during the DMA processing. It must be executed several times by itself and power consumption by the processor 2 becomes large.

  Further, according to the information processing apparatus 1 of the present embodiment, the processor 2 can inquire about the operation state of the DMA controller 4 by the operation of reading the state notification register 7, and therefore programming for processing for detecting the DMA execution state Can be made easy.

(Second Embodiment)
Next, a second embodiment of the processor control circuit of the present invention will be described.
In the present embodiment, when the supply of the clock signal to the processor 2 is stopped, the supply of the clock signal is temporarily resumed every time data of a predetermined length is DMA-transferred. Different from the embodiment. Specifically, as shown in FIG. 4, a transfer data length setting unit 8 for setting a data length for DMA transfer is provided in the DMA controller 4, and every time the data length is transferred to the DMA controller 4, The processor 2 is made to read the DMA execution state flag. Further, instead of the processing of FIG. 2 performed by the processor 2 of the first embodiment, the control processing of steps S201 to S207 of FIG. 5 is performed. In addition, this embodiment contains many structures equivalent to the said 1st Embodiment, an equivalent code | symbol is attached | subjected to an equivalent structure and the detailed description is abbreviate | omitted.

First, in step S201, DMA parameters are set.
In step S202, the transfer data length setting unit 8 sets the data length for continuous DMA transfer, that is, the data length for temporarily restarting the supply of the clock signal to the processor 2.
In step S203, a DMA start command is output to the DMA controller 4.

Next, the process proceeds to step S <b> 204, and a status notification register read request signal is output to the DMA controller 4.
Next, the process proceeds to step S205, and after the data length set by the transfer data length setting unit 8 is DMA-transferred, the DMA transfer state is read from the status notification register 7 and the DMA transfer process is completed. If the control flow of FIG. 5 is finished and the DMA transfer is not finished, it is determined whether or not the processor 2 needs to execute a predetermined process (step S206). If the predetermined process execution is not necessary, the control returns to step S204, and if the predetermined process execution is necessary, the process is performed in step S207. Then, when the execution of the predetermined process in step S207 is completed, the process proceeds to step S204.

Next, the operation of the information processing apparatus 1 according to the present embodiment will be described in detail.
First, as shown in FIG. 6, it is assumed that a DMA request signal for requesting the DMA controller 4 to start DMA is output in the cycle “1”. Then, in cycle “2”, the DMA controller 4 outputs a signal notifying that DMA transfer processing is in progress. As shown in FIG. 5, the processor 2 executes predetermined processing. First, in step S201, the DMA parameter is set. In step S202, the data length for continuous DMA transfer is set by the transfer data length setting unit 8. In step S203, a high-level DMA start command is output to the DMA controller 4 as shown in FIG. 6B, and the DMA processing is started by the DMA controller 4.

  In addition, as the DMA processing continues, after going through cycle “3”, in cycle “4”, as shown in FIG. Assume that a level status notification register read request signal is output. Then, in cycle “5”, as shown in FIG. 6F, the DMA controller 4 outputs a high-level WAIT signal to the clock controller 5, and in cycle “6”, as shown in FIG. 6H. In addition, the operation clock signal supplied to the processor 2 by the clock controller 5 is stopped.

  Further, after cycle “7”, in cycle “8”, as shown in FIG. 6C, the data length set by transfer data length setting unit 8 is DMA-transferred, and the operating state of the DMA controller is low level. Suppose that Then, the DMA execution state flag is read by the DMA controller 4 to the processor 2, the WAIT signal is stopped, the supply of the clock signal from the clock controller 5 to the processor 2 is temporarily resumed, and the DMA execution state is When the flag is read, the status notification register read request signal is stopped, and the DMA transfer is not completed, so the determination in step S205 is “No”, and if the determination in step S206 is “Yes”, a predetermined process is performed in step S207. Execute. In cycle “9”, a high-level state notification register read request signal is output again from the processor 2 to the DMA controller 4 in step S204.

As described above, in the present embodiment, even if the supply of the clock signal to the processor 2 is stopped during the DMA process, the supply of the clock signal is temporarily performed before the DMA process ends, that is, during the DMA process. Can be resumed.
In the above embodiment, the DMA controller 4 constitutes a functional unit, the clock control unit 5 constitutes a suppression unit, and the state notification register 7 constitutes a state storage unit.

The above embodiment shows an example of the processor control circuit according to the present invention, and does not limit the configuration or the like.
For example, in the above-described embodiment, when the status notification register read request signal is output from the processor 2, the supply of the clock signal to the processor 2 is stopped. However, the present invention is not limited to this. The frequency of the clock signal supplied to 2 may be lowered so that the frequency of reading the status notification register 7 is lowered.

Further, the example in which the supply of the clock signal to the processor 2 is stopped and the function of the processor 2 is completely stopped (set to the WAIT state) is shown, but the present invention is not limited to this. The interrupt processing program may be activated (set to the sleep state) by an external interrupt while the supply of signals is stopped.
Furthermore, although the example in which the clock control unit 5 controls the supply state of the clock signal to the processor 2 has been shown, the present invention is not limited to this. For example, the DMA controller by the processor 2 is simply used until the DMA processing is completed. The operation relating to the inquiry about the operation state 4 may be delayed. By doing so, the program executed by the processor 2 can be simplified compared to the method in which the processor 2 performs polling during DMA processing, and the processing efficiency of the processor 2 can be improved.

(Third embodiment)
Next, an embodiment of the information processing apparatus of the present invention will be described.
In this embodiment, when the processor 2 inquires about the operation state of the DMA controller 4 in the first embodiment, the state notification register 7 is read, whereas when the processor 102 to be described later inquires about the operation state of the DMA controller 104. This is different from the first embodiment in that predetermined information (detection condition information described later) is written in the condition setting register 107.

  FIG. 7 is a block diagram showing a schematic configuration of the information processing apparatus 100 according to the third embodiment of the present invention. As shown in FIG. 7, the information processing apparatus 100 includes a processor 102, a RAM 103, a DMA controller 104 having a condition setting register 107, and a clock control unit 105. Each unit excluding the clock control unit 105 includes a data bus 106. Are connected to each other so as to be able to exchange data.

  Among these, the processor 102 reads various programs and data such as a basic control program and application program stored in a storage device (not shown), and develops and executes these various programs and data in a work area provided in the RAM 103. And various processes, such as control of each part with which the information processing apparatus 100 is provided, and arithmetic processing, are performed.

  Further, as shown in the flowchart of FIG. 8, the processor 102 sets a parameter (DMA parameter) for DMA processing (step S301), and outputs a DMA start command for causing the DMA controller 104 to start DMA processing (step S301). S302). Then, a condition setting register write request signal and detection condition information (write data) are output to the DMA controller 104 in order to acquire the DMA operation state. Thereafter, when a write completion signal indicating completion of writing to the condition setting register 107 is output from the DMA controller 104, writing to the condition setting register 107 is completed (step S303).

Here, the detection condition information will be described.
In the present embodiment, a plurality of channels are prepared in the DMA controller 104, and DMA in a plurality of hardware modules can be executed. Therefore, when a plurality of DMA transfers are performed at the same time, as shown in FIG. 9, a plurality of state machines indicating the DMA operation state are operating. The detection condition information indicates a detection condition when detecting an operation state in the plurality of state machines SM0 to SMn.

FIG. 10 is a diagram illustrating a data configuration example of detection condition information.
In FIG. 10, the detection condition information is composed of 8-bit data, and the lower 4 bits are “1” indicating the specified state of each of the four state machines SM0 to SM3 (DMA transfer state confirmation target). In addition, bit data (hereinafter referred to as “confirmation target setting data”) indicating bit data “0” indicating that it is not a confirmation target of DMA transfer, and the upper 4 bits are detection conditions set for bit data of lower 4 bits ( Bit data (hereinafter, “condition setting data”) indicating “1000” indicating that an AND condition is set for bit data and “1100” indicating that an OR condition is set for bit data Say.)

  That is, when the condition setting data (upper 4 bits) of the detection condition information is “1000”, the state machine (hardware module) in which “1” is set in the confirmation target setting data (lower 4 bits). If not all of the DMA transfer is in progress, a write completion signal is output from the DMA controller 104. When the upper 4 bits of the detection condition information is “1100”, any of the state machines (hardware modules) in which “1” is set in the confirmation target setting data (lower 4 bits) is DMA-transferred. If not, the DMA controller 104 outputs a write completion signal.

Returning to FIG. 7, the RAM 103 forms a work area for developing the various programs when the processor 102 executes the above-described processing according to the various programs, and expands data related to the various processes executed by the processor 102. A memory area is formed.
The DMA controller 104 starts DMA processing when a DMA start command is output from the processor 102.

  The DMA controller 104 also includes a status notification unit 104a that manages the status of DMA processing. Then, when the condition setting register write request signal and the detection condition information are input from the processor 102 to the DMA controller 104, the state notification unit 104a, based on the detection condition information, determines the state of DMA processing, that is, in a plurality of DMA channels. Determine the operating state of the state machine. Then, when the operation state of each state machine meets the detection condition indicated by the detection condition information, the state notification unit 104a outputs a write completion signal indicating that writing to the condition setting register 107 is completed to the processor 102. If the operating state of each state machine does not match the detection condition indicated in the detection condition information, the WAIT signal is output to the clock control unit 105.

FIG. 11 is a block diagram illustrating a schematic configuration of the state notification unit 104a.
In FIG. 11, the state notification unit 104a includes the above-described condition setting register 107, an AND circuit 104b, an OR circuit 104c, and a selection circuit 104d.
A signal (busy_ready signal) indicating whether or not DMA transfer is being performed is input to the AND circuit 104b from each state machine in the hardware module performing the DMA transfer. The busy_ready signal is “1” when the DMA transfer is in progress, and is “0” when the DMA transfer is not in progress. The bit data (confirmation target setting data) stored in the condition setting register 107 is input to the AND circuit 104b.

  Then, the AND circuit 104b confirms the operation state of the hardware module (state machine) in which “1” is set in the confirmation target setting data based on the busy_ready signal of each hardware module. When all of the busy_ready signals input from the hardware module in which “1” is set are “0” (indicating that none of them are in DMA transfer), the detection condition in the AND circuit 104b is satisfied. An AND condition result (in this case, “1”) indicating this is output to the selection circuit 104d. On the other hand, when all of the busy_ready signals input from the hardware module in which “1” is set in the confirmation target setting data are not “0” (indicating that one of them is performing DMA transfer), AND An AND condition result (here, “0”) indicating that the detection condition in the circuit 104b is not satisfied is output to the selection circuit 104d.

Similarly to the AND circuit 104b, the OR circuit 104c receives a signal (busy_ready signal) indicating whether or not the DMA transfer is being performed from each state machine in the hardware module performing the DMA transfer. The bit data (confirmation target setting data) stored in the condition setting register 107 is input to the OR circuit 104c.
Then, the OR circuit 104c confirms the operation state of the hardware module (state machine) in which “1” is set in the confirmation target setting data based on the busy_ready signal of each hardware module. When one of the busy_ready signals input from the hardware module in which “1” is set is “0” (indicating that one of them is not performing DMA transfer), the detection condition in the OR circuit 104c is An OR condition result (here, “1”) indicating that the condition is satisfied is output to the selection circuit 104d. On the other hand, when all the busy_ready signals input from the hardware module in which “1” is set in the confirmation target setting data are “1” (indicating that all are DMA transfers), OR An OR condition result (here, “0”) indicating that the detection condition in the circuit 104c is not satisfied is output to the selection circuit 104d.

The condition setting data in the detection condition information input from the processor 102 is input to the selection circuit 104d.
The selection circuit 104d receives the AND condition result from the AND circuit 104b and the OR condition result from the OR circuit 104c.
Then, the selection circuit 104d selects either the AND condition result or the OR condition result according to the detection condition (that is, the AND condition or the OR condition) indicated by the condition setting data, and outputs the selection result to the processor 102. To do. This selection result is a write completion signal when the result is an AND condition result or an OR condition result indicating that the condition is satisfied, and when the selection result is an AND condition result or an OR condition result indicating that the condition is not satisfied. Becomes a WAIT signal for the processor 102.

Returning to FIG. 7, the clock control unit 105 determines whether or not the WAIT signal is output from the DMA controller 104. If the WAIT signal is not output, the clock control unit 105 supplies the clock signal to the processor 102, and the WAIT signal is If it is output, supply of the clock signal is stopped.
Next, the operation of the information processing apparatus 100 of this embodiment will be described in detail.

First, it is assumed that a DMA request signal for requesting the DMA controller 104 to start DMA is output in cycle “2” as shown in FIG.
Then, in cycle “3”, the DMA controller 104 outputs a signal notifying that DMA transfer processing is in progress. As shown in FIG. 8, the processor 102 executes predetermined processing. First, in step S301, the DMA parameter is set. In step S302, the DMA start command is sent to the DMA controller 104 as shown in FIG. 12B. Is output. Then, in cycle “3”, as shown in FIG. 12C, the operation state of the DMA controller is set to “operating”, and the DMA processing is started by the DMA controller 104.

In addition, while the DMA processing is continued, through cycles “4” to “6”, in cycle “7”, as shown in FIG. 12D, the processor 102 requests the DMA controller 104 to write a condition setting register. A signal and write data (detection condition information) are output.
Then, in cycle “8”, as shown in FIG. 12F, a high-level WAIT signal is output from the DMA controller 104 to the clock controller 105, and in cycle “9”, as shown in FIG. Further, the operation clock signal supplied to the processor 102 by the clock control unit 105 is stopped.

Further, it is assumed that the cycle “10” to “13” is followed by the cycle “14”, the operation state of the DMA controller 104 is set to the low level as shown in FIG.
Then, in cycle “15”, the DMA controller 104 outputs a write completion signal indicating that the DMA processing is not in progress to the processor 102, and the WAIT signal is stopped. Also, the supply of the clock signal from the clock control unit 105 to the processor 102 is resumed, and when the write completion signal is output, the condition setting register write request signal is stopped, and the processing of the processor 102 is resumed at cycle “16”. The

  As described above, according to the information processing apparatus 100 of the present embodiment, even when the DMA processing is executed by the DMA controller 104, until the processor 102 inquires about the operation state of the DMA controller 104, that is, the condition setting register write request signal is transmitted. Until the output, the processor 102 can continue the processing so far, and when the condition setting register write request signal is output from the processor 102, the supply of the clock signal to the processor 102 is stopped. The power consumption by the processor 102 can be reduced while preventing the processing efficiency by the processor 102 from being lowered.

In addition, since the supply of the clock signal is stopped until the DMA processing is completed, it is possible to prevent the inquiry about the operation state of the DMA controller 104 from being performed many times during the execution of the DMA processing. Power consumption can be further reduced.
Further, when the processor 102 outputs a condition setting register write request signal, detection condition information indicating a detection condition for the operation state of the DMA controller 104 is output as write data. Therefore, when there are a plurality of DMA channels, it is possible to inquire about the operation state of the DMA controller 104 by setting complicated conditions in those channels. In addition to the above effects, efficient execution control of software is performed. It becomes possible. Specifically, since the number of condition judgments in the program can be reduced, the execution speed can be improved. Further, unnecessary power consumption can be reduced as compared with the conventional method in which the condition determination is repeated for polling the DMA controller. Further, since the process for detecting various conditions in the DMA controller 104 can be executed only by outputting a write request signal and detection condition information (write data), it is easy to create a program for realizing such a process. It becomes.

  In the present embodiment, the DMA controller 104 has been described as determining the AND condition or the OR condition indicated in the detection condition information. However, a condition (such as an XOR condition) other than the AND condition and the OR condition may be set. In addition, the DMA controller 104 may determine only one of the AND condition and the OR condition. When only one fixed condition is determined in the DMA controller 104, the upper 4 bits of the detection condition information are not necessary, the write data by the processor 102 is reduced, and the configuration of the status notification unit 104a is For example, it can be simplified as shown in FIGS.

  In this embodiment, when the condition setting register write request signal is output by the processor 102, the supply of the clock to the processor 102 is continuously stopped until the write completion signal is output from the DMA controller 104. As described in the second embodiment, the supply of the clock signal may be temporarily resumed each time a predetermined length of data is DMA transferred.

  In the above embodiment, the processor 102 constitutes the processor in the claims, the DMA controller 104 constitutes the function unit, the clock control unit 105 constitutes the suppression unit, and the condition setting register 107 serves as the detection condition storage unit. Configure.

It is a schematic block diagram which shows 1st Embodiment of the processor control circuit of this invention. It is a flowchart of the arithmetic processing performed with the processor of FIG. 2 is a timing chart illustrating an operation of the information processing apparatus in FIG. 1. It is a schematic block diagram which shows 2nd Embodiment of the processor control circuit of this invention. It is a flowchart of the arithmetic processing performed with the processor of FIG. 5 is a timing chart showing the operation of the information processing apparatus of FIG. It is a block diagram which shows schematic structure of the information processing apparatus 100 in the 3rd Embodiment of this invention. It is a flowchart of the arithmetic processing performed with the processor of FIG. It is a flowchart which shows the state in which the state machine which shows the operation state of DMA is operating in multiple numbers. It is a figure which shows the data structural example of detection condition information. It is a block diagram which shows schematic structure of the status notification part 104a. It is a timing chart which shows operation | movement of the information processing apparatus of FIG. It is a figure which shows the structural example of the status notification part 104a in the case of determining only AND conditions. It is a figure which shows the structural example of the status notification part 104a in the case of determining only OR condition. It is a flowchart of the arithmetic processing performed with the conventional processor.

Explanation of symbols

  1, 100 is an information processing device, 2, 102 is a processor, 3, 103 is RAM, 4, 104 is a DMA controller, 5, 105 is a clock controller, 6, 106 is a data bus, 7 is a status notification register, 107 is Condition setting register, 8 is transfer data length setting section

Claims (15)

A functional unit capable of executing a predetermined process without using a processor;
An inquiry detection unit that detects whether or not the processor has inquired about an operating state of the functional unit after the execution of the predetermined process is started in the functional unit;
An end detection unit for detecting the end of the predetermined process in the function unit;
When the execution of the predetermined process is started in the function unit, the operation state of the processor is maintained, and further, when the inquiry detection unit detects that the processor has inquired about the operation state of the function unit, A suppression unit that suppresses an operation related to an inquiry about an operation state of the function unit by the processor until the end detection unit detects the end of the predetermined process in the function unit;
A processor control circuit comprising: When it is detected by the inquiry detection unit that the processor has inquired about the operating state of the function unit , the suppression unit until the end detection unit detects the end of the predetermined process in the function unit. The processor control circuit according to claim 1, wherein an operation related to an inquiry about an operation state of the functional unit by the processor is delayed. When it is detected by the inquiry detection unit that the processor has inquired about the operating state of the function unit , the suppression unit until the end detection unit detects the end of the predetermined process in the function unit. 2. The processor control circuit according to claim 1, wherein the frequency of the clock signal supplied to the processor is lowered. When it is detected by the inquiry detection unit that the processor has inquired about the operating state of the function unit , the suppression unit until the end detection unit detects the end of the predetermined process in the function unit. 2. The processor control circuit according to claim 1, wherein the supply of the clock signal to the processor is stopped.   5. The processor control circuit according to claim 4, wherein when the supply of the clock signal is stopped, the suppression unit can temporarily resume the supply of the clock signal. 6.   The functional unit is capable of executing DMA processing, and when the supply of the clock signal is stopped, the suppression unit temporarily supplies the clock signal every time a predetermined length of data is DMA transferred. The processor control circuit according to claim 5, wherein the processor control circuit restarts. The function unit includes a state storage unit that stores execution state information indicating an operation state of the function unit ;
When the inquiry detection unit detects that the processor has inquired about the operation state of the function unit by outputting a read signal of the execution state information, the end detection unit ends the predetermined process in the function unit Is output to the processor in response to the detection of the execution state information, thereby notifying the processor that the predetermined processing in the functional unit has been completed. A status notification section;
Processor control circuit according to any one of claims 1 to 6, characterized in that it comprises a. A processor for executing predetermined arithmetic processing;
A functional unit capable of executing predetermined processing without going through the processor;
An inquiry detection unit that detects whether or not the processor has inquired about an operating state of the functional unit after the execution of the predetermined process is started in the functional unit;
An end detection unit for detecting the end of the predetermined process in the function unit;
When the execution of the predetermined process is started in the function unit, the operation state of the processor is maintained, and further, when the inquiry detection unit detects that the processor has inquired about the operation state of the function unit, A suppression unit that suppresses an operation related to an inquiry about an operation state of the function unit by the processor until the end detection unit detects the end of the predetermined process in the function unit;
An information processing apparatus comprising: When it is detected by the inquiry detection unit that the processor has inquired about the operating state of the function unit , the suppression unit until the end detection unit detects the end of the predetermined process in the function unit. The information processing apparatus according to claim 8, wherein an operation related to an inquiry about an operation state of the functional unit by a processor is delayed. When it is detected by the inquiry detection unit that the processor has inquired about the operating state of the function unit , the suppression unit until the end detection unit detects the end of the predetermined process in the function unit. The information processing apparatus according to claim 8, wherein a frequency of a clock signal supplied to the processor is lowered. When it is detected by the inquiry detection unit that the processor has inquired about the operating state of the function unit , the suppression unit until the end detection unit detects the end of the predetermined process in the function unit. The information processing apparatus according to claim 8, wherein supply of a clock signal to the processor is stopped.   The information processing apparatus according to claim 11, wherein when the supply of the clock signal is stopped, the suppression unit can temporarily resume the supply of the clock signal.   The functional unit is capable of executing DMA processing, and when the supply of the clock signal is stopped, the suppression unit temporarily supplies the clock signal every time a predetermined length of data is DMA transferred. The information processing apparatus according to claim 12, wherein the information processing apparatus is restarted. The functional unit includes a detection condition storage unit that stores detection condition information indicating a detection condition related to an operation state of the functional unit,
The processor makes an inquiry about the operation state by outputting a write signal to the detection condition storage unit of the detection condition information in which a predetermined condition in detection of the operation state is set,
The functional unit outputs a write completion signal indicating that writing of the detection condition information is completed to the processor when the operation state satisfies a condition indicated by the detection condition information. The information processing apparatus according to claim 8, further comprising a state notification unit that notifies the processor that a predetermined process has been completed. The functional unit can execute a plurality of the predetermined processes,
The processor outputs a write signal to the detection condition storage unit of the detection condition information including information specifying each of the predetermined processes and a detection condition of an operation state set during a plurality of the predetermined processes. To inquire about the operating state,
The state notification unit in the functional unit, if the operating condition matches the detection condition between predetermined process shown in the detected condition information, by outputting the write completion signal to the processor, predetermined in the functional unit The information processing apparatus according to claim 14, wherein the processor is notified that the process has been completed .

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