JP2006331248A - Data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accelerate the speed of a function for executing data transfer to a FIFO circuit. <P>SOLUTION: A data transfer device has: the FIFO circuit for providing buffering for data transfer; an external storage circuit storing a control program including a FIFO control function for controlling the FIFO circuit; and a microcomputer having an internal storage circuit accelerated in the speed of operation more than the external storage circuit, and a processing circuit for executing the FIFO control function. If the size of the control program is larger than the capacity of the internal storage circuit and the size of the FIFO control function is smaller than the capacity of the internal storage circuit, the FIFO control function is copied into the internal storage circuit and the FIFO control function is executed from the internal storage circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a data transfer apparatus having a FIFO circuit for data transfer and a microcomputer that executes a FIFO control function for controlling the buffering operation of the FIFO circuit.

The above-described data transfer device is provided in a development kit for developing an electronic device such as a mobile phone, and is used to transfer data between the development kit and the electronic device. Yes. The data transfer device has an external RAM. At the initial operation of the development kit, the control program including the FIFO control function is loaded from the ROM stored in advance into the external RAM, and the microcomputer stores the program in the external RAM. The buffering operation of the FIFO circuit is controlled by executing the FIFO control function. In relation to speeding up of the FIFO circuit, Patent Document 1 discloses a configuration in which a FIFO circuit is connected to an internal bus of a semiconductor memory (RAM) to speed up data transfer.

JP 7-192454 A (paragraph 0013 and FIG. 1)

However, when the FIFO control function is executed from the external RAM as in the prior art, the operation speed of the external RAM is slower than that of the microcomputer, so that there is a problem that the data transfer through the FIFO circuit cannot be accelerated.

Therefore, an object of the present invention is to provide a data transfer apparatus that can realize a high-speed operation of a FIFO control function without changing the configuration of the data transfer apparatus.

In order to solve the above problems, in the data transfer device of the present invention, the FIFO circuit that performs buffering for data transfer, the external storage circuit, and the operation speed of the FIFO circuit are faster than those of the external storage circuit. An internal storage circuit for storing a FIFO control function to perform and the FIFO
And a microcomputer having a processing circuit for executing the O control function.

According to this configuration, the FIFO control function is stored in the internal storage circuit that is faster in operation speed than the external storage circuit and is executed.
Compared with the case where the FO control function is stored and executed, the FIFO circuit can be read and written at high speed.

Further, in the data transfer apparatus of the present invention, the FIFO that performs buffering for data transfer
An O circuit, an external storage circuit that stores a control program including a FIFO control function for controlling the FIFO circuit, an internal storage circuit that operates faster than the external storage circuit, and the FIFO
A microcomputer having a processing circuit for executing a control function, wherein the microcomputer has a capacity of the control program larger than that of the internal storage circuit and smaller than that of the internal storage circuit. The FIFO control function is stored in the internal storage circuit, and the FIFO control function is executed from the internal storage circuit.

According to this configuration, the FIFO control function is stored in the internal storage circuit that is faster in operation speed than the external storage circuit and is executed.
Compared with the case where the FO control function is stored and executed, the FIFO circuit can be read and written at high speed.

Further, in the data transfer apparatus of the present invention, the FIFO that performs buffering for data transfer
An O circuit, an external storage circuit that stores a control program including a FIFO control function for controlling the FIFO circuit, an internal storage circuit that operates faster than the external storage circuit, and the FIFO
A microcomputer having a processing circuit for executing a control function and a dynamic memory management mechanism for managing the internal storage circuit, and the microcomputer starts the data transfer at the start of the data transfer. A search process for searching for an empty area in the internal storage circuit necessary for storing the FIFO control function by a management mechanism; a copy process for copying and storing the FIFO control function from the external storage circuit to the internal storage circuit; Execution processing for executing the FIFO control function stored in the internal storage circuit, and at the end of the data transfer, the dynamic memory management mechanism removes the FIFO from the internal storage circuit.
A release process for releasing the area storing the control function is executed.

According to this configuration, since the FIFO control function is executed from the internal storage circuit during the data transfer period, the FIFO circuit can be read and written at a high speed. Further, during the period other than the data transfer, the internal storage circuit Since the memory area of the FIFO control function is released from the memory area, the processing circuit can use all areas of the internal memory circuit.

In the data transfer device of the present invention, the data transfer device further detects an interface unit for mounting the external device that is the target of the data transfer, and detects that the external device is mounted or removed from the interface unit. An attachment / detachment detection unit, and the microcomputer sets, as the start time, a time point when the attachment / detachment detection unit detects that the external device is attached to the interface unit, and the search process, the copy process, The execution process is executed, and the release process is executed with the point in time when the attachment / detachment detection unit detects that the external device is detached from the interface unit as the end point.

In the data transfer device according to the present invention, the FIFO control function includes a FIFO read function for reading data from the FIFO circuit and a FIFO write function for writing data to the FIFO circuit. When reading data from the FIFO circuit, the computer searches the free space in the internal storage circuit necessary for storing the FIFO read function by the dynamic memory management mechanism, and stores the FIFO read function in the external storage. The FI copied from the circuit to the internal storage circuit and stored in the internal storage circuit
When executing a FO read function and writing data into the FIFO circuit, the dynamic memory management mechanism searches for a free area in the internal storage circuit necessary for storing the FIFO write function, and the FIFO write A copy function is copied from the external storage circuit to the internal storage circuit and stored, and the FIFO write function stored in the internal storage circuit is executed.

According to this configuration, even when there is no area for storing the entire FIFO control function in the internal storage circuit, if the area for storing the FIFO read function or the FIFO write function can be secured, the FIFO circuit can be read and written at high speed. become.

  Embodiments of a data transfer apparatus according to the present invention will be described below with reference to the drawings.

(First embodiment)
First, a schematic configuration of the data transfer apparatus according to the first embodiment will be described with reference to FIG.

<Configuration of data transfer device>
FIG. 1 is a block diagram showing the configuration of the data transfer apparatus according to the first embodiment. As shown in FIG. 1, the data transfer apparatus 1 includes at least a microcomputer 100, an external ROM 210 that stores a control program 230 that controls data transfer, an external RAM 220 that is an external storage circuit, and an external device (not shown). The controller 300 is configured to control an interface 320 that is an interface unit for connecting to the external bus 200, and the external bus 200 connects these components to each other.

Further, the microcomputer 100 includes at least a CPU 110 that is a processing circuit for executing control of each device and a program, and a built-in RAM 120 that is an internal storage circuit, and is connected to each other via an internal bus 130. Further, the controller 300 includes at least a FIFO circuit 310 that performs buffering for data transfer. The control program 230 includes a FIFO control function 240 that controls the FIFO circuit 310.

<Configuration of external RAM and internal RAM>
Next, the configuration of the external RAM 220 and the built-in RAM 120 will be described with reference to FIG.
FIG. 2 is a block diagram showing the configuration of the external RAM and the built-in RAM.

The control program 230 stored in the external ROM 210 is stored in the microcomputer 1.
00 is loaded into the external RAM 220. The built-in RAM 120 includes a use area 121 that is already used for other processing of the CPU 110 of the microcomputer 100 and a free area 122 that is not used. As shown in FIG. 2, the capacity of the control program 230 is larger than the free area 122 of the internal RAM 120. F included in the control program 230
The IFO control function 240 is smaller than the free area 122 of the internal RAM 120.

The external RAM 220 on the data transfer device 1 operates based on a basic basic clock signal. On the other hand, the microcomputer 100 operates with a high-speed clock signal obtained by speeding up the basic clock signal with a phase synchronization circuit (not shown). For example, when the frequency of the basic clock signal is 33 MHz, the high-speed clock signal is generated by the phase synchronization circuit, for example, 2
When the output is doubled, it is set to 66 MHz.

Next, processing of the data transfer apparatus according to the first embodiment will be described with reference to FIG. FIG. 3 is a flowchart for explaining processing of the data transfer apparatus according to the first embodiment.

First, in step S200, the data transfer apparatus 1 is turned on, and step S210 is performed.
Then, the control program 230 stored in the external ROM 210 is loaded into the external RAM 220 via the external bus 200.

Next, in step S220, the control program 230 loaded in the external RAM 220.
From this, the FIFO control function 240 is copied to the free area 122 of the internal RAM 120.

Next, in step S230, the CPU 110 of the microcomputer 100 causes the built-in R
The FIFO control function 240 on the AM 120 is executed, the buffering operation of the FIFO circuit 310 is controlled, and data is transferred to and from an external device connected to the interface 320.

  According to the embodiment described above, the following effects can be obtained.

In this embodiment, the microcomputer 100 operates based on the high-speed clock signal, and the built-in RAM 120 that operates the FIFO control function 240 also operates based on the high-speed clock signal. The buffering operation of the FIFO circuit 310 can be speeded up as compared with the case where 240 is executed.

(Second Embodiment)
Next, a second embodiment of the data transfer apparatus according to the present invention will be described. In the first embodiment, the data transfer apparatus 1 stores the control program 230 in the external RAM 220 when the power is turned on.
The method of copying the FIFO control function 240 to the built-in RAM 120 has been described, but the built-in RAM 120 may already be used for other processing of the CPU 110, and the free space for copying the FIFO control function 240 122 may not be secured.

In the present embodiment, a method will be described in which it is detected that an external device is attached to the interface 320, and a free area 122 of the built-in RAM 120 is dynamically secured and data transfer is performed while the external device is attached.

A data transfer apparatus according to the second embodiment will be described with reference to FIG. FIG. 4 is a block diagram showing the configuration of the data transfer apparatus according to the second embodiment. Here, only the difference from FIG. 1 will be described.

The microcomputer 100 further includes a dynamic memory management mechanism 140 that manages the free area 122 of the internal RAM 120, dynamically allocates a necessary area, and releases the used area when it becomes unnecessary. In addition, the controller 300 includes an interface 32.
0 further includes an attachment / detachment detection unit 330 that detects that an external device is attached or detached and transmits a detection signal indicating that the external device is attached or detached to the microcomputer 100 via the external bus 200.

Next, processing of the data transfer apparatus according to the second embodiment will be described with reference to FIG. FIG. 5 is a flowchart for explaining processing of the data transfer apparatus according to the third embodiment.

First, in step S300, the data transfer apparatus 1 is turned on, and step S310 is executed.
Then, the control program 230 stored in the external ROM 210 is loaded into the external RAM 220 via the external bus 200.

Next, in step S320, the address information of the available free area 122 of the internal RAM 120 is registered in the dynamic memory management mechanism 140.

Next, in step S330, the microcomputer 100 monitors an attachment detection signal indicating that an external device is attached to the interface 320 from the attachment / detachment detection unit 330. If the attachment detection signal is received, the microcomputer 100 proceeds to step S340. If not received, the mounting detection signal is continuously monitored.

Next, in step S340, the dynamic memory management mechanism 140 can use the available built-in RA.
A search process is performed to search for a free area 122 of M120.

Next, in step S350, the built-in RA that can be used by the dynamic memory management mechanism 140 is displayed.
It is determined whether or not the free space 122 of M120 has been secured.
If the process proceeds to 360 and cannot be secured, the process proceeds to step S400.

Next, in step S360, the control program 230 loaded in the external RAM 220.
Then, a copy process for copying the FIFO control function 240 portion to the free area 122 of the internal RAM 120 is performed.

Next, in step S370, the CPU 110 of the microcomputer 100 causes the built-in R
The FIFO control function 240 on the AM 120 is executed, the buffering operation of the FIFO circuit 310 is controlled, and an execution process for transferring data to and from an external device connected to the interface 320 is performed.

Next, in step S380, the microcomputer 100 monitors the detachment detection signal indicating that the external device is detached from the interface 320 from the detachment detection unit 330. If the detachment detection signal is received, the microcomputer 100 proceeds to step S390. If not received, the monitoring of the separation detection signal is continued.

Next, in step S390, the dynamic memory management mechanism 140 performs release processing for releasing the used area of the internal RAM 120.

On the other hand, in step S400, a built-in RAM for copying the FIFO control function 240
Since 120 free areas 122 could not be secured, the FIFO control function 240 on the external RAM 220 is executed, the buffering operation of the FIFO circuit 310 is controlled, and data is exchanged with an external device connected to the interface 320. Perform the transfer.

  According to the embodiment described above, the following effects can be obtained.

In the present embodiment, when the microcomputer 100 detects that an external device is attached to the interface 320 by the attachment / detachment detection unit 330, the dynamic memory management mechanism 140.
Thus, the free area 122 of the internal RAM 120 is secured, and when the external device is detached from the interface, the dynamic memory management mechanism 140 releases the area used by the internal RAM 120. According to this configuration, if the external device is not attached to the data transfer apparatus 1, the microcomputer 100 can use the entire area of the internal RAM 120, and the internal RAM 120 is free only during the period in which the external device is attached. Since the area 122 can be used, the buffering operation of the FIFO circuit 310 can be speeded up as compared with the case where the FIFO control function 240 is executed on the external RAM 220. Since the memory area of the FIFO control function is released from the memory circuit, the processing circuit can use all areas of the internal memory circuit.

As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, In the range which does not deviate from the meaning of this invention, it can be implemented with various forms. Hereinafter, a modification will be described.

(Modification 1) A first modification of the data transfer apparatus according to the present invention will be described. In the second embodiment, the free area 122 in which the FIFO control function 240 can be copied to the built-in RAM 120.
However, if it cannot be ensured, it is proposed as follows so that it can be implemented even with a smaller free space 122.

The FIFO control function 240 is a FIFO for reading data from the FIFO circuit 310.
It is divided into a read function and a FIFO write function for writing data to the FIFO circuit.
When the empty area 122 that can copy the FIFO control function 240 cannot be secured in the built-in RAM 120, or when data is read from the FIFO circuit 310, the F
When it is determined whether there is a free area 122 necessary for the IFO read function and data is written to the FIFO circuit 310, the free area 122 necessary for the FIFO write function is stored in the internal RAM 120.
Is determined (corresponding to S340 and S350 in FIG. 5). When the free area 122 can be secured, the process proceeds to step S360 in FIG.

(Modification 2) A second modification of the data transfer apparatus according to the present invention will be described. In the second embodiment, the case where the attachment / detachment detection unit 330 is used has been described, but the attachment / detachment detection unit 330 may not necessarily be provided. In this case, the microcomputer 100 includes the controller 3
When a data transfer request is received from 00, the dynamic memory management mechanism 140 uses the built-in RAM 1
20 free areas are secured, and when the data transfer request from the controller 300 is interrupted for a predetermined time, the dynamic memory management mechanism 140 may release the used area of the internal RAM 120.

1 is a block diagram showing a configuration of a data transfer apparatus according to a first embodiment of the present invention. The block diagram which shows the structure of external RAM and built-in RAM. 6 is a flowchart for explaining processing of the data transfer apparatus according to the first embodiment. The block diagram which shows the structure of the data transfer apparatus which concerns on 2nd Embodiment of this invention. The flowchart explaining the process of the data transfer apparatus which concerns on 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Data transfer apparatus, 100 ... Microcomputer, 110 ... CPU, 120 ... Built-in RAM, 130 ... Internal bus, 140 ... Dynamic memory management mechanism, 200 ... External bus, 210 ...
External ROM 220 ... External RAM 230 ... Control program 240 ... FIFO control function 300 ... Controller 310 ... FIFO circuit 320 ... Interface 330 ...
Attachment / detachment detection unit.

Claims (5)

A FIFO circuit for buffering for data transfer;
An external storage circuit;
A microcomputer having an operation speed higher than that of the external storage circuit, an internal storage circuit for storing a FIFO control function for controlling the FIFO circuit, and a processing circuit for executing the FIFO control function;
including,
A data transfer device. A FIFO circuit for buffering for data transfer;
An external storage circuit for storing a control program including a FIFO control function for controlling the FIFO circuit;
A microcomputer having an internal storage circuit whose operation speed is higher than that of the external storage circuit and a processing circuit for executing the FIFO control function;
Have
The microcomputer is
The FIFO control function having a capacity of the control program larger than the capacity of the internal storage circuit and smaller than the capacity of the internal storage circuit is stored in the internal storage circuit, and the F
Executing an IFO control function from the internal storage circuit;
A data transfer device. A FIFO circuit for buffering for data transfer;
An external storage circuit for storing a control program including a FIFO control function for controlling the FIFO circuit;
A microcomputer having an internal storage circuit whose operation speed is faster than that of the external storage circuit, a processing circuit for executing the FIFO control function, and a dynamic memory management mechanism for managing the internal storage circuit;
Have
The microcomputer is
A search process for searching for a free area in the internal storage circuit necessary for storing the FIFO control function by the dynamic memory management mechanism at a start time of starting the data transfer;
A copy process for copying and storing an IFO control function from the external storage circuit to the internal storage circuit, and an execution process for executing the FIFO control function stored in the internal storage circuit;
At the end of the data transfer, the dynamic memory management mechanism executes a release process for releasing the area storing the FIFO control function from the internal storage circuit.
A data transfer device. The data transfer device according to claim 3, wherein
The data transfer device further includes an interface unit for mounting the external device that is the target of the data transfer, and an attachment / detachment detection unit that detects that the external device is mounted or detached from the interface unit,
The microcomputer is
The point in time when the attachment / detachment detection unit detects that the external device is attached to the interface unit is set as the start point, and the search process, the copy process, and the execution process are executed.
The time when the attachment / detachment detection unit detects that the external device has been detached from the interface unit is set as the end time, and the release process is executed.
A data transfer device. The data transfer device according to claim 3, wherein
The FIFO control function includes a FIFO read function for reading data from the FIFO circuit and a FIFO write function for writing data to the FIFO circuit.
The microcomputer is
When reading data from the FIFO circuit, the dynamic memory management mechanism causes the F
A search is made for a free area of the internal storage circuit necessary for storing the IFO read function, and the FIFO
O read function is copied from the external storage circuit to the internal storage circuit and stored, and the FIFO read function stored in the internal storage circuit is executed,
When writing data to the FIFO circuit, the dynamic memory management mechanism causes the FI
Searching for a free area of the internal storage circuit necessary for storing the FO write function, and the FIFO
Copying and storing a write function from the external storage circuit to the internal storage circuit, and executing the FIFO write function stored in the internal storage circuit;
A data transfer device.

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