JP5231496B2 - Information processing apparatus and suspend / resume method thereof - Google Patents

Description

  The present invention relates to an information processing apparatus and a suspend / resume method thereof, and more particularly to shortening of a suspend / resume process.

  In recent years, in electronic devices that require a power saving state such as personal computers and mobile phones, the storage capacity of the main storage device tends to increase. As the storage capacity increases, the processing time increases when data in the main storage device is sequentially saved in an external storage device such as a hard disk during suspension, and it takes time to enter the suspended state. Suspend is an operation that saves the system state information and interrupts the task. Resume is an operation that restores the state information and resumes the task.

  The suspend / resume function of the information processing apparatus is described in Patent Documents 1 to 3, for example. Patent Document 1 describes that the main memory device itself is composed of a nonvolatile memory element as an approach for speeding up the suspend / resume function. That is, by making the main storage device itself non-volatile, processing at the time of suspend / resume (for example, saving to a secondary storage device such as a hard disk) can be largely omitted, so that high speed can be expected. .

  Further, Patent Document 2 has a suspend function for storing the CPU execution state (system state a1) in the main memory and then stopping the operation of the CPU while continuing to supply power to the main memory. It describes that the CPU execution state (system state a2) is saved in the HDD at the time of transition.

  Further, in Patent Document 3, the contents in the main storage device are managed in blocks, and a block having information that is in use and exists only on the main storage device among the blocks of the main storage device at the time of power-off request. And the block information found only in the main storage device is saved in the nonvolatile storage device.

JP 2004-362426 A JP 2008-033436 A Japanese Patent Laid-Open No. 06-131082

  In the information processing apparatus, it is necessary to save the information in the main storage device to a hard disk or the like that can be retained even when the power is turned off during suspension. At that time, the information in the main storage device is read as needed, and the read data is written to the hard disk or the like. However, as the capacity of the main storage device increases as described above, the data read / write processing time increases. The increase causes an increase in the suspend / resume processing time.

  However, the method of Patent Document 1 is expensive because the main memory device itself is composed of nonvolatile memory elements. Patent Document 2 only describes saving the execution state of the CPU to the HDD at the time of transition to the suspended state, and does not particularly describe shortening the processing time at the time of suspension.

  Further, Patent Document 3 describes that the contents of the main storage device are divided into a plurality of blocks and managed, and when the power-off request is made, the block information retrieved as being only in the main storage device is saved in the nonvolatile storage device. However, the block information that does not need to be saved becomes invalid. At that time, the information on the block that was not saved in the non-volatile storage device among the information that existed on the main storage device at the time of the power-off request was transferred from the peripheral device when the reference was requested for the first time when the power was turned on again. It is described that the data is transferred to a predetermined block of the storage device. Therefore, in the method of Patent Document 3, it is necessary to separately manage blocks having information existing on the main storage device and blocks of information that are not so, and complicated management is necessary.

  An object of the present invention is to provide an information processing apparatus and its suspend / resume method capable of shortening the suspend / resume processing time even when the capacity of the main storage device increases.

  An information processing apparatus according to the present invention is provided corresponding to a CPU that controls each unit in the apparatus, a plurality of main storage devices, and the plurality of main storage devices, and stores data in the main storage devices And a buffer for disconnecting and connecting an address bus and a data bus between the memory devices, the memory device including the plurality of nonvolatile memories, and the main storage device and the nonvolatile memory corresponding thereto Buffer control means for controlling disconnection and connection of the address bus and data bus between the memory devices by the buffer, and the buffer control means controls the buffer during suspend / resume processing to control the main memory device. And an address bus and a data bus between the memory devices each having a nonvolatile memory corresponding thereto , And it performs parallel data transfer between said plurality of main memory and a plurality of non-volatile memory.

  The suspend / resume method according to the present invention includes a CPU that controls each unit in the device, a plurality of main storage devices, and a plurality of main storage devices, respectively. Provided between memory devices including a plurality of nonvolatile memories for storing, the main memory device and the corresponding nonvolatile memory, and for disconnecting and connecting an address bus and a data bus between the memory devices And a buffer control means for controlling disconnection and connection of an address bus and a data bus between the memory devices by the buffer, the suspend / resume method of the information processing apparatus, wherein the buffer control means includes a suspend / resume method. The main memory and its corresponding non-volatile memory by controlling the buffer during resume processing On cutting the address bus and data bus between the memory device comprising, and performing in parallel the data transfer between said plurality of main memory and a plurality of non-volatile memory.

  According to the present invention, a plurality of main storage devices and a plurality of non-volatile memories corresponding thereto are provided, and an address bus and a data bus between the main storage device and a memory device composed of the corresponding non-volatile memories are provided during suspend / resume processing. By disconnecting, data transfer between a plurality of main storage devices and a plurality of nonvolatile memories can be performed in parallel, and the suspend / resume processing time can be shortened even when the capacity of the main storage device increases. It becomes possible.

1 is a block diagram showing a first embodiment of an information processing apparatus according to the present invention.

  Next, modes for carrying out the invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a first embodiment of an information processing apparatus according to the present invention. In the figure, reference numeral 1 denotes a CPU that controls each unit in the information processing apparatus, 2 denotes a suspend / resume control apparatus, and 3 denotes a power supply control unit that controls a power supply (not shown). Reference numeral 6 denotes a main storage device, and reference numeral 5 denotes a data evacuation nonvolatile memory for storing data in the main storage device.

  A plurality of main storage devices 6 are provided from the main storage device 1 to the main storage device n, and a nonvolatile memory 5 is provided corresponding to each of the plurality of main storage devices 6, and a plurality of nonvolatile memories 1 to n are provided. . 7 is an address bus and 8 is a data bus. The CPU 1, the suspend / resume control device 2, the nonvolatile memory 5, and the main storage device 6 are connected by an address bus 7 and a data bus 8.

  A buffer 4 is arranged between the memory device composed of the main storage device 5 and the corresponding nonvolatile memory 6. The buffer 4 connects and disconnects the address bus 7 and the data bus 8 between the main memory device 5 and the corresponding memory device composed of the nonvolatile memory 6 under the control of the suspend / resume control device 2. A plurality of buffers 4 are provided from the buffer 1 to the buffer n, and are arranged between the memory devices. The main storage device 6 is composed of a plurality of LSIs, and one set of buffer 4 and nonvolatile memory 5 is arranged in each LSI (main storage device).

  During normal startup, processing, and termination, the suspend / resume control device 2 controls connection of the address bus 7 and data bus 8 to each buffer 4. Therefore, the address bus 7 and the data bus 8 between the memory devices are in a connected state, and each unit in the apparatus operates under the control of the CPU 1.

  When the suspend / resume control device 2 receives the suspend event, the nonvolatile memory 5 becomes ready to store the data in the main storage device 6 and then the address bus 7 and the data bus between the memory devices for each buffer 4. Control is performed to cut 8. Therefore, each main storage device 6 is disconnected from the address bus 7 and the data bus 8 and is no longer controlled by the CPU 1.

  Thereafter, the suspend / resume control device 2 simultaneously controls the address bus 7 and the like for all the main storage devices 6 to start data transfer from all the main storage devices 6 to the corresponding nonvolatile memories 5 respectively. . Since this operation simultaneously processes a plurality of main storage devices 6, the processing time required for data transfer is the data transfer time of one main storage device 6 even if the processing time is composed of a plurality of main storage devices 6. Will be the same.

  When the data transfer to the main storage device 6 is completed, the suspend / resume control device 2 finishes the control to each main storage device 6, and the address bus 7 and the data bus 8 between the memory devices are connected to each buffer 4. Perform connection control. Thereafter, the CPU 1 is notified of the completion of data saving. Also, if necessary, a power OFF instruction is issued to the power control unit 3, and the system shifts to a power saving mode.

  On the other hand, when the suspend / resume control device 2 receives a resume event, the suspend / resume control device 2 controls each buffer 4 to disconnect the address bus 7 and the data bus 8 between the memory devices. Thereafter, read control is performed on all the non-volatile memories 5, and at the same time, data write control of the non-volatile memory 5 is performed on each main storage device 6 corresponding to each non-volatile memory 5.

  As a result, data can be copied from all the nonvolatile memories 5 to all the main storage devices 6 at the same time and restored to the state of the memory before suspension. The suspend / resume control device 2 controls connection of the address bus 7 and the data bus 8 between the memory devices to each buffer 4 when the data restoration of each nonvolatile memory 5 is completed, and controls the CPU 1. Notify that data restoration is complete.

  In the present embodiment, a plurality of main storage devices are arranged, and a plurality of nonvolatile memories for saving data for storing data of the main storage devices are provided corresponding to the respective main storage devices. Further, a buffer 4 for disconnecting and connecting the address bus 7 and the data bus 8 is disposed between the main memory device and the memory device composed of the corresponding non-volatile memory. By disconnecting the address bus and data bus between the memory devices during the suspend process, the data in each main storage device can be copied to each nonvolatile memory in parallel. Since the copy time is only the processing time of one main storage device, the suspend processing time can be shortened even when the capacity of the main storage device is increased.

  Further, since the buffer 4 is also controlled during the resume process to disconnect the address bus 7 and the data bus 8 between the memory devices, data is concurrently transmitted from each nonvolatile memory 5 to each main storage device 6 corresponding thereto. Can be written back, and the processing time for resuming can be shortened.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. The basic configuration of the present embodiment is the same as that shown in FIG. 1, but the CPU 1 controls the buffer 4, the main storage device 6, and the nonvolatile memory 5 as described above without using the suspend / resume control device 2. The data transfer between the memory devices is performed in parallel.

  In this embodiment, since the CPU 1 controls the address bus and the like as compared with the first embodiment, the CPU 1 cannot execute processes other than the data saving process in parallel with the data saving process. As in the case of the first embodiment, the data saving process can be performed on a plurality of main storage devices 6 in parallel. The same process is performed for the resume process. Therefore, the suspend processing time and the resume processing time can be shortened as in the first embodiment.

  The information processing apparatus of the above embodiment can be realized by hardware, but can also be realized by reading and executing a program for causing a computer to function as the information processing system from a computer-readable recording medium. it can. In addition, the suspend / resume method of the above embodiment can be realized by hardware, but can also be realized by reading and executing a program for causing a computer to execute the method from a computer-readable recording medium. .

  Moreover, although a part or all of the said embodiment can be described also as the following additional remarks, it is not restricted to the following.

(Supplementary note 1) CPU for controlling each part in the apparatus;
A plurality of main storage devices;
A plurality of nonvolatile memories provided corresponding to the plurality of main storage devices, respectively, for storing data in the main storage devices;
A buffer provided between a memory device including the main storage device and the nonvolatile memory corresponding thereto, and a buffer for disconnecting and connecting an address bus and a data bus between the memory devices;
Buffer control means for controlling disconnection and connection of an address bus and a data bus between the memory devices by the buffer;
The buffer control means controls the buffer during suspend / resume processing to disconnect an address bus and a data bus between the memory devices including the main storage device and a nonvolatile memory corresponding thereto, and then An information processing apparatus that performs data transfer between a main storage device and a plurality of nonvolatile memories in parallel.

  (Supplementary Note 2) When the data transfer from the plurality of main storage devices to the plurality of nonvolatile memories is completed, the buffer control means includes the main storage device and the corresponding nonvolatile memory. The information processing apparatus according to appendix 1, wherein an address bus and a data bus are connected between devices.

  (Supplementary Note 3) When the data transfer from the plurality of nonvolatile memories to the plurality of main storage devices is completed, the buffer control unit includes the main storage device and the corresponding nonvolatile memory. The information processing apparatus according to appendix 1, wherein an address bus and a data bus are connected between devices.

  (Supplementary note 4) Any one of Supplementary notes 1 to 3, wherein the CPU controls connection of an address bus and a data bus between the memory devices instead of the buffer control means during the suspend / resume process. The information processing apparatus according to item.

(Additional remark 5) CPU which controls each part in an apparatus,
A plurality of main storage devices;
A plurality of nonvolatile memories provided corresponding to the plurality of main storage devices, respectively, for storing data in the main storage devices;
A buffer provided between a memory device including the main storage device and the nonvolatile memory corresponding thereto, and a buffer for disconnecting and connecting an address bus and a data bus between the memory devices;
A suspend / resume method for an information processing apparatus, comprising buffer control means for controlling disconnection and connection of an address bus and a data bus between the memory devices by the buffer,
The buffer control means controls the buffer during suspend / resume processing to disconnect an address bus and a data bus between the memory devices including the main storage device and a corresponding nonvolatile memory, and then A suspend / resume method, wherein data transfer between a main storage device and a plurality of nonvolatile memories is performed in parallel.

  (Supplementary Note 6) When the data transfer from the plurality of main storage devices to the plurality of nonvolatile memories is completed, the buffer control means includes the main storage device and the corresponding nonvolatile memory. 6. The suspend / resume method according to appendix 5, wherein an address bus and a data bus are connected between devices.

  (Supplementary note 7) When the data transfer from the plurality of nonvolatile memories to the plurality of main storage devices is completed, the buffer control means includes the main storage device and the corresponding nonvolatile memory. 6. The suspend / resume method according to appendix 5, wherein an address bus and a data bus are connected between devices.

  (Supplementary note 8) Any one of Supplementary notes 5 to 7, wherein the CPU controls connection between an address bus and a data bus between the memory devices instead of the buffer control means during the suspend / resume process. Suspend / resume method described in 1.

(Additional remark 9) CPU which controls each part in an apparatus,
A plurality of main storage devices;
A plurality of nonvolatile memories provided corresponding to the plurality of main storage devices, respectively, for storing data in the main storage devices;
A program of an information processing apparatus having
The information processing apparatus;
A buffer provided between a memory device including the main storage device and the nonvolatile memory corresponding thereto, and a buffer for disconnecting and connecting an address bus and a data bus between the memory devices;
Buffer control means for controlling disconnection and connection of an address bus and a data bus between the memory devices by the buffer;
The buffer control means controls the buffer during suspend / resume processing to disconnect the address bus and data bus between the memory devices including the main storage device and the corresponding nonvolatile memory, and then Means for causing data transfer between the storage device and the plurality of nonvolatile memories in parallel;
Program to make it function.

  (Supplementary Note 10) When the data transfer from the plurality of main storage devices to the plurality of nonvolatile memories is completed, the buffer control unit includes the main storage device and the corresponding nonvolatile memory. The program according to appendix 9, wherein an address bus and a data bus are connected between devices.

  (Supplementary Note 11) When the data transfer from the plurality of nonvolatile memories to the plurality of main storage devices is completed, the buffer control means includes the main storage device and the corresponding nonvolatile memory. The program according to appendix 9, wherein an address bus and a data bus are connected between devices.

  (Supplementary note 12) Any one of Supplementary notes 9 to 11, wherein the CPU performs connection control between an address bus and a data bus between the memory devices instead of the buffer control means during the suspend / resume process. The program described in the section.

  The present invention can be suitably used for a computer, a mobile phone, a communication device, and the like that require a power saving state.

1 CPU
2 Suspend / resume control device 3 Power supply control device 4 Buffer 5 Non-volatile memory 6 Main storage device 7 Address bus 8 Data bus

Claims (9)

A CPU for controlling each part in the apparatus;
A plurality of main storage devices;
A plurality of nonvolatile memories provided corresponding to the plurality of main storage devices, respectively, for storing data in the main storage devices;
A buffer provided between a memory device including the main storage device and the nonvolatile memory corresponding thereto, and a buffer for disconnecting and connecting an address bus and a data bus between the memory devices;
Buffer control means for controlling disconnection and connection of an address bus and a data bus between the memory devices by the buffer;
The buffer control means controls the buffer during suspend / resume processing to disconnect an address bus and a data bus between the memory devices including the main storage device and a nonvolatile memory corresponding thereto, and then An information processing apparatus that performs data transfer between a main storage device and a plurality of nonvolatile memories in parallel.   When the data transfer from the plurality of main storage devices to the plurality of nonvolatile memories is completed, the buffer control unit includes an address between the memory devices including the main storage device and the corresponding nonvolatile memory. The information processing apparatus according to claim 1, wherein a bus and a data bus are connected.   When the data transfer from the plurality of nonvolatile memories to the plurality of main storage devices is completed, the buffer control unit includes an address between the memory devices including the main storage device and the corresponding nonvolatile memory. The information processing apparatus according to claim 1, wherein a bus and a data bus are connected.   4. The CPU according to claim 1, wherein the CPU performs connection control of an address bus and a data bus between the memory devices instead of the buffer control unit during the suspend / resume process. 5. Information processing device. A CPU for controlling each part in the apparatus;
A plurality of main storage devices;
A plurality of nonvolatile memories provided corresponding to the plurality of main storage devices, respectively, for storing data in the main storage devices;
A buffer provided between a memory device including the main storage device and the nonvolatile memory corresponding thereto, and a buffer for disconnecting and connecting an address bus and a data bus between the memory devices;
A suspend / resume method for an information processing apparatus, comprising buffer control means for controlling disconnection and connection of an address bus and a data bus between the memory devices by the buffer,
The buffer control means controls the buffer during suspend / resume processing to disconnect an address bus and a data bus between the memory devices including the main storage device and a corresponding nonvolatile memory, and then A suspend / resume method, wherein data transfer between a main storage device and a plurality of nonvolatile memories is performed in parallel.   When the data transfer from the plurality of main storage devices to the plurality of nonvolatile memories is completed, the buffer control unit includes an address between the memory devices including the main storage device and the corresponding nonvolatile memory. 6. The suspend / resume method according to claim 5, wherein a bus and a data bus are connected.   When the data transfer from the plurality of nonvolatile memories to the plurality of main storage devices is completed, the buffer control unit includes an address between the memory devices including the main storage device and the corresponding nonvolatile memory. 6. The suspend / resume method according to claim 5, wherein a bus and a data bus are connected.   8. The CPU according to claim 5, wherein the CPU performs connection control between an address bus and a data bus between the memory devices instead of the buffer control means during the suspend / resume process. Suspend / resume method. A CPU for controlling each part in the apparatus;
A plurality of main storage devices;
A plurality of nonvolatile memories provided corresponding to the plurality of main storage devices, respectively, for storing data in the main storage devices;
A program of an information processing apparatus having
The information processing apparatus;
A buffer provided between a memory device including the main storage device and the nonvolatile memory corresponding thereto, and a buffer for disconnecting and connecting an address bus and a data bus between the memory devices;
Buffer control means for controlling disconnection and connection of an address bus and a data bus between the memory devices by the buffer;
The buffer control means controls the buffer during suspend / resume processing to disconnect the address bus and data bus between the memory devices including the main storage device and the corresponding nonvolatile memory, and then Means for causing data transfer between the storage device and the plurality of nonvolatile memories in parallel;
Program to make it function.