CN102521175A - SDRAM (synchronous dynamic random access memory) controller and operating method for same - Google Patents
SDRAM (synchronous dynamic random access memory) controller and operating method for same Download PDFInfo
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Abstract
The invention discloses an SDRAM (synchronous dynamic random access memory) controller and an operating method for the same. The controller comprises a read-write signal receiving and processing module, a data caching module and an SDRAM read-write time sequence implementation module. The SDRAM read-write time sequence implementation module comprises a read time sequence state machine and a write time sequence state machine; the data caching module comprises a temporary storage area, an address register, a write identifier register and a valid data register; the read-write signal receiving and processing module is connected with an external bus; and the SDRAM read-write time sequence implementation module is connected with a dynamic random access memory. The controller can be mounted on a processor not supporting burst read-write to realize high-speed read-write functions of the SDRAM. As read-write operation for the SDRAM in practical application frequently arms at adjacent areas and some processors do not support burst read-write operation of data, the controller in the form of an IP (internet protocol) core can be applied to many occasions, and system efficiency can be effectively improved.
Description
Technical field
The present invention relates to a kind of sdram controller and method of work thereof, belong to embedded, SOC technical field.
Background technology
SDRAM has burst mode as the stochastic and dynamic storer, and very high read-write speed can be provided.But in some application, CPU does not possess the burst read-write capability, so if adopt common sdram controller, read-write speed then can receive very big restriction.Burst mode is meant after an address being carried out addressing and operation completion, needn't carry out addressing more again, can carry out read-write operation to one section continuous address, has so just saved a lot of time, has very high read-write speed.
Summary of the invention
To above technical deficiency; The invention provides a kind of reasonable in design, move sdram controller efficiently; This controller is through adding the metadata cache part; Used the burst read WriteMode of SDRAM to greatest extent, with the read-write speed of lifting stochastic and dynamic storer (SDRAM) and the work efficiency of place system thereof.
The present invention also provides the method for work of above-mentioned sdram controller.
Technical scheme of the present invention is following:
A kind of sdram controller comprises read-write reception and processing module, data cache module and SDRAM read-write sequence realization module; Said SDRAM read-write sequence realization module comprises to be read sequential state machine and writes sequential state machine; Described data cache module comprises staging area, address register, writes marker register and the effective register of data; Said read-write reception links to each other with external bus with processing module, and said SDRAM read-write sequence realizes that module links to each other with stochastic and dynamic storer (SDRAM).
Said read-write receives and links to each other with external bus through data line, address wire, reading writing signal line and acknowledge signal line with processing module; Said SDRAM read-write sequence realizes that module links to each other with said stochastic and dynamic storer (SDRAM) with the data active line through data line, address wire, row route selection, column selection line, piece route selection, clock/clock enable line, write signal line.
Most importantly staging area in the data cache module, the width of staging area is consistent with highway width, and length is consistent with the burst mode length of setting; Also comprise address register in the data cache module, write marker register and the effective register of data etc.There are two effects the staging area: when needs are initiated a read operation, with a succession of data storage that reads in this zone; In the time need writing new data, then that new data is temporary to this regional correspondence position to a certain address in the address register corresponding address section.The corresponding address in SDRAM of data in the address register stores staging area.Writing in the marker register storage staging area data of which position need be written among the SDRAM and upgrade.Whether the data that the effective register of data is used for identifying in the staging area are effective.
The SDRAM read-write sequence is realized module with generating the concrete sequential to the SDRAM practical operation, mainly reads (reading sequential state machine) by burst and two state machines of single writing (writing sequential state machine) are formed.When needs are initiated once new read operation, read sequential state machine and will start working, the data storage that reads in the staging area of data cache module, and is upgraded address register wherein.Writing sequential state machine mainly works under two kinds of situation: when whole sdram controller is in idle condition; Sdram controller reading of data cache module write marker register; If the data updated of needs is arranged; This writes sequential state machine will get into duty, write data among the SDRAM, will write the correspondence position zero in the marker register simultaneously; Another kind of situation is that this writes sequential state machine entering mode of operation, writes data among the SDRAM when the data address that will write during not in the corresponding scope of address register.
The method of work of above-mentioned sdram controller, method step is following:
Be in idle condition when 1) sdram controller is initial, read-write receives with processing module to detect whether receive the read-write requests signal from bus:
If a. receive read request, then carry out step 2) from bus;
If b. receive the request of writing, then carry out step 3) from bus;
Whether if c. do not receive the request that reads or writes from bus, then detecting writing of data cache module has data need write SDRAM to upgrade in the marker register:
If c1. there are data need write SDRAM, then notify the SDRAM read-write sequence to realize that module initiates write operation, will data updated be written to the corresponding address of SDRAM;
If c2. there are not data need write SDRAM, then sdram controller gets into idle condition again, and read-write receives with processing module and proceeds cycle detection;
2) read-write receives with the processing module detection and receives the read request from bus:
D. whether the read-write reception is in the address register corresponding address section of data cache module with the address that processing module detects request msg in the read request:
D1. if the address of request msg in address register corresponding address section, then whether effective: as, then to carry out steps d 4 if corresponding data is effective through the corresponding data that detects the effective register identification of data in the data cache module; If corresponding data is invalid, then wait for effective until corresponding data; Described corresponding data is meant, in the staging area with the corresponding data in the address of request msg;
D2. the address of request msg then empties the effective register of data not in address register corresponding address section; Detection writes marker register: if there are data to need to upgrade; Then notify the SDRAM read-write sequence to realize module initiation write operation; Need data updated to be written among the SDRAM all, will write the zero clearing of marker register correspondence position writing fashionable needs, carry out steps d 3 after accomplishing upgrading; If do not have data to upgrade then directly carry out steps d 3.
D3. notify the SDRAM read-write sequence to realize module initiation read operation; Through burst mode the data read in the address corresponding address section of bus request data is got in the staging area; The start address of initiating read operation is the address of bus request data, after getting access to first group of data (promptly ask read data), carries out steps d 4; At this moment the SDRAM read-write sequence realizes that module continues to read residue continuation address corresponding data, with steps d 4 parallel operations;
D4. read-write receives with processing module the data that read is put on the address wire of bus, then bus is sent answer signal, and last read-write receives with processing module and gets into idle condition;
3) read-write receives with processing module and detects the request of writing from bus of receiving:
E. read-write receives with processing module and detects in the address register corresponding address the section whether address of writing request msg in the request be in the metadata cache part:
E1. the address of writing request msg in the request is in address register corresponding address section: the correspondence position data in the staging area are upgraded, and write the position set of the corresponding address in the marker register, carry out step e3;
E2. the address of writing request msg in the request is not in address register corresponding address section: notice SDRAM read-write sequence is realized module initiation write operation, and required data updated is directly write among the SDRAM, carries out step e3;
E3. read-write receives with processing module and sends answer signal to bus, and last sdram controller gets into idle condition.
Often the present invention is directed in practical application and need carry out the adjacent area read-write operation SDRAM; Wherein read-write receives with processing module and receives the read-write that the processing bus sends, and determines whether needing to initiate once new read-write operation through the address that will operate; The SDRAM read-write sequence realizes that module is used for producing the read-write mutual with SDRAM (row choosing, column selection, data, address, clock etc.), and this part adopts the burst read mode of SDRAM, to realize the fast processing function of mass data; Data cache module one is that the continuous data that reads is carried out buffer memory, can fast return when guaranteeing the neighbor address data are read, and the 2nd, the data that write are stored temporarily, guarantee the ageing of data.
The invention has the beneficial effects as follows:
The present invention can be mounted to the high speed read-write capability of realizing SDRAM on the processor of the read-write of not supporting to happen suddenly.Maximally utilise the burst mode that SDRAM itself supports, improved the efficient of read-write, in the processor system of read-write of not supporting to happen suddenly, strengthened the performance of system effectively.
Description of drawings
Fig. 1 is a module frame chart of the present invention;
Fig. 2 is the process flow diagram of the method for the invention.
Embodiment
1-2 is described further the present invention below in conjunction with accompanying drawing, but is not limited thereto.
As shown in Figure 1, a kind of sdram controller comprises read-write reception and processing module, data cache module and SDRAM read-write sequence realization module; Said SDRAM read-write sequence realization module comprises to be read sequential state machine and writes sequential state machine; Described data cache module comprises staging area, address register, writes marker register and the effective register of data; Said read-write reception links to each other with external bus with processing module, and said SDRAM read-write sequence realizes that module links to each other with stochastic and dynamic storer (SDRAM).Said read-write receives and links to each other with external bus through data line, address wire, reading writing signal line and acknowledge signal line with processing module; Said SDRAM read-write sequence realizes that module links to each other with said stochastic and dynamic storer (SDRAM) with the data active line through data line, address wire, row route selection, column selection line, piece route selection, clock/clock enable line, write signal line.
As shown in Figure 2, like the method for work of embodiment 1 said a kind of sdram controller, method step is following:
Be in idle condition when 1) sdram controller is initial, read-write receives with processing module to detect whether receive the read-write requests signal from bus:
If a. receive read request, then carry out step 2) from bus;
If b. receive the request of writing, then carry out step 3) from bus;
Whether if c. do not receive the request that reads or writes from bus, then detecting writing of data cache module has data need write SDRAM to upgrade in the marker register:
If c1. there are data need write SDRAM, then notify the SDRAM read-write sequence to realize that module initiates write operation, will data updated be written to the corresponding address of SDRAM;
If c2. there are not data need write SDRAM, then sdram controller gets into idle condition again, and read-write receives with processing module and proceeds cycle detection;
2) read-write receives with the processing module detection and receives the read request from bus:
D. whether the read-write reception is in the address register corresponding address section of data cache module with the address that processing module detects request msg in the read request:
D1. if the address of request msg in address register corresponding address section, then whether effective: as, then to carry out steps d 4 if corresponding data is effective through the corresponding data that detects the effective register identification of data in the data cache module; If corresponding data is invalid, then wait for effective until corresponding data; Described corresponding data is meant, in the staging area with the corresponding data in the address of request msg;
D2. the address of request msg then empties the effective register of data not in address register corresponding address section; Detection writes marker register: if there are data to need to upgrade; Then notify the SDRAM read-write sequence to realize module initiation write operation; Need data updated to be written among the SDRAM all, will write the zero clearing of marker register correspondence position writing fashionable needs, carry out steps d 3 after accomplishing upgrading; If do not have data to upgrade then directly carry out steps d 3.
D3. notify the SDRAM read-write sequence to realize module initiation read operation; Through burst mode the data read in the address corresponding address section of bus request data is got in the staging area; The start address of initiating read operation is the address of bus request data, after getting access to first group of data (promptly ask read data), carries out steps d 4; At this moment the SDRAM read-write sequence realizes that module continues to read residue continuation address corresponding data, with steps d 4 parallel operations;
D4. read-write receives with processing module the data that read is put on the address wire of bus, then bus is sent answer signal, and last read-write receives with processing module and gets into idle condition;
3) read-write receives with processing module and detects the request of writing from bus of receiving:
E. read-write receives with processing module and detects in the address register corresponding address the section whether address of writing request msg in the request be in the metadata cache part:
E1. the address of writing request msg in the request is in address register corresponding address section: the correspondence position data in the staging area are upgraded, and write the position set of the corresponding address in the marker register, carry out step e3;
E2. the address of writing request msg in the request is not in address register corresponding address section: notice SDRAM read-write sequence is realized module initiation write operation, and required data updated is directly write among the SDRAM, carries out step e3;
E3. read-write receives with processing module and sends answer signal to bus, and last sdram controller gets into idle condition.
Claims (3)
1. a sdram controller is characterized in that, said controller comprises read-write reception and processing module, data cache module and SDRAM read-write sequence realization module; Said SDRAM read-write sequence realization module comprises to be read sequential state machine and writes sequential state machine; Described data cache module comprises staging area, address register, writes marker register and the effective register of data; Said read-write reception links to each other with external bus with processing module, and said SDRAM read-write sequence realizes that module links to each other with SDRAM.
2. sdram controller according to claim 1 is characterized in that, said read-write receives and links to each other with external bus through data line, address wire, reading writing signal line and acknowledge signal line with processing module; Said SDRAM read-write sequence realizes that module links to each other with SDRAM with the data active line through data line, address wire, row route selection, column selection line, piece route selection, clock/clock enable line, write signal line.
3. the method for work of sdram controller according to claim 1 is characterized in that method step is following:
Be in idle condition when 1) sdram controller is initial, read-write receives with processing module to detect whether receive the read-write requests signal from bus:
If a. receive read request, then carry out step 2) from bus;
If b. receive the request of writing, then carry out step 3) from bus;
Whether if c. do not receive the request that reads or writes from bus, then detecting writing of data cache module has data need write SDRAM to upgrade in the marker register:
If c1. there are data need write SDRAM, then notify the SDRAM read-write sequence to realize that module initiates write operation, will data updated be written to the corresponding address of SDRAM;
If c2. there are not data need write SDRAM, then sdram controller gets into idle condition again, and read-write receives with processing module and proceeds cycle detection;
2) read-write receives with the processing module detection and receives the read request from bus:
D. whether the read-write reception is in the address register corresponding address section of data cache module with the address that processing module detects request msg in the read request:
D1. if the address of request msg in address register corresponding address section, then whether effective: as, then to carry out steps d 4 if corresponding data is effective through the corresponding data that detects the effective register identification of data in the data cache module; If corresponding data is invalid, then wait for effective until corresponding data; Described corresponding data is meant, in the staging area with the corresponding data in the address of request msg;
D2. the address of request msg then empties the effective register of data not in address register corresponding address section; Detection writes marker register: if there are data to need to upgrade; Then notify the SDRAM read-write sequence to realize module initiation write operation; Need data updated to be written among the SDRAM all, will write the zero clearing of marker register correspondence position writing fashionable needs, carry out steps d 3 after accomplishing upgrading; If do not have data to upgrade then directly carry out steps d 3;
D3. notify the SDRAM read-write sequence to realize module initiation read operation; Through burst mode the data read in the address corresponding address section of bus request data is got in the staging area; The start address of initiating read operation is the address of bus request data, after getting access to first group of data (promptly ask read data), carries out steps d 4; At this moment the SDRAM read-write sequence realizes that module continues to read residue continuation address corresponding data, with steps d 4 parallel operations;
D4. read-write receives with processing module the data that read is put on the address wire of bus, then bus is sent answer signal, and last read-write receives with processing module and gets into idle condition;
3) read-write receives with processing module and detects the request of writing from bus of receiving:
E. read-write receives with processing module and detects in the address register corresponding address the section whether address of writing request msg in the request be in the metadata cache part:
E1. the address of writing request msg in the request is in address register corresponding address section: the correspondence position data in the staging area are upgraded, and write the position set of the corresponding address in the marker register, carry out step e3;
E2. the address of writing request msg in the request is not in address register corresponding address section: notice SDRAM read-write sequence is realized module initiation write operation, and required data updated is directly write among the SDRAM, carries out step e3;
E3. read-write receives with processing module and sends answer signal to bus, and last sdram controller gets into idle condition.
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| CN105741237A (en) * | 2016-01-26 | 2016-07-06 | 南京铁道职业技术学院 | FPGA (Field Programmable Gate Array) image rollover based hardware realization method |
| CN106845290A (en) * | 2017-01-25 | 2017-06-13 | 天津大学 | For the SRAM controller and its interface circuit of safe storage chip |
| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN112506823A (en) * | 2020-12-11 | 2021-03-16 | 盛立金融软件开发（杭州）有限公司 | FPGA data reading and writing method, device, equipment and readable storage medium |
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| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN112416823B (en) * | 2020-11-15 | 2024-05-03 | 珠海一微半导体股份有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN112506823A (en) * | 2020-12-11 | 2021-03-16 | 盛立金融软件开发（杭州）有限公司 | FPGA data reading and writing method, device, equipment and readable storage medium |
| CN112506823B (en) * | 2020-12-11 | 2023-09-29 | 盛立安元科技(杭州)股份有限公司 | FPGA data reading and writing method, device, equipment and readable storage medium |
| CN113892911A (en) * | 2021-09-28 | 2022-01-07 | 北京清雷科技有限公司 | Device and method for acquiring sleep breathing data |
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