CN102103490B - Method for improving memory efficiency by using stream processing - Google Patents
Method for improving memory efficiency by using stream processing Download PDFInfo
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- CN102103490B CN102103490B CN201010598497.3A CN201010598497A CN102103490B CN 102103490 B CN102103490 B CN 102103490B CN 201010598497 A CN201010598497 A CN 201010598497A CN 102103490 B CN102103490 B CN 102103490B
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Abstract
The invention provides a method for improving the memory efficiency by using stream processing. A parallel processing unit simultaneously sends a request and adds a tag number on a request address; returned data is stored into a corresponding buffer area according to a tag carried by the returned data of a memory in a classified way; and the data is fetched from the corresponding buffer area during use so as to perform data processing. By the method of parallel access and storage by using a production line, the access and storage efficiency is improved effectively.
Description
Technical field
The present invention relates to Memory control technology, specifically relate to a kind of method of utilizing stream treatment to improve memory efficient.
Background technology
Computer software has obtained application more and more widely at society, and on the one hand, computer software is being applied in the middle of increasing field; On the other hand, the user of computer software is also by original professional Computer Engineer, the users of changing present different know-hows into.This just requires 10 computer software functions powerful, but be simple and easy to use, this requirement directly causes computer software scale to become large, complexity increases, make user in the time of appliance computer software, the incidence of software error increases, and wherein, main, modal mistake is exactly the mistake that software causes in the time carrying out internal storage access.This wrong aggregate performance is two kinds of forms: one is read/write address misquotation; Another kind is that access limit is violated license, and these two kinds of mistakes are referred to as illegal memory access.At present, illegal memory access can cause serious bad rear skilful fruit: illegal rdma read, can cause that data referencing makes mistakes, and cause system confusion; Illegally write internal memory, can destroy the normal data in internal memory, when serious, also can cause systemic breakdown
To in the method for internal storage access, be substantially all to carry out data search by sequential access internal memory at present, need more periodicity owing to returning from internal storage access to data, if sequential access can cause system performance low.
Summary of the invention
The object of the invention is to propose a kind of high-level efficiency memory pool access method.
Utilize stream treatment to improve a method for memory efficient, step is as follows:
When A, pipeline system receive new message information, obtain cryptographic hash according to four-tuple by hash algorithm, every level production line access TCP join index table, is widened to 40 by 32 memory access addresses, and most-significant byte is No. tag;
The return data of B, first order pipeline latency TCP join index table, is saved in buffer zone queue, tag position 1; In waiting for first order streamline return data, second level waterline is got access TCP linkage record buffer zone, location from the queue of tag position 1, and streamline can receive new message message simultaneously, carries out memory access for the first time; Connection management system classifies return data to be saved to fifo queue buffer zone according to No. tag;
C, pipeline system, in the time of needs usage data, are taken out data from corresponding buffer zone and are used.
The first optimal technical scheme of the present invention is: connection management adopts the multiple TCP of 3 level production line mode concurrent processing to connect, and the first order is access TCP join index table, and the second level is TCP linkage record buffer zone, and 3rd level is for upgrading above-mentioned two list structures.
The second optimal technical scheme of the present invention is: adopt pipeline system to carry out internal storage access.
The third optimal technical scheme of the present invention is: in carrying out two memory access in the first order and the second level, if stream table address and out of order buffer zone are soon used up, can initiate to upgrade the access of above-mentioned two address pool, tag is respectively 3 and 4, and return data is stored in the queue of corresponding buffer zone.
The present invention adopts the streamline memory access that walks abreast, and saves the data in the queue of corresponding FIFO buffer, has effectively improved memory access efficiency.
Brief description of the drawings
Fig. 1 position building-block of logic of the present invention
Embodiment
1, while receiving new message information, obtain cryptographic hash according to four-tuple by hash algorithm, first order streamline access TCP join index table, is widened to 40 by 32 memory access addresses, and most-significant byte is 1.
2, waiting step 1 return data, is saved in FIFO buffer queue, tag position 1.In waiting for first order streamline return data, second level waterline is got access TCP linkage record buffer zone, location from the queue of tag position 1, and 32 memory access addresses are widened to 40, and most-significant byte is 2.Streamline can receive new message message simultaneously, carries out memory access for the first time.
3, waiting step 2 return datas, are saved in the queue of corresponding buffer zone, are for No. tag 2.
4, in carrying out above-mentioned two memory access, if stream table address and out of order buffer zone are soon used up, can initiate to upgrade the access of above-mentioned two address pool, tag is respectively 3 and 4, and return data is stored in the queue of corresponding buffer zone.
Claims (3)
1. utilize pipeline processes to improve a method for memory efficient, it is characterized in that: step is as follows:
When A, pipeline system receive new message information, obtain cryptographic hash according to four-tuple by hash algorithm, first order streamline access TCP join index table, is widened to 40 by 32 memory access addresses, and most-significant byte is No. tag;
The return data of B, first order pipeline latency TCP join index table, is saved in queue buffer, is for No. tag 1; In waiting for first order streamline return data, second level streamline is got access TCP linkage record buffer zone, location from No. tag queue buffer that is 1, and pipeline system receives new message message simultaneously, carries out memory access for the first time; What connection management system was carried according to return data is saved to respective queue buffer zone by return data No. tag;
C, pipeline system, in the time of needs usage data, are taken out data and are used from respective queue buffer zone;
Connection management system adopts the multiple TCP of 3 level production line mode concurrent processing to connect, and the first order is access TCP join index table, and the second level is access TCP linkage record buffer zone, and the third level is for upgrading the first order and second level list structure.
2. a kind of pipeline processes of utilizing improves the method for memory efficient as claimed in claim 1, it is characterized in that: adopt pipeline system to carry out internal storage access.
3. a kind of pipeline processes of utilizing improves the method for memory efficient as claimed in claim 1, it is characterized in that: in carrying out two memory access in the first order and the second level, if stream table address and out of order buffer zone are soon used up, can initiate to upgrade the access in the first order and address, second-level pond, be respectively 3 and 4 No. tag, return data is stored in corresponding queue buffer.
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| CN201010598497.3A CN102103490B (en) | 2010-12-17 | 2010-12-17 | Method for improving memory efficiency by using stream processing |
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| CN201010598497.3A CN102103490B (en) | 2010-12-17 | 2010-12-17 | Method for improving memory efficiency by using stream processing |
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| CN102103490A CN102103490A (en) | 2011-06-22 |
| CN102103490B true CN102103490B (en) | 2014-07-23 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104793987B (en) * | 2014-01-17 | 2018-08-03 | 中国移动通信集团公司 | A kind of data processing method and device |
| CN113590520A (en) * | 2021-06-15 | 2021-11-02 | 珠海一微半导体股份有限公司 | Control method for automatically writing data into SPI system and SPI system |
| CN114710421B (en) * | 2022-04-14 | 2022-10-25 | 合肥卓讯云网科技有限公司 | Network connection state maintenance device and method based on data prefetching |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949191A (en) * | 2005-10-14 | 2007-04-18 | 杭州中天微系统有限公司 | Method of realizing low power consumption high speed buffer storying and high speed buffer storage thereof |
| CN101650698A (en) * | 2009-08-28 | 2010-02-17 | 曙光信息产业(北京)有限公司 | Method for realizing direct memory access |
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| JP2001216194A (en) * | 2000-01-28 | 2001-08-10 | Sony Corp | Arithmetic processor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949191A (en) * | 2005-10-14 | 2007-04-18 | 杭州中天微系统有限公司 | Method of realizing low power consumption high speed buffer storying and high speed buffer storage thereof |
| CN101650698A (en) * | 2009-08-28 | 2010-02-17 | 曙光信息产业(北京)有限公司 | Method for realizing direct memory access |
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Effective date of registration: 20210820 Address after: Room 111-1, 1st floor, building 23, No.8 yard, Dongbei Wangxi Road, Haidian District, Beijing 100193 Patentee after: Zhongke Tenglong Information Technology Co.,Ltd. Address before: 300384 Xiqing District, Tianjin Huayuan Industrial Zone (outside the ring) 15 1-3, hahihuayu street. Patentee before: DAWNING INFORMATION INDUSTRY Co.,Ltd. |