CN101650698A - Method for realizing direct memory access - Google Patents

Method for realizing direct memory access Download PDF

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Publication number
CN101650698A
CN101650698A CN 200910091835 CN200910091835A CN101650698A CN 101650698 A CN101650698 A CN 101650698A CN 200910091835 CN200910091835 CN 200910091835 CN 200910091835 A CN200910091835 A CN 200910091835A CN 101650698 A CN101650698 A CN 101650698A
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buffer
information
card
determining
packet
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CN 200910091835
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Chinese (zh)
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CN101650698B (en )
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刘兴奎
刘新春
刘朝晖
军 历
李永成
窦晓光
华 聂
贺志强
邵宗有
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曙光信息产业(北京)有限公司
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Abstract

The invention provides a method for realizing direct memory access and an apparatus, wherein the method comprises the following steps: a network card determines threads corresponding to messages according to control information of received messages; the network card determines cache regions corresponding to the threads on a host computer and writes the messages to the cache regions, wherein the cache regions correspond to CPU cores on the host computer. By using the invention, each DMA array corresponds to a CPU core and a software thread, and data processing threads of software are rarely interactive, thereby avoiding access conflicts in technology related and reducing multithread synchronization spending in a mono-array DMA method. Processor resources of the system are used adequately toimprove the transmission bandwidth of DMA data and the processing efficiency.

Description

直接存储器访问的实现方法技术领域本发明涉及通信领域,尤其涉及一种直接存储器访问(Direct Memory Access,简称为DMA)的实现方法。 TECHNICAL FIELD achieve direct memory access, the present invention relates to communication field, particularly to a direct memory access (Direct Memory Access, abbreviated as DMA) implementation. 背景技术DMA是一种高速的数据传输操作,其允许在外部设备和存储器之间直接进行数据的读写,CPU需要在数据传输开始和结束时做一点处理, 而整个读写的过程既不通过CPU也不需要CPU干预,在传输过程中CPU 可以进行其他的工作。 BACKGROUND DMA data transfer is a high-speed operation, which allows the read and write data directly between the external device and as memory, CPU processing that needs to be done at the beginning and end of the data transfer, the entire process neither read by CPU does not require CPU intervention, CPU can perform other tasks during transmission. 也就是说,在DMA操作的大部分时间里,CPU 执行的处理和存储器的输入输出操作处于并行执行状态,因此能够大大提高整个计算机系统的效率。 That is, most of the DMA operation, the input and output operation process executed by the CPU and memory in a parallel execution state, it is possible to greatly improve the efficiency of the whole computer system. 在现有的对称多处理(Symmetrical Multi-Processing,简称为SMP ) 系统中,DMA模式采用单引擎单队列实现,多个处理器共享一份DMA 数据,或者通过内存拷贝方式为每个CPU核单独维护一份数据。 In conventional SMP (Symmetrical Multi-Processing, abbreviated as SMP) systems, single-mode DMA engine to achieve a single queue, a plurality of processors share a DMA data, or by the memory copy mode for each individual CPU core a maintenance data. 这样, 在多个CPU核并行处理一个设备的DMA数据时,多个CPU之间会存在大量的访存沖突,如果要避免这些沖突就需要进行同步操作,导致CPU 资源被大量占用,并且会降低DMA操作的效率。 Thus, when a plurality of CPU cores parallel processing device DMA data, there will be a large number of memory access conflicts between multiple CPU, if such conflicts to be avoided on the need for synchronization, resulting in excessive usage of CPU resources, and reduces the efficiency of the DMA operation. 针对相关技术中由于DMA操作存在访问冲突而导致CPU资源占用以及DMA操作效率低的问题,目前尚未提出有效的解决方案。 Related technology due to the presence of an access violation DMA operations cause the CPU resource consumption and low efficiency for DMA operations, has yet to come up with effective solutions. 发明内容针对相关技术中直接存储器访问操作存在访问沖突而导致CPU资源占用以及DMA操作效率低的问题,本发明的目的在于提供一种直接存储器访问的实现方案,以解决上述问题中的至少之一。 SUMMARY OF THE INVENTION least one of a related art direct memory access operation with an access violation results in a low CPU usage and efficiency of the DMA operation, an object of the present invention is to provide a direct memory access implementation, in order to solve the aforementioned problems . 为实现上述目的,根据本发明,提供了一种直接存储器访问的实现方法。 To achieve the above object, according to the present invention, there is provided a method for implementing a direct memory access. 根据本发明的直接存储器访问的实现方法包括:网卡根据其接收的报文的控制信息确定与报文——对应的线程;网卡确定主机上与线程一一对应的緩存区,并将报文写入緩存区中,其中,每个緩存区与主机上的CPU核--只于应。 The direct memory access method to achieve the present invention comprises: determining the card with its information packet according to the received control message - corresponding to the thread; determining card buffer area correspondence with the thread on the host, and a write packet into the buffer area, wherein, on each of the CPU core to the host buffer - only to be. 其中,网卡根据报文的控制信息确定相应线程的操作包括:网卡根据报文的控制信息进行哈希计算得到哈希值,并根据哈希值确定相应的线程。 Wherein the card according to the determined control information message corresponding thread operations comprising: hash card hash value calculated based on the control information message, and determine the corresponding thread in accordance with the hash value. 并且,在网卡确定与线程——对应的緩存区之后,该方法可进一步包括:网卡根据其本地緩存的緩存区描述符信息确定緩存区的地址和长度,以便之后进行报文的写入。 And, determining the card thread - after the corresponding buffer, the method may further comprise: a card in accordance with its local cache buffer descriptor address and length information for determining the buffer so packets followed by a write. 另外,网卡将报文写入緩存区的处理包括:网卡向主机发送写入请求,并在主机响应于写入请求返回完成信号时完成才艮文的写入。 NIC sends the write request to the host, and completed before the text written in the Burgundy request returns a write completion response to the host signal: Further, the card processing buffer comprises a write packet. 最后,在网卡将报文写入緩存区中之后,该方法还可以包括:网卡在其本地更新本次在緩存区进行写入的结束地址。 Finally, after the card is written the message buffer, the method may further include: updating the card end address of this writing in the buffer zone in its local. 优选地,上述控制信息为以下之一: 一元组信息、二元组信息、三元组信息、四元组信息、五元组信息。 Preferably, the control information is one of the following: One-tuple information, information tuple, triplet information, information quads, quintuple. 根据本发明的另一方面,提供了一种直接存储器访问的实现装置, 该装置可设置于网卡侧。 According to another aspect of the present invention, there is provided a device for implementing a direct memory access, the device may be provided on the card side. 根据本发明的直接存储器访问的实现装置包括:接收模块,用于接收报文;第一确定模块,用于根据接收模块接收的报文的控制信息确定与报文——对应的线程;第二确定模块,用于确定主机上与确定的线程一一对应的緩存区;写入模块,用于将报文写入确定的緩存区中,其中, 每个緩存区与主才几上的CPU核——对应。 Direct memory access apparatus for implementing the present invention includes: a receiving module, configured to receive a message; a first determining module for determining a packet according to the control information receiving module receives the message - the threads; second determining means for determining a thread on the host and the determined buffer area correspondence; writing module configured to write the packet in the determined cache, wherein each cache region and only a few on the main CPU core --correspond. 其中,第一确定模块可用于根据报文的控制信息进行哈希计算得到哈希值,并根据哈希值确定相应的线程。 Wherein the first determining module may be used to obtain a hash value based on hash calculation control information message, and determine the corresponding thread in accordance with the hash value. 该装置可以进一步包括:寄存器,用于存储主机上緩存区的地址和长度,以便写入模块在写入报文时参照。 The apparatus may further comprise: a register configured to store the host address and length of the buffer to write module referred to when writing of the message. 优选地,上述控制信息为以下之一: 一元组信息、二元组信息、三元组信息、四元组信息、五元组信息。 Preferably, the control information is one of the following: One-tuple information, information tuple, triplet information, information quads, quintuple.

借助本发明上述至少一个技术方案,通过多队列单引擎的DMA的方法,使每一个DMA队列对应一个CPU核和一个软件线程,软件各个数据处理线程之间几乎没有交互,避免了相关技术中的访问冲突,降低单队列DMA方法中的多线程同步开销,充分利用系统的处理器资源,提高DMA数据传输带宽和处理效率。 With the present invention, the at least one aspect, by a method of the multi-queue DMA single engine, so that each corresponds to a DMA queue a CPU core and a software thread, the software is little interaction between the various data processing thread, avoiding related art an access violation, a single reduced multithreaded DMA queue process synchronization overhead, fully utilize the processor resources of the system, improve DMA data transfer bandwidth and processing efficiency.

附图说明 BRIEF DESCRIPTION

图; Figure;

图2是根据本发明装置实施例的直接存储器访问的实现装置的框图; 图3是根据本发明装置实施例的直接存储器访问的实现装置对主机进行报文写入的示意图. FIG 2 is a block diagram of apparatus for implementing a direct memory access device according to an embodiment of the invention; FIG. 3 is a schematic diagram of the packet will be written to the host to achieve direct memory access device embodiment of the present invention, apparatus according to embodiments.

具体实施方式 Detailed ways

功能概述 Functional Overview

针对相关技术中由于DMA操作存在访问冲突而导致CPU资源占用以及DMA操作效率低的问题,本发明提出在主冲几上为主机的每个CPU 核配置——对应的緩存区,该緩存区同样与该CPU核的线程——对应, 网卡根据预先配置的线程与报文的对应关系将接收的报文写入相应的緩存区中方,从而避免多个CPU核访问共享的緩存区而造成的访问沖突, 提高了DMA操作的效率。 Because of the related art access violation caused by the DMA operation and low CPU usage efficiency for the DMA operation, the present invention provides a CPU core disposed in each of the main punch to several hosts on - the corresponding buffer, the same buffer the CPU core thread - corresponds to the received message card written in the corresponding buffer in accordance with a correspondence relationship Chinese thread preconfigured with packets, thus avoiding a plurality of CPU cores to access a shared cache access caused conflict, improve the efficiency of the DMA operation.

下面将详细描述本发明的实施例。 Embodiments of the invention will be described in detail below.

方法实施例 Example embodiments

在本实施例中,提供了一种直接存储器访问的实现方法。 In the present embodiment, there is provided a method for implementing a direct memory access. 在实现本发明的方案之前,首先需要对主机的每个CPU核的线程配置相应的緩存区,将每个緩存区的信息记录在网卡上,并且配置每个线程对应的报文哈希值,具体的对应双方可以是哈希值与线程号。 Prior to implementation of the present invention, first requires that each of the host CPU core configuration corresponding thread cache, each cache information is recorded on the card, and the configuration packet corresponds to a hash value for each thread, be specific to the two sides may be a hash value and thread number.

图1是根据本发明方法实施例的直接存储器访问的实现方法的流程图。 1 is a flowchart of a method to achieve direct memory access method according to an embodiment of the present invention. 如图1所示,根据本实施例的直接存储器访问的实现方法包括: As shown in FIG 1, the direct memory access method for implementing the present embodiment includes:

步骤S102,网卡根据其接收的报文的控制信息确定与报文——对应 Step S102, determining the card information control packet according to the received message which - corresponding to

的线程,具体地,网卡可以根据报文的控制信息进行哈希计算,确定哈 Thread, specifically, the card can be hashed based on the control information packet, determine Kazakhstan

希值对应的线程,报文的控制信息可以是一元组信息、二元组信息、三 Xi values ​​corresponding thread, the control information message may be a tuple of information, the information tuples, tris

元组信息、四元组信息、五元组信息; Tuple information, information quads, quintuple information;

步骤S104,网卡确定主机上与线程一~""对应的緩存区,并将报文写 Step S104, the card determines a thread ~ "" corresponding cache on the host, and write the message

入緩存区中,其中,每个緩存区与主机上的CPU核——对应。 Into the buffer area, wherein each of the buffer on the host CPU core - corresponds.

其中,在网卡确定与线程——对应的缓存区之后,网卡需要根据其 Wherein, in determining the NIC thread - after the corresponding buffer, in accordance with need thereof card

本地緩存的緩存区描述符信息确定该緩存区的地址和长度,以便之后进 Local cache buffer descriptor information to determine the address and length of the buffer zone, to then enter

行才艮文的写入。 Rows Gen written text.

在网卡将报文写入緩存区时,网卡可以向主机发送写入请求,并在主机响应于写入请求返回完成信号时完成报文的写入。 When the card write packet buffer, the card may send a write request to the host, and the host write request completion packet returned in response to the write completion signal. 并且,在网卡发送的写入请求较大时,网卡可以将其发送的请求首先分为多个小的请求之后发送给主机。 Further, in the write request sent large card, the card can send a request to the host after the first divided into a plurality of smaller requests.

在网卡将报文写入緩存区中之后,网卡在其本地更新本次在緩存区进行写入的结束地址,以便下一次向该緩存区中写入报文时从该地址继续写入。 After the card is written the message buffer area, its local network card addresses the end of this update is written in the buffer zone, so that the next write buffer to continue to write to the address from the packets.

通过上述处理,使得CPU仅仅访问与其对应的緩存区,避免了相关技术中由于交叉访问带来的访问冲突,节省CPU的资源,能够有效提高DMA操作的效率。 By the above processing, so that the CPU access only its corresponding buffer, in the related art is avoided due to cross-visits to a access violation, save CPU resources, it is possible to improve the efficiency of the DMA operation.

装置实施例 Means Example

在本实施例中,提供了一种直接存储器访问的实现装置,该装置可设置于网卡侧。 In the present embodiment, there is provided a device for implementing a direct memory access, the device may be provided on the card side.

图2是根据本实施例的直接存储器访问的实现装置的框图。 FIG 2 is a block device for implementing a direct memory access according to the present embodiment. 如图2 所示,根据本实施例的直接存储器访问的实现装置包括: 接收模块1,用于接收报文; 2, the direct memory access device for implementing the embodiment according to the present embodiment comprises: a receiving module, configured to receive a packet;

第一确定模块2,连接至接收模块l,用于根据接收模块接收的报文的控制信息确定与报文——对应的线程,优选地,第一确定模块2可以根据报文控制信息进行计算,得到哈希值,并根据预先配置的哈希值与线程号的对应关系确定相应的线程;优选地,报文的控制信息可以是一元组信息、二元组信息、三元组信息、四元组信息、或五元组信息 First determining module 2, connected to the receiving module L, for determining information control packet according to the receiving module receives the message - the threads, preferably, the first determining module 2 according to the control information packet may be calculated obtain the hash value, and determines correspondence relationship between the corresponding thread in accordance with the hash value and the thread preconfigured; preferably, the control information message may be a tuple of information, the information tuples, triplet information, tetrakis tuple information, or quintuple information

第二确定模块3,连接至第一确定模块2,用于确定主机上与由第一确定模块2确定的线程——对应的緩存区; The second determination module 3, module 2 is connected to a first determination for determining the host determined by the first determination module 2 thread - corresponding buffer;

写入模块4,连接至第二确定模块3,用于将报文写入第二确定模块3之前确定的緩存区中,其中,每个緩存区与主机上的CPU核——对应。 Write module 4, connected to the second determination module 3, for the packet write buffer 3 previously determined in the second determination module, wherein each of the buffer on the host CPU core - corresponds.

该装置还可以包括:寄存器5,连接至写入模块4和第二确定模块3, 用于存储主机上緩存区的地址和长度,以便第二确定模块3确定緩存区时、以及写入模块4在写入报文时参照,从而确定需要进行写入的緩存区的位置。 The apparatus may further comprise: a register 5 is connected to the write module 4 and the second determination module 3, the address and length of the storage area of ​​the host cache to a second cache determination module determines when 3, 4 and a writing module when writing the message reference, to determine the required position of the write buffer.

在实际应用中,根据本发明的直接存储器访问的实现装置可以根据图3所示的方式与主机连接,根据本发明的直接存储器访问的实现装置中模块的功能可以进一步划分或合并。 In practical applications, it can be connected to the host shown in FIG. 3 implemented in accordance with a direct memory access apparatus according to the present invention may be further combined or divided according to function realizing means of the direct memory access module of the present invention.

如图3所示,左边为网卡侧,右边为主机侧,在网卡侧主要包括: 数据采集和处理模块,用于接收报文,并且还能够根据报文的控制信息进行哈西计算,得到哈希值;确定模块,用于对来自数据采集和处理模块的哈希值进行一些处理,之后确定对应的线程和缓存区,即,能够实现图2中第一确定模块2和第二确定模块3的确定功能;DMA写引擎, 即图3中的DMA写控制模块,用于进行DMA写请求的组织、队列选择(即,实现緩存区的多选一)、分流算法(即,确定线程)和DMA写描述符的维护(即,更新网卡本地的寄存器中保存的緩存区地址和长度等信息),并且能够在向主机的緩存区进行写入之前向主机的接口控制器发送写入请求,还能够将待发送的请求分包和打包成控制器数据包格式,之后再发送到主机接口控制器;寄存器,用于存储每个緩存区的地址和长 3, the left side of the card, the host on the right side, in the card side including: data acquisition and processing module for receiving packets, and can also be calculated hash control information message, to give Ha Xi value; a determining module, configured to the hash value from the data acquisition and processing module performs some processing, and then determines the corresponding thread cache, i.e., FIG. 2 can be implemented in a first determination and the second determination module 2 module 3 the determination function; DMA write engine, i.e., in FIG. 3 DMA write control module, for performing the tissue, DMA write request queue selection (i.e., selected from a multi-buffer), the split algorithm (i.e., determining the thread) and maintenance DMA write descriptor (i.e., the local storage card update register buffer address and length information, etc.), and can transmit a write request to the host interface controller prior to writing to buffer the host, but also can be a request to be transmitted and the sub-controller packaged into a packet format, then the controller and then sent to the host interface; and a long address register for storing each buffer zone 等信息。 And other information.

在进行写入时,具体的处理过程如下: When writing is performed, the specific process is as follows:

(1 )主机加载与网卡设备绑定的驱动时才艮据CPU核的数量对DMA 写引擎分配緩沖区队列,即,对每个CPU均分配一个——对应的緩存区, 并将緩冲区队列相关描述信息写到网卡寄存器;(2) 网卡在接收IP报文的同时,数据采集和处理模块抽取IP报文包头中四元组(也可以是一元组、二元组、三元组、或五元组),利用Hash算法计算出一个hash值,然后将IP报文和相应的hash值提交给确 (1) bound to the host card loading drive device when the number of CPU cores Gen According to allocate a buffer queue DMA write engine, i.e., one pair for each CPU is assigned - corresponding buffer, and the buffer description queue register writes information card; (2) the card while receiving IP packets, the data acquisition and processing module extracts the IP packet header quads (which may be a tuple, diad, triad, or a group of five yuan), a hash value is calculated using a hash algorithm, and then submitted to the IP packet and the hash value corresponding to the determined

定模块; Given module;

(3) 确定模块根据hash值和软件配置好的分流算法算出报文所属的线程号,然后根据线程号选择相应的DMA緩存区队列的描述符信息 (3) The algorithm for determining the shunt module good hash value and the calculated number of the thread configuration software packet belongs, and then select the appropriate queue based on the thread number of the DMA buffer descriptor information

(队列的地址、长度); (Address queue length);

(4 ) DMA写控制模块将待发送的写入请求打包成PCIe事务层数据包格式发送到PCIe接口(或PCIe接口控制器),当请求的所有数据传输完成时向DMA写控制模块返回完成信号; (. 4) DMA write control module to be packaged into a write request PCIe transaction layer packets transmitted to the PCIe interface format (or PCIe interface controller), when all the data transfer request to the DMA completion of the write control module returns a completion signal ;

(5 ) DMA写控制模块收到请求完成信号之后完成一个IP报文的传输过程,然后更新寄存器中DMA写緩沖区队列的信息,并开始处理下一个IP包的传输。 (. 5) control block DMA write request received transmission completion signal after completion of transmission of a IP packet, and the update information register DMA write queue buffer, and starts processing for the next IP packet.

在上述步骤(5)中,在写入时,主机侧的芯片组会将数据主机侧的主存中的某个緩存区中,主存中包括与多个CPU核core 1、 core 2、...、 core n对应的緩存区1至緩存区n中。 In the above step (5), at the time of writing data will set the main memory chip host side host side in a buffer in main memory comprises a plurality of CPU cores and the core 1, core 2 ,. .., core n 1 corresponds to the buffer area in the buffer n.

在本发明中,DMA写引擎(DMA写控制模块)可以支持64个DMA 写緩冲区队列,并且软件启动的緩冲区队列数目以及各个队列的流量比例可以配置,从而满足当前以及未来几年主流SMP服务器的要求,并且可以很容易地对DMA写引擎进行扩展,使其支持128甚至更多的緩冲区队列。 In the present invention, the write DMA engine (DMA write control module) 64 may support DMA write buffer queue, and the number of queue buffers, and start the software flow rate ratio of the queues can be configured to meet the current and future years mainstream SMP server requirements, and can easily write DMA engine to be extended to support 128 or more buffer queue.

通过上述装置,使得CPU仅仅访问与其对应的緩存区,避免了相关技术中由于交叉访问带来的访问沖突,节省CPU的资源,能够有效提高DMA4喿作的效率。 By the above means, so that the CPU access only its corresponding buffer, in the related art is avoided due to cross-visits to a access violation, save CPU resources, it is possible to improve the efficiency DMA4 Qiao made.

综上所述,本发明针对对称多处理(Symmetrical Multi Processing, 简称为SMP)系统的多CPU多核的架构,提出了多队列单引擎的DMA 方法,每一个DMA队列对应一个CPU核和一个软件线程,软件各个凄史据处理线程之间几乎没有交互,避免了相关技术中的访问沖突和访问资源竟争,降低单队列DMA方法中的多线程同步开销和操作系统协议栈开销,充分利用系统的处理器资源,提高DMA数据传输带宽和处理效率,改善系统性能。 In summary, the present invention is directed to a symmetric multiprocessing (Symmetrical Multi Processing, abbreviated as SMP) system is a multi-core multi-CPU architecture, the method proposed multi-queue DMA single engine, a DMA queue corresponding to each of a CPU core and a software thread , sad history of the various software data between processing threads virtually no interaction, to avoid access conflicts related art competition and access to resources, reduce single-queue DMA method in a multi-thread synchronization overhead and operating system overhead protocol stack, make full use of the system processor resources, improve DMA data transfer bandwidth and processing efficiency, improve system performance.

显然,本领域的技术人员应该明白,上述的本发明的各模块或各步骤可以用通用的计算装置来实现,它们可以集中在单个的计算装置上, 或者分布在多个计算装置所组成的网络上,可选地,它们可以用计算装置可执行的程序代码来实现,从而,可以将它们存储在存储装置中由计算装置来执行,或者将它们分别制作成各个集成电路模块,或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。 Obviously, those skilled in the art will appreciate that the present invention each module or each step may be a general-purpose computing device, they can be integrated in a single computing device or distributed in a network composed of multiple computing devices on, alternatively, they may be implemented by program codes executable by a computing device, so that, to be performed by a computing device stored in a storage device, or they are made into integrated circuit modules, or they a plurality of modules or steps are manufactured into a single integrated circuit module. 这样,本发明不限制于任何特定的硬件和软件结合。 Thus, the present invention is not limited to any particular hardware and software combination.

以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。 The above are only preferred embodiments of the present invention, it is not intended to limit the invention to those skilled in the art, the present invention may have various changes and variations. 凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。 Any modification within the spirit and principle of the present invention, made, equivalent substitutions, improvements, etc., should be included within the scope of the present invention.

Claims (10)

  1. 1.一种直接存储器访问的实现方法,其特征在于,包括: 网卡根据其接收的报文的控制信息确定与所述报文一一对应的线程; 所述网卡确定主机上与所述线程一一对应的缓存区,并将所述报文写入所述缓存区中,其中,每个缓存区与所述主机上的CPU核一一对应。 A method to realize a direct memory access, characterized by comprising: determining thread card correspondence with the packet based on the control information it receives packet; on the host and the card determining a thread a corresponding buffer, and the packet written into the buffer area, wherein each of the buffer and the CPU core of the host on-one correspondence.
  2. 2. 根据权利要求1所述的方法,其特征在于,网卡根据所述报文的控制信息确定相应线程的操作包括:所述网卡根据所述报文的控制信息进行哈希计算得到哈希值,并根据所述哈希值确定相应的线程。 2. The method according to claim 1, characterized in that the card comprises a corresponding thread determining operation based on the control information of the packet: the card hashed to obtain a hash value based on the control information of the packet and determine the corresponding thread in accordance with the hash value.
  3. 3. 根据权利要求1所述的方法,其特征在于,在所述网卡确定与所述线程——对应的緩存区之后,所述方法进一步包括:所述网卡根据其本地緩存的緩存区描述符信息确定所述緩存区的地址和长度,以便之后进行报文的写入。 3. The method according to claim 1, wherein determining the thread of the card - after the corresponding buffer, the method further comprising: said network adapter according to its local cache buffer descriptor the address and length information for determining the buffer so packets followed by a write.
  4. 4. 根据权利要求1所述的方法,其特征在于,所述网卡将所述报文写入所述緩存区的处理包括:所述网卡向所述主机发送写入请求,并在所述主机响应于所述写入请求返回完成信号时完成才艮文的写入。 4. The method according to claim 1, wherein said card comprises processing the buffer writing the message: write request to send the card to the host, and the host in response to the write request packet write is complete before Gen return completion signal.
  5. 5. 根据权利要求1所述的方法,其特征在于,在所述网卡将所述报文写入所述緩存区中之后,所述方法还包括:所述网卡在其本地更新本次在所述緩存区进行写入的结束地址。 After 5. The method according to claim 1, wherein, in the card the packet written into the buffer, the method further comprising: said card in its local views are updated to the present end address of said buffer for writing.
  6. 6. 根据权利要求1至5中任一项所述的方法,其特征在于,所述控制信息为以下之一: 一元组信息、二元组信息、三元组信息、四元组信息、五元组信息。 6. A method according to any one of claims 1 to 5, wherein the control information is one of the following: One tuple information, information tuple, triplet information, information quads, five tuple information.
  7. 7. —种直接存储器访问的实现装置,设置于网卡侧,其特征在于, 所述装置包括:接收模块,用于接收报文;第一确定模块,用于根据所述接收模块接收的所述报文的控制信息确定与所述才艮文——对应的线程;第二确定模块,用于确定主机上与确定的所述线程——对应的緩存区;写入模块,用于将所述报文写入确定的所述緩存区中,其中,每个緩存区与所述主机上的CPU核——对应。 7. - kind of apparatus for implementing a direct memory access, provided in the card side, characterized in that said apparatus comprises: a receiving module, configured to receive a message; a first determining module, for receiving the receiving module according to the determining control information message before the message Burgundy - the threads; a second determining module configured to determine a host and determining the thread - corresponding buffer; writing module, for the packet written into the buffer identified in which, on each of the CPU core to the host buffer - corresponds.
  8. 8. 根据权利要求7所述的装置,其特征在于,所述第一确定模块用于根据所述报文的控制信息进行哈希计算得到哈希值,并根据所述哈希值确定相应的线程。 8. The apparatus according to claim 7, wherein said means for determining a first hashed to obtain a hash value based on the control information of the packet, and the value determined according to the respective hash thread.
  9. 9. 根据权利要求7所述的装置,其特征在于,进一步包括: 寄存器,用于存储所述主机上緩存区的地址和长度,以便所述写入模块在写入报文时参照。 9. The apparatus according to claim 7, characterized in that, further comprising: a register for storing the address and length of the buffer to the host, so that the writing module referred to when writing of the message.
  10. 10. 根据权利要求7至9中任一项所述的装置,其特征在于,所述控制信息为以下之一: 一元组信息、二元组信息、三元组信息、四元组信息、五元组信息。 10. The apparatus of one of claims 7 to 9 claims, wherein the control information is one of the following: One tuple information, information tuple, triplet information, information quads, five tuple information.
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CN102045199A (en) * 2010-12-17 2011-05-04 天津曙光计算机产业有限公司 Performance optimization method for multi-server multi-buffer zone parallel packet sending
CN102103490A (en) * 2010-12-17 2011-06-22 曙光信息产业股份有限公司 Method for improving memory efficiency by using stream processing
CN102497322A (en) * 2011-12-19 2012-06-13 曙光信息产业(北京)有限公司 High-speed packet filtering device and method realized based on shunting network card and multi-core CPU (Central Processing Unit)
CN102541803A (en) * 2011-12-31 2012-07-04 曙光信息产业股份有限公司 Data sending method and computer
CN102541779A (en) * 2011-11-28 2012-07-04 曙光信息产业(北京)有限公司 System and method for improving direct memory access (DMA) efficiency of multi-data buffer
CN102567226A (en) * 2011-12-31 2012-07-11 曙光信息产业股份有限公司 Data access implementation method and data access implementation device
CN102571580A (en) * 2011-12-31 2012-07-11 曙光信息产业股份有限公司 Data receiving method and computer
CN102662865A (en) * 2012-04-06 2012-09-12 福建星网锐捷网络有限公司 Multi-core CPU (central processing unit) cache management method, device and equipment
CN102984085A (en) * 2012-11-21 2013-03-20 网神信息技术(北京)股份有限公司 Method and apparatus for mapping
CN103532876A (en) * 2013-10-23 2014-01-22 中国科学院声学研究所 Processing method and system of data stream
CN104753813A (en) * 2013-12-27 2015-07-01 国家计算机网络与信息安全管理中心 DMA (Direct Memory Access) message transfer method
CN105187235A (en) * 2015-08-12 2015-12-23 广东睿江科技有限公司 Message processing method and device
WO2017177400A1 (en) * 2016-04-13 2017-10-19 华为技术有限公司 Data processing method and system

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CN102103490A (en) * 2010-12-17 2011-06-22 曙光信息产业股份有限公司 Method for improving memory efficiency by using stream processing
CN102045199A (en) * 2010-12-17 2011-05-04 天津曙光计算机产业有限公司 Performance optimization method for multi-server multi-buffer zone parallel packet sending
CN102103490B (en) 2010-12-17 2014-07-23 曙光信息产业股份有限公司 Method for improving memory efficiency by using stream processing
CN102541779B (en) * 2011-11-28 2015-07-08 曙光信息产业(北京)有限公司 System and method for improving direct memory access (DMA) efficiency of multi-data buffer
CN102541779A (en) * 2011-11-28 2012-07-04 曙光信息产业(北京)有限公司 System and method for improving direct memory access (DMA) efficiency of multi-data buffer
CN102497322A (en) * 2011-12-19 2012-06-13 曙光信息产业(北京)有限公司 High-speed packet filtering device and method realized based on shunting network card and multi-core CPU (Central Processing Unit)
CN102571580A (en) * 2011-12-31 2012-07-11 曙光信息产业股份有限公司 Data receiving method and computer
CN102567226A (en) * 2011-12-31 2012-07-11 曙光信息产业股份有限公司 Data access implementation method and data access implementation device
CN102541803A (en) * 2011-12-31 2012-07-04 曙光信息产业股份有限公司 Data sending method and computer
CN102662865B (en) * 2012-04-06 2014-11-26 福建星网锐捷网络有限公司 Multi-core CPU (central processing unit) cache management method, device and equipment
CN102662865A (en) * 2012-04-06 2012-09-12 福建星网锐捷网络有限公司 Multi-core CPU (central processing unit) cache management method, device and equipment
CN102984085A (en) * 2012-11-21 2013-03-20 网神信息技术(北京)股份有限公司 Method and apparatus for mapping
CN103532876A (en) * 2013-10-23 2014-01-22 中国科学院声学研究所 Processing method and system of data stream
CN104753813A (en) * 2013-12-27 2015-07-01 国家计算机网络与信息安全管理中心 DMA (Direct Memory Access) message transfer method
CN104753813B (en) * 2013-12-27 2018-03-16 国家计算机网络与信息安全管理中心 The method of transmitting messages Dma
CN105187235A (en) * 2015-08-12 2015-12-23 广东睿江科技有限公司 Message processing method and device
WO2017177400A1 (en) * 2016-04-13 2017-10-19 华为技术有限公司 Data processing method and system

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