CN102521175B - SDRAM (synchronous dynamic random access memory) controller and operating method for same - Google Patents
SDRAM (synchronous dynamic random access memory) controller and operating method for same Download PDFInfo
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Abstract
The invention discloses an SDRAM (synchronous dynamic random access memory) controller and an operating method for the same. The controller comprises a read-write signal receiving and processing module, a data caching module and an SDRAM read-write time sequence implementation module. The SDRAM read-write time sequence implementation module comprises a read time sequence state machine and a write time sequence state machine; the data caching module comprises a temporary storage area, an address register, a write identifier register and a valid data register; the read-write signal receiving and processing module is connected with an external bus; and the SDRAM read-write time sequence implementation module is connected with a dynamic random access memory. The controller can be mounted on a processor not supporting burst read-write to realize high-speed read-write functions of the SDRAM. As read-write operation for the SDRAM in practical application frequently arms at adjacent areas and some processors do not support burst read-write operation of data, the controller in the form of an IP (internet protocol) core can be applied to many occasions, and system efficiency can be effectively improved.
Description
Technical field
The present invention relates to a kind of sdram controller and method of work thereof, belong to embedded, SOC technical field.
Background technology
SDRAM, as stochastic and dynamic storer, has burst mode, and very high read-write speed can be provided.But in some application, CPU does not possess burst read-write capability, so if adopt common sdram controller, read-write speed can be very restricted.Burst mode refer to when an address is carried out addressing and operated after, needn't re-start again addressing, can carry out read-write operation to one section of continuous address, so just saved a lot of time, there is very high read-write speed.
Summary of the invention
For above technical deficiency, the invention provides a kind of reasonable in design, move efficient sdram controller, this controller is by adding data buffer storage part, use to greatest extent the burst read-write mode of SDRAM, to promote the read-write speed of stochastic and dynamic storer (SDRAM) and the work efficiency of place system thereof.
The present invention also provides the method for work of above-mentioned sdram controller.
Technical scheme of the present invention is as follows:
A kind of sdram controller, comprises that read-write reception and processing module, data cache module and SDRAM read-write sequence realize module; Described SDRAM read-write sequence is realized module and is comprised and read sequential state machine and write sequential state machine; Described data cache module comprises staging area, address register, writes marker register and the effective register of data; Described read-write reception is connected with external bus with processing module, and described SDRAM read-write sequence is realized module and is connected with stochastic and dynamic storer (SDRAM).
Described read-write receives and is connected with external bus by data line, address wire, reading writing signal line and acknowledge signal line with processing module; Described SDRAM read-write sequence is realized module and is connected with described stochastic and dynamic storer (SDRAM) with data active line by data line, address wire, row route selection, column selection line, piece route selection, clock/clock enable line, write signal line.
Most importantly staging area in data cache module, the width of staging area is consistent with highway width, and length is consistent with the burst mode length of setting; In data cache module, also comprise address register, write marker register and the effective register of data etc.There are two effects staging area: in the time that needs are initiated a read operation, a succession of data that read are stored in this region; In the time need to writing new data to a certain address in address register corresponding address section, new data is kept in to the correspondence position in this region.Address in SDRAM corresponding to data in address register stores staging area.Writing in marker register storage staging area the data of which position need to be written in SDRAM and upgrade.Whether the effective register of data is used for identifying data in staging area effective.
SDRAM read-write sequence is realized module and is used for generating concrete sequential to SDRAM practical operation, mainly reads (reading sequential state machine) by burst and two state machines of single writing (writing sequential state machine) form.In the time that needs are initiated once new read operation, read sequential state machine and will start working, the data that read are stored in the staging area of data cache module, and upgrade address register wherein.Writing sequential state machine mainly works in both cases: when whole sdram controller is during in idle condition, sdram controller reading out data cache module write marker register, the data of upgrading if necessary, this writes sequential state machine will enter duty, write data in SDRAM, simultaneously by the correspondence position zero writing in marker register; Another kind of situation is that this is write sequential state machine and enters mode of operation, writes data in SDRAM when the data address that will write is not during in scope corresponding to address register.
The method of work of above-mentioned sdram controller, method step is as follows:
1) when sdram controller is initial, in idle condition, read-write receives with processing module and detects the read-write requests signal of whether receiving from bus:
If a. receive the read request from bus, carry out step 2);
If b. receive the write request from bus, carry out step 3);
Whether if c. do not receive the request that reads or writes from bus, detecting writing of data cache module has data need to write SDRAM in marker register to upgrade:
If c1. there are data need to write SDRAM, to notify SDRAM read-write sequence to realize module and initiate write operation, the data that will upgrade are written to the corresponding address of SDRAM;
If c2. do not have data need to write SDRAM, sdram controller reenters idle condition, and read-write receives with processing module and proceeds cycle detection;
2) read-write receives with processing module and detects the read request of receiving from bus:
D. read-write receives the address of detecting request msg in read request with processing module whether in the address register corresponding address section in data cache module:
If d1. the address of request msg is in address register corresponding address section, whether effective by the corresponding data of the effective register identification of data in detection data cache module: if corresponding data is effective, to carry out steps d 4; If corresponding data is invalid, wait for until corresponding data is effective; Described corresponding data refers to, data corresponding with the address of request msg in staging area;
D2. the address of request msg, not in address register corresponding address section, empties the effective register of data; Detection writes marker register: if there are data to need to upgrade, notify SDRAM read-write sequence to realize module and initiate write operation, all data of upgrading that need are written in SDRAM, will write the zero clearing of marker register correspondence position writing fashionable needs, after renewal completes, carry out steps d 3; If do not have data to upgrade, directly carry out steps d 3.
D3. notify SDRAM read-write sequence to realize module and initiate read operation, by burst mode, the data in the address corresponding address section of bus request data are read in staging area, the start address of initiating read operation is the address of bus request data, getting after first group of data (ask read data), carry out steps d 4, at this moment SDRAM read-write sequence is realized module and is continued to read residue continuation address corresponding data, operates with steps d 4 is parallel;
D4. read-write receives with processing module the data that read is put in the address wire of bus, then bus is sent to answer signal, and last read-write receives with processing module and enters idle condition;
3) read-write receives with processing module and detects the write request of receiving from bus:
E. read-write receives the address of detecting request msg in write request with processing module whether in the address register corresponding address section in data buffer storage part:
E1. in write request the address of request msg in address register corresponding address section: the correspondence position data in staging area are upgraded, and are write the position set of the corresponding address in marker register, carry out step e3;
E2. in write request the address of request msg not in address register corresponding address section: notice SDRAM read-write sequence is realized module and is initiated write operation, and the data of required renewal are directly write in SDRAM, carries out step e3;
E3. read-write receives with processing module and sends answer signal to bus, and last sdram controller enters idle condition.
Often the present invention is directed in actual applications and need to carry out adjacent area read-write operation to SDRAM, wherein read-write receives the read-write sending with processing module reception & disposal bus, determines whether needing to initiate once new read-write operation by the address that will operate; SDRAM read-write sequence is realized module and is used for producing the read-write (row choosing, column selection, data, address, clock etc.) mutual with SDRAM, and this part adopts the burst read mode of SDRAM, to realize the fast processing function of mass data; Data cache module one is that the continuous data reading is carried out to buffer memory, and ensureing when neighbor address data are read can fast return, the 2nd, the data that write are stored temporarily, and ensure the ageing of data.
The invention has the beneficial effects as follows:
The present invention can be mounted to the high-speed read-write function that realizes SDRAM on the processor of not supporting burst read-write.Maximally utilise the burst mode that SDRAM itself supports, improved the efficiency of read-write, in the processor system of not supporting burst read-write, effectively strengthened the performance of system.
Brief description of the drawings
Fig. 1 is module frame chart of the present invention;
Fig. 2 is the process flow diagram of the method for the invention.
Embodiment
Below in conjunction with accompanying drawing 1-2, the invention will be further described, but be not limited to this.
Embodiment 1,
As shown in Figure 1, a kind of sdram controller, comprises that read-write reception and processing module, data cache module and SDRAM read-write sequence realize module; Described SDRAM read-write sequence is realized module and is comprised and read sequential state machine and write sequential state machine; Described data cache module comprises staging area, address register, writes marker register and the effective register of data; Described read-write reception is connected with external bus with processing module, and described SDRAM read-write sequence is realized module and is connected with stochastic and dynamic storer (SDRAM).Described read-write receives and is connected with external bus by data line, address wire, reading writing signal line and acknowledge signal line with processing module; Described SDRAM read-write sequence is realized module and is connected with described stochastic and dynamic storer (SDRAM) with data active line by data line, address wire, row route selection, column selection line, piece route selection, clock/clock enable line, write signal line.
Embodiment 2,
As shown in Figure 2, a kind of method of work of sdram controller as described in Example 1, method step is as follows:
1) when sdram controller is initial, in idle condition, read-write receives with processing module and detects the read-write requests signal of whether receiving from bus:
If a. receive the read request from bus, carry out step 2);
If b. receive the write request from bus, carry out step 3);
Whether if c. do not receive the request that reads or writes from bus, detecting writing of data cache module has data need to write SDRAM in marker register to upgrade:
If c1. there are data need to write SDRAM, to notify SDRAM read-write sequence to realize module and initiate write operation, the data that will upgrade are written to the corresponding address of SDRAM;
If c2. do not have data need to write SDRAM, sdram controller reenters idle condition, and read-write receives with processing module and proceeds cycle detection;
2) read-write receives with processing module and detects the read request of receiving from bus:
D. read-write receives the address of detecting request msg in read request with processing module whether in the address register corresponding address section in data cache module:
If d1. the address of request msg is in address register corresponding address section, whether effective by the corresponding data of the effective register identification of data in detection data cache module: if corresponding data is effective, to carry out steps d 4; If corresponding data is invalid, wait for until corresponding data is effective; Described corresponding data refers to, data corresponding with the address of request msg in staging area;
D2. the address of request msg, not in address register corresponding address section, empties the effective register of data; Detection writes marker register: if there are data to need to upgrade, notify SDRAM read-write sequence to realize module and initiate write operation, all data of upgrading that need are written in SDRAM, will write the zero clearing of marker register correspondence position writing fashionable needs, after renewal completes, carry out steps d 3; If do not have data to upgrade, directly carry out steps d 3.
D3. notify SDRAM read-write sequence to realize module and initiate read operation, by burst mode, the data in the address corresponding address section of bus request data are read in staging area, the start address of initiating read operation is the address of bus request data, getting after first group of data (ask read data), carry out steps d 4, at this moment SDRAM read-write sequence is realized module and is continued to read residue continuation address corresponding data, operates with steps d 4 is parallel;
D4. read-write receives with processing module the data that read is put in the address wire of bus, then bus is sent to answer signal, and last read-write receives with processing module and enters idle condition;
3) read-write receives with processing module and detects the write request of receiving from bus:
E. read-write receives the address of detecting request msg in write request with processing module whether in the address register corresponding address section in data buffer storage part:
E1. in write request the address of request msg in address register corresponding address section: the correspondence position data in staging area are upgraded, and are write the position set of the corresponding address in marker register, carry out step e3;
E2. in write request the address of request msg not in address register corresponding address section: notice SDRAM read-write sequence is realized module and is initiated write operation, and the data of required renewal are directly write in SDRAM, carries out step e3;
E3. read-write receives with processing module and sends answer signal to bus, and last sdram controller enters idle condition.
Claims (1)
1. a method of work for sdram controller, wherein said sdram controller comprises that read-write reception and processing module, data cache module and SDRAM read-write sequence realize module; Described SDRAM read-write sequence is realized module and is comprised and read sequential state machine and write sequential state machine; Described data cache module comprises staging area, address register, writes marker register and the effective register of data; Described read-write reception is connected with external bus with processing module, and described SDRAM read-write sequence is realized module and is connected with SDRAM; Described read-write receives and is connected with external bus by data line, address wire, reading writing signal line and acknowledge signal line with processing module; Described SDRAM read-write sequence is realized module and is connected with SDRAM with data active line by data line, address wire, row route selection, column selection line, piece route selection, clock/clock enable line, write signal line;
It is characterized in that, the method for work of described sdram controller comprises that step is as follows:
1) when sdram controller is initial, in idle condition, read-write receives with processing module and detects the read-write requests signal of whether receiving from bus:
If a. receive the read request from bus, carry out step 2);
If b. receive the write request from bus, carry out step 3);
Whether if c. do not receive the request that reads or writes from bus, detecting writing of data cache module has data need to write SDRAM in marker register to upgrade:
If c1. there are data need to write SDRAM, to notify SDRAM read-write sequence to realize module and initiate write operation, the data that will upgrade are written to the corresponding address of SDRAM;
If c2. do not have data need to write SDRAM, sdram controller reenters idle condition, and read-write receives with processing module and proceeds cycle detection;
2) read-write receives with processing module and detects the read request of receiving from bus:
D. read-write receives the address of detecting request msg in read request with processing module whether in the address register corresponding address section in data cache module:
If d1. the address of request msg is in address register corresponding address section, whether effective by the corresponding data of the effective register identification of data in detection data cache module: if corresponding data is effective, to carry out steps d 4; If corresponding data is invalid, wait for until corresponding data is effective; Described corresponding data refers to, data corresponding with the address of request msg in staging area;
D2. the address of request msg, not in address register corresponding address section, empties the effective register of data; Detection writes marker register: if there are data to need to upgrade, notify SDRAM read-write sequence to realize module and initiate write operation, all data of upgrading that need are written in SDRAM, will write the zero clearing of marker register correspondence position writing fashionable needs, after renewal completes, carry out steps d 3; If do not have data to upgrade, directly carry out steps d 3;
D3. notify SDRAM read-write sequence to realize module and initiate read operation, by burst mode, the data in the address corresponding address section of bus request data are read in staging area, the start address of initiating read operation is the address of bus request data, getting after first group of data, carry out steps d 4, at this moment SDRAM read-write sequence is realized module and is continued to read residue continuation address corresponding data, operates with steps d 4 is parallel;
D4. read-write receives with processing module the data that read is put in the address wire of bus, then bus is sent to answer signal, and last sdram controller enters idle condition;
3) read-write receives with processing module and detects the write request of receiving from bus:
E. read-write receives the address of detecting request msg in write request with processing module whether in the address register corresponding address section in data buffer storage part:
E1. in write request the address of request msg in address register corresponding address section: the correspondence position data in staging area are upgraded, and are write the position set of the corresponding address in marker register, carry out step e3;
E2. in write request the address of request msg not in address register corresponding address section: notice SDRAM read-write sequence is realized module and is initiated write operation, and the data of required renewal are directly write in SDRAM, carries out step e3;
E3. read-write receives with processing module and sends answer signal to bus, and last sdram controller enters idle condition.
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| WO2015061921A1 (en) * | 2013-10-29 | 2015-05-07 | 上海宝存信息科技有限公司 | Dynamic caching method and system for data storage system |
| CN105741237B (en) * | 2016-01-26 | 2019-03-26 | 南京铁道职业技术学院 | A kind of hardware implementation method based on FPGA Image Reversal |
| CN106845290B (en) * | 2017-01-25 | 2020-06-05 | 天津大学 | SRAM controller for secure memory chip and interface circuit thereof |
| CN112416823B (en) * | 2020-11-15 | 2024-05-03 | 珠海一微半导体股份有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN112506823B (en) * | 2020-12-11 | 2023-09-29 | 盛立安元科技(杭州)股份有限公司 | FPGA data reading and writing method, device, equipment and readable storage medium |
| CN113892911A (en) * | 2021-09-28 | 2022-01-07 | 北京清雷科技有限公司 | Device and method for acquiring sleep breathing data |
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| CN1553496A (en) * | 2003-06-05 | 2004-12-08 | 中兴通讯股份有限公司 | Controller for accessing system chip external SDRAM and realizing method thereof |
| CN101814012A (en) * | 2010-05-20 | 2010-08-25 | 锐迪科科技有限公司 | SDRAM (Synchronous Dynamic Random Access Memory) memory structure and data reading and writing method |
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| CN1553496A (en) * | 2003-06-05 | 2004-12-08 | 中兴通讯股份有限公司 | Controller for accessing system chip external SDRAM and realizing method thereof |
| CN101814012A (en) * | 2010-05-20 | 2010-08-25 | 锐迪科科技有限公司 | SDRAM (Synchronous Dynamic Random Access Memory) memory structure and data reading and writing method |
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