JPH11224221A - Unit and method for memory control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a unit and method for memory control which maximizes the data transfer performance of an SDRAM by optimizing the order of command issue according to an access pattern. SOLUTION: A transfer request unit 11 outputs a command regarding the reading and writing of data. An address generation part 12 generates a control signal according to the command and also outputs the number of starting transfer bytes of read access. A command generation part 13 generates a control command based upon the control signal to control the SDRAM 15. At this time, the command generation part 13 judges the number of transfer bytes and performs control so that an instruction with good data transfer efficiency is executed first. Namely, when a data read is made exceeding a bank border, which of the read process of a bank A and the active process of a bank B is carried out first is judged to control the SDRAM 15. A data process part 14 mediates data transfer between a transfer request unit 11 and the SDRAM 15 according to the control command.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory control device and method, and more particularly, to a dynamic random access memory (DRA) that performs data transfer in synchronization with a clock.
M), that is, synchronous DRAM (Synchronous DRAM)
In a circuit for controlling DRAM (SDRAM), SD
The present invention relates to a memory control device and method for improving a substantial bus bandwidth of a RAM.

[0002]

2. Description of the Related Art SDRAMs have been conventionally used as one of devices for storing data. This SDRAM is capable of continuous data transfer in synchronization with a clock, and when burst transfer is specified, data transfer for the specified number of bytes can be performed continuously in units of one clock. In general, the storage area in the SDRAM is divided into two areas (banks A and B) as shown in FIG. As described above, the storage area is divided by performing the burst transfer by switching for each bank, thereby concealing the precharge operation required when accessing a different page, and improving the transfer rate. Because you can do it.

A document describing the specifications of the SDRAM is, for example, “NEC μPD4516”.
421, μPD4516821, μPD4516161
Data Sheet "(1995, NEC) and
No. 76567, “Semiconductor storage device and synchronous semiconductor storage device” and the like exist.

[0004] As a memory control device for efficiently controlling such a high-performance SDRAM, the following device has been conventionally used. FIG. 8 is a block diagram showing an example of a configuration of a conventional memory control device. In FIG. 8, a conventional memory control device includes a transfer request unit 81
, An address generation unit 82, a command generation unit 83, a data processing unit 84, and an SDRAM 85.

The transfer request unit 81 includes an SDRAM 85
In order to perform data transfer with the address generator 82, commands such as a start address, transfer size, and read / write are output to the address generator 82. Based on the command received from the transfer request unit 81, the address generator 82 generates a plurality of control signals such as a start address, a burst length (indicating a size that can be transferred continuously by one read command), and read / write. Is generated and output to the command generation unit 83. The command generation unit 83, based on the control signal received from the address generation unit 82, generates a clock (CLK) and a row address strobe (RA).
S), column address strobe (column address
strobe; CAS), write enable (write enabl)
e; WE), generate control commands such as address designation,
The SDRAM 85 and the data processing unit 84 are controlled. The data processing unit 84 transfers read data from the SDRAM 85 to the transfer request unit 81 and transfers write data from the transfer request unit 81 to the SDRAM 85 according to the control command received from the command generation unit 83.

[0006]

However, in the control of the SDRAM 85 according to the configuration of the conventional memory control device, the SDRAM 85 is controlled depending on the conditions of data transfer.
May not be used efficiently.

For example, in an SDRAM 85 whose storage area is divided into banks A and B, as shown in FIG. 9, the sum of data a1 to a2 existing in bank A and data b1 to b8 existing in bank B This is a case where ten pieces of data are continuously read out beyond a bank boundary.

In the above case, the data a2 of the bank A
And the data b1 of the bank B cannot be read at the same time.
The order of commands issued to M85 is as shown in FIG. In FIG. 10, the precharge command for bank A is “Pa”, the precharge command for bank B is “Pb”, the active command for bank A is “Aa”, and the active command for bank B is “Ab”. The read command for the bank A is represented by "Ra", and the read command for the bank B is represented by "Rb". The CAS latency is "3" clocks, and the burst length is "8" data.

Here, the precharge command is defined as SD
This is a command for initializing a place in the RAM 85 for temporarily waiting for data. The active command is a command for writing data to be read in the temporary standby location. The read command is a command for reading data written in the temporary standby location. Also,
The interval (Pa) at which a precharge command, an active command, and a read command for the same bank can be issued
⇒ Aa ⇒ Ra or Pb ⇒ Ab ⇒ Rb interval), and the active command issue interval between bank A and bank B (Aa ⇔ Ab interval) is the minimum transition time C
Three clocks are required because of the AS latency.

Referring to FIG. 10, command generation unit 83
Issues a Pa command to the bank A in which the data a1 and a2 exist to read the data (0th cycle). Then, A for bank A
Although it is desired to issue the a command, it cannot be issued continuously due to the limitation of the CAS latency. Therefore, the Pb command is issued to the bank B using this time (first cycle). Thereafter, the Aa command is issued at the third clock after the Pa command is issued (third cycle).

Considering the commands that can be issued next, the Ra command for bank A or the Ab command for bank B is considered. Since both commands are restricted by the CAS latency, it is necessary to wait for three clocks to elapse. No. Here, there is a rule that the command generation unit 83 executes processing in the order of the control signals sent from the address generation unit 82. Therefore, the command generation unit 83
After elapse of three clocks, the Ra command is issued first (sixth cycle), and then the Ab command is issued (seventh cycle). Therefore, the Rb command is issued in the tenth cycle at the earliest.

By the above processing, the data a1 and a2 are
From the ninth cycle three clocks after the Ra command issuance, the data b1 to b8 are sequentially read from the thirteenth cycle three clocks after the Rb command issuance. Therefore, all data reading ends in the 20th cycle.

As described above, in the conventional memory control device,
Due to the above-mentioned fixed rules and restrictions, data read of bank A and data read of bank B cannot be performed consecutively (FIG. 10, 11th to 12th cycles). This may take a long time. That is, when data is continuously transferred from an arbitrary address of the SDRAM 85 beyond the bank boundary, a problem arises in that data transfer efficiency is deteriorated due to a command issuing procedure which is uniquely determined.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control device which can always optimize the order in which commands are issued to the SDRAM in accordance with the relationship between access contents and bank boundaries, and can maximize the data transfer performance of the SDRAM. To provide.

[0015]

According to a first aspect of the present invention, there is provided a synchronous memory (hereinafter referred to as an SDR) comprising a plurality of banks and reading and writing data using a clock.
AM), a transfer requesting means for outputting a command relating to reading and writing of data, a command input, generating and outputting a predetermined control signal in accordance with the command, and performing read access. Address generation means for outputting the number of first transfer bytes, generating and outputting a clock, inputting a control signal and the number of transfer bytes, generating and outputting a predetermined control command according to the control signal, and outputting the SDRAM And a data processing means for inputting a control command and mediating data transfer between the transfer request means and the SDRAM in accordance with the control command. When performing data read, the command generation means stores the data in the first bank according to the number of transfer bytes. And controlling the issue order of the active command regarding a subsequent bank as read command.

As described above, according to the first aspect, which of the read command for the first bank and the active command for the subsequent bank is issued first based on the number of transfer bytes generated by the command generating means in the address generating means. Then, the processing of the SDRAM is controlled.
This makes it possible to issue a command so that the data transfer cycle always ends in the shortest time when performing continuous data read for different banks, and it is possible to reduce the number of cycles required for two consecutive accesses. , SDRA
The effective transfer rate of M can be improved.

In a second aspect based on the first aspect, the command generation means, when the number of transfer bytes is larger than the minimum number of transition clocks between the commands, changes the read command for the first bank to the active command for the subsequent bank. If the number of transfer bytes is smaller than the minimum number of transition clocks between commands, the active command for the subsequent bank is issued earlier than the read command for the first bank.

As described above, the second invention shows a typical control method of the command generation means in the first invention.

A third invention relates to a memory control device for controlling a synchronous memory (hereinafter referred to as an SDRAM) composed of a plurality of banks and reading and writing data using a clock, and relates to data reading and writing. Transfer request means for outputting a command, inputting the command, generating and outputting a predetermined control signal according to the command, and outputting a transfer size of read data relating to one of the plurality of banks to be processed; Address generating means, generating and outputting a clock, inputting a control signal, generating and outputting a predetermined control command according to the control signal, and controlling the SDRAM; and reading the command generating means Count the number of command issuances, enter the transfer size, and A counter for subtracting the burst length from the size; and a data processing unit for inputting a control command and mediating data transfer between the transfer requesting unit and the SDRAM in accordance with the control command. When the burst length or less is reached, the command generation means is notified of the fact, and the command generation means responds to the notification by reading the next read command and automatically performing precharge when the read processing is completed. It is characterized in that it is issued as an attached read command.

As described above, in the third aspect, the counter counts the number of read commands issued by the command generation means to detect the last data transfer to one of the plurality of banks to be processed. The command generating means issues a read command with precharge according to the detection result to control the processing of the SDRAM. As a result, the bank to which the command with precharge has been issued is
After the read processing for one data is completed, the precharge for the other data is automatically executed. Therefore, even if the issue timing of the precharge command coincides with the issue timing of the subsequent other command, the precharge processing starts. Is not delayed, and the effective transfer rate of the SDRAM can be improved.

According to a fourth aspect of the present invention, there is provided a memory control method for controlling a synchronous memory (hereinafter, referred to as an SDRAM) comprising a plurality of banks and reading and writing data using a clock. Outputting a command relating to data reading when continuously reading data across bank boundaries by inputting the command, generating and outputting a predetermined control signal according to the command, and starting the read access. And outputting a control command based on the control signal and the number of transfer bytes, in accordance with the control signal and the number of transfer bytes. Controlling.

As described above, according to the fourth invention, it is determined which of a read command for the first bank and an active command for the subsequent bank is to be issued first in accordance with the number of first transfer bytes of the read access. SDRA
M processing is controlled. This makes it possible to issue a command so that the data transfer cycle always ends in the shortest time when performing continuous data read for different banks, and it is possible to reduce the number of cycles required for two consecutive accesses. , The effective transfer rate of the SDRAM can be improved.

In a fifth aspect based on the fourth aspect, the step of generating and outputting the control command includes, when the number of transfer bytes is larger than the minimum number of transition clocks between the commands, a read command for the first bank. The active command for the subsequent bank is issued before the active command for the subsequent bank, and if the number of transfer bytes is smaller than the minimum number of transition clocks between each command, the active command for the subsequent bank is issued before the read command for the first bank. And

As described above, the fifth invention shows a typical control method in the step of generating a control command in the fourth invention.

A sixth aspect of the present invention is a memory control method for controlling a synchronous memory (hereinafter, referred to as an SDRAM) which includes a plurality of banks and reads and writes data using a clock, and relates to data reading and writing. Outputting a command, generating and outputting a predetermined control signal in accordance with the command, outputting the read data transfer size for one of the plurality of banks to be processed, and issuing a read command to the SDRAM. Counting the number of times, subtracting the burst length from the transfer size for each count, and outputting a predetermined notification when the transfer size after the subtraction has reached the burst length or less; When issuing a control command based on Of a read command, and a step of issuing a precharge read command read process is performed automatically precharged when finished.

As described above, the sixth invention relates to an SDRAM
By counting the number of read commands issued to
The last data transfer to one of the banks to be processed is detected, and a read command with precharge is issued according to the detection result to control the processing of the SDRAM. As a result, the bank to which the command with precharge has been issued is automatically precharged for the other data after the read processing for one data is completed, so that the issuance timing of the precharge command is changed to the other Even when the timing coincides with the command issuance timing, the start of the precharge processing is not delayed, and the effective transfer rate of the SDRAM can be improved.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a configuration of a memory control device according to a first embodiment of the present invention. In FIG. 1, a memory control device according to the first embodiment includes a transfer request unit 11, an address generation unit 12, a command generation unit 13, a data processing unit 14, an SDRAM 15
And

The memory control device according to the first embodiment of the present invention is arranged such that the address of one bank (hereinafter, referred to as bank A) in the SDRAM 15 extends beyond the bank boundary to the other bank (hereinafter, referred to as bank B). This is effective when data transfer is continuously performed to the address of (represented by) (see FIG. 9), particularly when the number of bytes of data transfer for the bank A to be performed first is equal to or less than the burst length.

The transfer request unit 11 outputs a start address (virtual address), a transfer size, and a read (or write) command relating to data to be read (or written) to the address generator 12.

The address generator 12 receives a command from the transfer request unit 11 and generates control signals for a start address (physical address), a burst length, and a read (or write) divided into a plurality of data transfer instructions. And
Output to the command generation unit 13. Further, the address generation unit 12 generates transfer byte number information indicating how many bytes of the first transfer byte of the read access are relative to the boundary of the burst length, and outputs the information to the command generation unit 13.

The command generating unit 13 outputs a low / high signal according to the clock and the control signal received from the address generating unit 12.
Generate a control command indicating a column address, and
Output to the DRAM 15. At this time, the command generation unit 13
Determines the number of bytes in the transfer byte count information and
The SDRAM 15 is controlled so as to execute from an instruction capable of improving the data transfer rate of M15. That is, the command generation unit 13 outputs the SDRAM 1 as described above.
When data read is performed beyond the bank boundary of No. 5, it is determined which of the read process for bank A and the active process for bank B is to be executed first, and the SDRAM 1
5 is controlled. Specifically, when the number of transfer bytes of data read from the bank A is larger than the number of cycles of the CAS latency, a read command is executed to give priority to the start of reading of data of the bank A, and the number of bytes of the cycle of the CAS latency is reduced. If it is smaller, an active command is executed to complete reading of all data with the shortest number of clocks. Further, the command generation unit 13 outputs a control command for instructing a read (or write) to the data processing unit 14.

The data processing unit 14 includes a command generation unit 13
Receives a data read control command from the SDRAM
15 to read data in synchronization with the clock and transfer it to the transfer request unit 11 (or read data from the transfer request unit 11 in response to a data write control command, and synchronize the SDRAM 1 with the clock.
5).

The SDRAM 15 is a synchronous dynamic random access memory that operates in response to a control command output from the command generator 13.

Next, the improvement of the data transfer efficiency by the memory control device according to the first embodiment will be described with reference to a specific data transfer example. FIG. 2 to FIG.
FIG. 9 is a diagram showing an example of data read timing when data is continuously read out beyond a bank boundary.

FIG. 2 is a diagram showing two types of data read timings when a total of ten data, that is, data a1 to a2 in bank A and data b1 to b8 in bank B are continuously read across a bank boundary. It is. FIG. 3 shows data a1 to a3 of bank A and data b1 to b of bank B.
FIG. 9 is a diagram showing two data read timings when a total of 11 data of 8 data are continuously read out beyond a bank boundary. FIG. 4 shows data a1 to a
FIG. 9 is a diagram showing two types of data read timings in a case where a total of 12 pieces of data b1 to b8 of No. 4 and bank B are read continuously beyond the bank boundary. In each of FIGS. 2 to 4, the CAS latency is "3" clocks and the burst length is "8" data.

2 to 4, the precharge command for bank A is "Pa", the precharge command for bank B is "Pb", the active command for bank A is "Aa", and the The active command is represented by “Ab”, the read command for the bank A is represented by “Ra”, and the read command for the bank B is represented by “Rb”.

First, the contents shown in FIGS. 2 to 4 will be described. FIG. 2A is the same as the case of FIG. 10 described above. By issuing an Ra command first and then issuing an Ab command, it takes 21 cycles to complete all data reading. On the other hand, FIG.
By issuing the command and then issuing the Ra command, the cycle of starting to read the first data is delayed, but it takes only 20 cycles to complete the data read. 3 (a) and 3 (b), there is no difference between issuing the Ra command first and then issuing the Ab command, and issuing the Ab command first and then issuing the Ra command. Even in this case, it takes 21 cycles to complete all data reading. FIG. 4A shows that the Ra command is issued first, and then the Ab command is issued, so that it takes 21 cycles to complete all the data reading. In contrast,
In FIG. 4B, an Ab command is issued first, and then Ra is issued.
On the contrary, it takes 22 cycles to complete the data read by issuing the command.

As described above, when data transfer is performed from an arbitrary address across a bank boundary, whether the Ra command or the Ab command is issued first depends on the number of data transfer bytes from the bank A to be performed first. ,
The number of cycles required to complete all data reading is different. In the specific examples of FIGS. 2 to 4, it can be seen that the transfer data length changes depending on whether the CAS latency is larger or smaller than “3”.

Therefore, in the conventional memory control device, only the procedure of issuing the Ra command first and then issuing the Ab command can be performed according to fixed rules and restrictions (FIGS. 2A and 3A). 4 (a)), the data transfer efficiency may deteriorate in some cases.

On the other hand, in the present memory control device, as described above, the address
The number of bytes to be transferred to the command generator 13 is calculated and sent to the command generator 13 as the number of bytes to be transferred. Then, the command generation unit 13 first determines the number of transfer bytes obtained as information on the number of transfer bytes to be transferred to the bank A, and compares the number of transfer bytes with a predetermined CAS latency to obtain the SDRA.
M15 is controlled. For example, in the case of the above specific example, the threshold value “3” is given to the command generation unit 13 in advance. Then, if the input transfer byte number X is X <3, the command generation unit 13 issues the Ab command first (FIG. 2B), and if X ≧ 3, issues the Ra command first. (FIG. 3A and FIG. 4A)
By controlling the RAM 15, the data transfer efficiency of the SDRAM 15 can be improved.

As described above, in the memory control device according to the first embodiment of the present invention, the command generation unit 13 determines whether the Ra command and the Ab command are based on the transfer byte number information generated in the address generation unit 12. The processing of the SDRAM 15 is controlled by determining which is issued first. Thus, when performing continuous data read for different banks, it is possible to issue a command so that the data transfer cycle always ends in the shortest time, and two consecutive accesses (access to bank A and access to bank B) Access) and reduce the number of cycles required for SDR
The effective transfer rate of the AM 15 can be improved.

In the above specific embodiment, the case where the CAS latency is "3" clocks and the burst length is "8" data has been described as a condition, but the application of the present memory controller is not limited to this. Under other conditions, the data transfer cycle can be optimized by controlling the command in the same manner as described above.

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a memory control device according to the embodiment. In FIG. 5, the memory control device according to the second embodiment includes a transfer request unit 51, an address generation unit 5
2, a command generation unit 53, a data processing unit 54,
A DRAM 55 and a counter 56 are provided.

The memory control device according to the second embodiment of the present invention continuously transfers data from the address of bank A in the SDRAM 55 to the address of bank B beyond the bank boundary, and further, This is effective when data transfer is performed from the address of the bank A.

The transfer request unit 51 outputs a start address (virtual address), a transfer size, and a read (or write) command relating to data to be read (or written) to the address generator 52.

The address generator 52 receives a command from the transfer request unit 51 and generates control signals for a start address (physical address), a burst length, and a read (or write) divided into a plurality of data transfer instructions. And
Output to the command generation unit 53. Further, the address generation unit 52 outputs to the counter 56 the data transfer size to be transferred to the bank A first.

The counter 56 counts the number of times of execution of read (or write) in the command generation unit 53, and transfers the data size transferred from the transfer size given from the address generation unit 52 for each count, that is,
A burst length, which is a data size that can be transferred by a single burst instruction to the SDRAM 55, is subtracted. Then, the counter 56 notifies the command generation unit 53 when the transfer size that has been subtracted (that is, the remaining data to be transferred) becomes smaller than or equal to the burst length.

Command generation unit 53 outputs a low / high signal according to a clock and a control signal received from address generation unit 52.
Generate a control command indicating a column address, and
Output to the DRAM 55. Here, the command generation unit 53
When receiving notification from the counter 56,
A read (or write) command for bank A issued to M55 is converted into a read (/ write) command accompanied by a precharge command for bank A for the next time, and sent to SDRAM 55. The read (/ write) command accompanied by the precharge command is to issue a precharge command during the transfer processing of bank B when the transfer processing of the current bank A is completed. Instead, pre-charging of processing for the next bank A is performed. The command generation unit 53 outputs a control command for instructing read (or write) to the data processing unit 54.

The data processing unit 54 includes a command generation unit 53
Receives a data read control command from the SDRAM
Data is read from the transfer request unit 51 in synchronization with the clock and transferred to the transfer request unit 51 (or data is read from the transfer request unit 51 in response to a data write control command, and the SDRAM 5 is read in synchronization with the clock.
5).

The SDRAM 55 is a synchronous dynamic random access memory that operates in response to a control command output from the command generator 53.

Next, the fact that the data transfer efficiency is improved by the memory control device according to the second embodiment will be described with reference to a specific data transfer example in the case of the data transfer by the conventional memory control device. A comparison will be described.

FIG. 6 shows a total of twelve pieces of data, that is, data a1 to a8 of bank A and data b1 to b4 of bank B, which are continuously read across the bank boundary. FIG. 9 is a diagram showing two data read timings when reading data. FIG.
(A) shows the data read timing in the conventional memory control device as shown in FIG. FIG. 6 (b)
Indicates the data read timing in the memory control device according to the second embodiment.

In FIG. 6, the precharge command for bank A is “Pa”, the precharge command for bank B is “Pb”, the active command for bank A is “Aa”, and the active command for bank B is "Ab", a read command for bank A "Ra", a read command for bank B "Rb", and a read command with precharge for bank A "RAWP". FIG.
In the above, the CAS latency is "2" clocks and the burst length is "4" data.

Referring to FIG. 6A, command generation unit 8
No. 3 first issues a Pa command to perform data read from bank A in which data a1 to a8 exist (0th cycle). The Pb command is also issued to the bank B using the CAS latency interval (2 clocks) (first cycle). Thereafter, the Aa command is issued two clocks after the issuance of the Pa command (second cycle). Then, after another two clocks, 1
The Ra command is issued a fourth time (fourth cycle), and data a1 to a4 are transferred (because the burst length is "4"). Here, an Ab command is issued during the data transfer of the bank A, and the bank B is prepared so that it can be accessed at any time (fifth cycle). Then, the second Ra command is issued in the eighth cycle so that the data transfer of the data a5 to a8 can be started immediately after the transfer of the data a4. Next, the command generation unit 83 issues the Rb command in the twelfth cycle so that the transfer of the data a8 is completed, that is, the data b1 to b4 of the bank B can be transferred immediately after the data transfer of the bank A is completed. I do. Thereafter, data a existing at another address of bank A
Regarding the transfer from 9 to a12, Pa, Aa, and Ra are issued at two clock intervals according to the CAS latency (13th, 15th, and 17th cycles).

As described above, in the conventional memory control device, a blank period (eighteenth cycle) in which no data transfer is performed occurs between the end of the transfer process of the bank B and the start of the transfer process of another bank A. . The cause of this is,
This is because it is desired to issue the Rb command and the Pa command at the same time in the twelfth cycle, but it is impossible. Therefore, the Rb command is issued first to give priority to the data read of the bank B, and then the Pa command is issued.

On the other hand, the memory control device according to the second embodiment solves this problem by the following method. As described above, the address generation unit 52
Outputs the number “8” of the transfer data a1 to a8 for the first bank A to the counter 56 as the transfer size based on the above conditions (see FIG. 5).

Referring to FIG. 6B, the operation is the same as that described above up to the fifth cycle, but when the first Ra command in the fourth cycle is issued, the counter 56 sets the address generation unit. “4 (the number of data a1 to a4)” is subtracted from the transfer size “8” obtained from 52. Here, the remaining data to be transferred, that is, the transfer size after the subtraction (=
Since 4) has become equal to or less than the burst length (= 4), the counter 56 notifies the command generation unit 53 of that fact. Subsequently, the command generation unit 53 issues the second Ra command in the eighth cycle so that the data transfer of the data a5 to a8 can be started immediately after the transfer of the data a4. In accordance with the notification, a RawP command which is a read with precharge is output.

By this RawP command, SDRAM
Reference numeral 55 denotes a thirteenth data transfer device that can complete the transfer of the data a8 without any problem.
In the cycle, the command generation unit 53 returns Pa
Even without receiving a command, a precharge can be performed at its own discretion. As a result, the subsequent Aa command and Ra command can be issued one cycle earlier (the 14th and 16th cycles). As a result, FIG.
All data transfer can be completed by the 21st cycle with respect to the 22nd cycle of (a).

As described above, in the memory control device according to the second embodiment of the present invention, the counter 56 counts the number of read commands issued by the command generation unit 53, thereby controlling one bank for processing. The command generator 53 detects the last data transfer, issues a read command with precharge according to the detection result, and
55 is controlled. As a result, the bank to which the command with precharge has been issued is automatically precharged for the other data after the read processing for one data is completed, so that the issuance timing of the precharge command is changed to the other Even when the timing coincides with the command issuance timing, the start of the precharge process is not delayed, and the effective transfer rate of the SDRAM 55 can be improved.

In the above specific embodiment, the case where the CAS latency is "2" clocks and the burst length is "4" data has been described as a condition, but the application of the present memory control device is not limited to this. Under other conditions, the data transfer cycle can be optimized by controlling the command in the same manner as described above.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a memory control device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of data read timing when data is continuously read out beyond a bank boundary.

FIG. 3 is a diagram showing an example of data read timing when data is continuously read out beyond a bank boundary.

FIG. 4 is a diagram showing an example of data read timing when data is continuously read out beyond a bank boundary.

FIG. 5 is a block diagram illustrating a configuration of a memory control device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing an example of data read timing when data is continuously read out beyond a bank boundary.

FIG. 7 is a diagram showing a configuration of a recording area of a conventional SDRAM.

FIG. 8 is a block diagram showing a configuration of a conventional memory control device.

FIG. 9 is a diagram showing a data arrangement used for explaining the operation of the conventional memory control device.

FIG. 10 is a diagram showing an example of data read timing of a conventional memory control device.

[Explanation of symbols]

 11, 51, 81 transfer request unit 12, 52, 82 address generation unit 13, 53, 83 command generation unit 14, 54, 84 data processing unit 15, 55, 85 SDRAM 56 counter

Claims (6)

[Claims] 1. A synchronous memory (hereinafter referred to as a synchronous memory) comprising a plurality of banks and reading and writing data using a clock.
Transfer control means for outputting a command relating to reading and writing of data; inputting the command, generating and outputting a predetermined control signal in accordance with the command, Address generating means for outputting the first transfer byte number of access; generating and outputting the clock; inputting the control signal and the transfer byte number; generating a predetermined control command according to the control signal; Output and the SD
A command generation unit for controlling a RAM; and a data processing unit for inputting the control command and mediating data transfer between the transfer request unit and the SDRAM in accordance with the control command. When reading data continuously beyond a boundary, the command generation means controls the order of issuing a read command for the first bank and an active command for the subsequent bank according to the number of transfer bytes. , Memory controller. 2. The command generating means, when the number of transfer bytes is larger than the minimum number of transition clocks between commands, issues a read command for the first bank before an active command for the subsequent bank. When the number of transfer bytes is smaller than the minimum number of transition clocks between commands, an active command for the subsequent bank is issued before a read command for the first bank.
The memory control device according to claim 1. 3. A synchronous memory (hereinafter referred to as a "memory") comprising a plurality of banks and reading and writing data using a clock.
A memory control device for controlling the SDRAM), a transfer requesting means for outputting a command relating to reading and writing of data, inputting the command, generating and outputting a predetermined control signal according to the command, Address generation means for outputting a transfer size of read data relating to one of the banks to be processed among the plurality of banks; generating and outputting the clock; inputting the control signal; and performing predetermined control according to the control signal A command generating means for generating and outputting a command, controlling the SDRAM; counting the number of read commands issued by the command generating means; inputting the transfer size; and for each count, determining a burst length from the transfer size. A counter to be decremented, and the control command Data transfer means for mediating data transfer between the transfer request means and the SDRAM in accordance with the command. The counter is configured to send to the command generation means when the transfer size after the subtraction has reached the burst length or less. In response to the notification, the command generation unit issues a next read command in response to the notification as a precharged read command that is automatically precharged when the read processing is completed. , Memory controller. 4. A synchronous memory (hereinafter, referred to as a memory) comprising a plurality of banks and reading and writing data using a clock.
A memory control method for controlling the SDRAM (hereinafter referred to as SDRAM), comprising: when continuously reading data from a different bank across a bank boundary, outputting a command related to the data read; and inputting the command. Generating and outputting a predetermined control signal in accordance with the command, outputting the first transfer byte number of the read access, and issuing a control command based on the control signal and the transfer byte number. Controlling the order in which a read command for the first bank and an active command for the subsequent bank are issued in accordance with the number of transfer bytes. 5. The method according to claim 5, wherein the step of generating and outputting the control command comprises: when the number of transfer bytes is greater than a minimum number of transition clocks between commands, changing a read command for the first bank to an active command for the subsequent bank. Issuing the active command for the subsequent bank earlier than the read command for the first bank, if the number of transferred bytes is smaller than the minimum number of transition clocks between the commands.
The memory control method according to claim 4. 6. A synchronous memory (hereinafter, referred to as a synchronous memory) comprising a plurality of banks and reading and writing data using a clock.
A command for reading and writing data, generating and outputting a predetermined control signal according to the command, and performing processing among the plurality of banks. Outputting the transfer size of the read data for one bank; counting the number of read command issuances to the SDRAM; subtracting the burst length from the transfer size for each count; Outputting a predetermined notification if the burst length or less is reached; and issuing a control command based on the control signal and the notification.If the notification is issued, the next read command is read. Is automatically pre-charged when is completed And a step of issuing a over-di-conditioned read command, the memory control method.