JPH05334183A - Method for controlling memory access and memory controller - Google Patents

Abstract

PURPOSE:To perform sure operation by delaying the transmission of a response signal or the timing of access control to a bank and sufficiently setting up a margin time necessary for operation such as a precharging time. CONSTITUTION:When an access control circuit receives an access request, a memory control device 2 identifies a bank address, starts access control and allows a response signal generating circuit 10 to generate a response signal. The identified bank address is stored in a register 8. When an access request is continuously received, its bank address is compared with the preceding bank address stored in the register 8 by a comprator 9. When both the bank addresses are the same as the result of comparison, the generation of continuous accesses to the same bank is recognized, the access control timing of an access control signal generating circuit 7 to the bank is delayed, a selector 12 is controlled so as to select the response signal delayed by a delay circuit 11 and the selected signal is transmitted to an accessing original device 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control method and a memory control device for a memory device having a plurality of interleaved banks.

In an interleaved memory device in which sequential addresses are distributed to a plurality of banks (independent memory elements) to enable a parallel access operation in response to a data access request of a continuous address, continuous access to the same bank is performed. When the error occurs, an access omission occurs due to lack of a margin time required for the operation, or an access speed is likely to be reduced by giving a sufficient margin time. The present invention provides efficient access control means for an interleaved memory device.

[0003]

2. Description of the Related Art FIG. 5 shows a conventional example of the configuration of a memory system in a relatively small computer system such as a minicomputer or a microcomputer. In FIG. 5, 1
Reference numeral 6 is a CPU, 17 and 18 are interleaved MSUs having two banks, and 19 is a memory bus composed of address / data lines and control lines. Each MSU
The two banks in 17 and 18 shall be identified by A / B and C / D.

FIG. 6 shows banks A and B in the MSU 17.
2 shows an interleaved structure of. 4 for each bank
Sequential address 00,0 in units of 4 bytes with byte width
4, 08, 0C, 10, ... Are alternately allocated to the bank A and the bank B.

FIG. 7 shows an M of a bank structure using a DRAM.
The structure of the conventional example of SU is shown. In FIG. 7, 17 is an MS
U and 19 are memory buses, and 20a and 20b are DR respectively.
AM banks A and B, 21 are DRAM control blocks, and 22 is a selector.

When, for example, a read access request is issued from the CPU 16 of FIG. 5, the MSU is transmitted via the memory bus 19.
A control signal and an address are sent to the DRAM control block 21 of 17 (the description of the MSU 18 is omitted). The DRAM control block 21 identifies the bank from the address of the access request, and determines the row address strobe signal ras and the column address strobe signal cas.
Access control signals are sent to the corresponding one bank, the selector 22 is controlled, the output terminal O of the corresponding bank is selected, and the read data is transferred to the CPU via the memory bus. To control. The same applies to write access, but in this case, memory bus 1
The write data from 9 is applied to the input terminal i of each bank 20a, 20b, and writing is performed only at the address of one bank selected by the DRAM control block 21.

FIG. 8 shows the control timing in the DRAM memory. FIG. 8A shows timing waveforms of the control signals ras A and ras B sent to the banks A and B of FIG. Ras A and ras B are given with a phase difference of 90 degrees, and each pulse width is set to 2 memory clock widths (2T) that guarantee the precharge time tRP necessary for the operation of the DRAM. FIG. 8B shows the timing of interface control between the CPU 16 and the MSUs 17 and 18 of FIG. start is CPU1
6 is a bus access start signal for starting an access request from 6 to MSU, busy is a bus busy signal indicating that the bus is in use, ack is a response signal from MSU to CPU 16,
data represents data transferred from the MSU to the CPU 16 during read access.

The DRAM control block 21 of FIG.
Is the CPU1 during the period (L level) of the bus busy signal busy.
The access request information given from 6 is taken in, and the CPU
The response signal ack is returned to 16 and access control to the bank is started.

FIG. 9 shows an example of conventional memory access control in the case of performing a read access of 4 byte × 2 block data to the banks A and B having the interleave structure of FIG. 9A is an example based on the control timing shown in FIG. 8, and the access cycle is fixed to 4 clock cycles 0 to 3. The block data is taken as a continuous address, and the sequential access operation to the bank A and the bank B is repeated. Therefore, as shown in the figure, a sufficient precharge time tRP of 2T is set between the accesses in the banks A and B, so that 4 bytes of data are sequentially read from each bank.

Unlike the case of FIG. 9A, FIG. 9B includes continuous access to the bank B. That is, both the 4-byte data in the latter half of the data block and the 4-byte data in the first half of the data block are both present in bank B. Therefore, when ras B is applied to the bank B together with the second ack, the precharge time tRP in the bank B is limited to the length of T, resulting in malfunction, and the first 4-byte data of the data block is indicated by the dotted line. Fails to read.

As a solution for ensuring continuous access to the same bank as shown in FIG. 9B, the access cycle is extended to 5 clock cycles as shown in FIG. 9C. Good. As a result, tRP is always 2
Although a length of T or more is guaranteed, there is a problem that the memory access speed is significantly reduced due to the extension of the access cycle.

[0012]

SUMMARY OF THE INVENTION According to the present invention, a memory access control method for efficiently performing continuous access to the same bank in a memory device having an interleaved structure with a plurality of banks without significantly reducing the memory access speed. It is also intended to realize a memory control device.

[0013]

According to the present invention, an access request from an access source device detects continuous access to the same bank, and only when the continuous access to the same bank is detected, the subsequent request of the latter bank is detected. By delaying the timing of sending a response signal to the access request and controlling the access to the bank, the margin time necessary for the operation such as the precharge time is set sufficiently to ensure the reliable operation.

FIG. 1 is a principle block diagram of the present invention showing an exemplary method for the case of two banks. In FIG. 1, 1 is a DR with an interleaved structure having two banks.
A memory device such as an AM.

Reference numeral 2 is a memory control device for performing access control according to an access request to the memory device 1. Three
Is a central processing unit (CPU) or channel processing unit (CH
The access source device has a memory access request such as P).

Reference numerals 4a and 4b are two interleaved banks A and B which constitute the memory device 1. An access request control unit 5 such as an instruction execution control unit controls a memory access request generated by the execution of an instruction or a command.

Reference numeral 6 is an access control circuit for the banks A and B in the memory control device 2. 7 is DRA
It is an access control signal generation circuit for generating an access control signal such as ras for M. When performing continuous access to the same bank, the access control signal is generated with a delay of a predetermined time.

Reference numeral 8 is a register for temporarily holding the bank address of the preceding access request. Reference numeral 9 is a comparator that compares the preceding bank address with the bank address of an access request that is subsequently input to detect the occurrence of continuous access to the same bank.

Reference numeral 10 is a response signal generation circuit for generating a response signal to the access source device. A delay circuit (D) 11 delays the response signal by a predetermined time.

Reference numeral 12 is a selector for selecting the output of the delay circuit 11 when the comparator 9 detects continuous access to the same bank, and directly selecting the output of the response signal generating circuit 10 in other cases.

[0021]

In FIG. 1, the access source device 3 generates an access request signal by the access request control section 5 and sends it to the memory control device 2. The access request control unit 5 does not issue the next access request unless a response signal is returned from the memory control device 2.

In the memory control device 2, when the access control circuit receives the access request, it identifies the bank address, starts access control, and causes the response signal generation circuit 10 to generate a response signal. The identified bank address is stored and held in the register 8. When the access request is subsequently accepted, the bank address is compared with the preceding bank address in the register 8 by the comparator 9. If the comparison result does not match, the access control start timing and the response signal transmission timing are not delayed,
The operation as in the conventional example shown in FIG. 9A is performed.
On the other hand, if the comparison results are in agreement, it is determined that continuous access to the same bank has occurred, and the access control timing of the access control signal generation circuit 7 to that bank is delayed, and the selector 12 is controlled to delay circuit 11.
The response signal delayed by is selected and sent to the access source device 3. As a result, a long access cycle like the conventional example shown in FIG. 9C is set.

FIG. 2 is 4 bytes × 2 in the conventional example of FIG.
FIG. 8 is an operation explanatory diagram showing control timing when the present invention is applied to read access of block data of FIG. As a result of detecting that both the 4-byte data access in the latter half of the data block and the 4-byte data access in the first half of the following data block are continuous accesses to bank B, ack and ras B are indicated by double arrows. After being delayed by one clock, the precharge time tRP for two clocks (2T) is set in ras B. As a result, a reliable operation is performed, and since the timing delay is limited to the continuous access to the same bank, it is possible to minimize the decrease in the memory access speed. The signal ihras in FIG. 2 will be described later.

[0024]

EXAMPLES Next, examples of the present invention will be described. In FIG. 1, the memory control device 2 is not necessarily a hardware device independent of the memory device 1, and may be provided as a control block in one MSU as in the conventional example of FIG. 7. The number of banks may be any number of 2 or more (generally 2 ⁿ ), and access control of a plurality of banks and interface control with the access source device are
The conventional memory system can be basically used as it is. A unique point in the configuration of the present invention is that the bank operation is detected by detecting continuous access to the same bank and, when continuous access is detected, shifting the timing of access control and response signal transmission of the latter one. It should be noted that it is about creating the necessary extra time.

Therefore, it goes without saying that various ordinary conventional techniques can be used as means for delaying such timing by a predetermined time. As an example, FIG.
FIG. 3 shows a configuration example of the access control signal generation circuit 7 in the inside.

The embodiment of FIG. 3 is similar in that instead of using the configuration of delay circuit 11 and selector 12 of FIG. 1 to delay the control signal, a delayed inverted output signal is used to gate the input signal. It is something that causes the action.

In FIG. 3, 13 is an AND gate and 14
Is a clock-synchronized JKFF, 15 is a clock-synchronized DF
It is F. Further, + ras A req is a ras output request signal A, + ras A is a ras signal A, -ihras A is a ras prohibition signal A, and + and-indicate polarities. FIG. 4 is a timing chart of the embodiment of FIG. 3, and only the one for bank A is shown in FIG. 3, but in FIG. 4, the signal for bank A is in the upper half and the signal for bank B is in the lower half. It is shown in. Note that the waveforms of -ihras and + ras in FIG. 4 and the waveforms of ihras and ras in FIG. 2 have an inverted relationship.

In FIG. 3, the + ras A req signal is
This signal identifies the address from the access source device and requests the output of the ras A signal in order to start the access from the bank A, and maintains the requested state until + ras A is output. The AND gate 13 gates it by the inverted output signal -ihras A delayed by one clock and writes it in the FF 14 at the next clock. The output of the FF 14 is + ras A. Although + ras A is sent to the bank A in FIG. 1, it is simultaneously written in the FF 15 at the next clock. The inverted output of this FF15 is -ihras A, + ra
s A is delayed by one clock and the polarity is inverted.

FIG. 4 shows + ras A req and + ras B r.
+ ras for each input of eq, as indicated by the arrow
A, + ras B, -ihras A, and -ihras B are generated, respectively.

[0030]

According to the present invention, since access to each bank of the memory device is executed in the shortest access cycle that secures a margin time necessary for operation such as DRAM precharge time, an interleave function is provided. High-speed data transfer can be realized while making good use of it, and the processing performance of the computer system can be improved.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an explanatory view of the operation of the present invention.

FIG. 3 is a block diagram of an embodiment of an access control signal generation circuit.

FIG. 4 is a timing diagram of an embodiment of an access control signal generation circuit.

FIG. 5 is a configuration diagram of a conventional example of a memory system.

FIG. 6 is an explanatory diagram of an interleaved structure of a memory bank.

FIG. 7 is a configuration diagram of a conventional example of an MSU having a bank configuration.

FIG. 8 is a control timing chart of the DRAM memory.

FIG. 9 is a timing diagram of a conventional memory access control example.

[Explanation of symbols]

 1 memory device 2 memory control device 3 access source device 4a bank A 4b bank B 5 access request control unit 6 access control circuit 7 access control signal generation circuit 8 register 9 comparator 10 response signal generation circuit 11 delay circuit 12 selector

Claims (2)

[Claims] 1. A memory device comprising a plurality of interleaved banks, an access source device for making an access request to the memory device, and a corresponding bank of the memory device in response to an access request from the access source device. In a memory access control method in a system including a memory control device that performs access control, an access source device sends an access request to the memory control device when an access request occurs, and the memory control device receives the access request when the access source device receives the access request. When the access source device receives a response signal from the memory control device and sends a response signal to the memory control device, it sends the response signal to the memory control device. The operation is repeated and the memory controller continues from the access source device. Memory access characterized in that when an access request to the same bank is issued, a response signal to the access source device for the later access request and the start of the access control of the corresponding bank are delayed by a predetermined time. Control method. 2. A memory device comprising a plurality of interleaved banks is controlled, a response signal is returned to the access source device in response to an access request from the access source device, and access control to the corresponding bank of the memory device is started. The memory control device is provided with means for detecting continuous access to the same bank in response to an access request from the access source device, and when continuous access to the same bank is detected, the timing of access control of the latter of the continuous access is set. A memory control device characterized by delaying for a predetermined time.