JP2006337859A - Display control device and method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display control device which permits simultaneous display on two or more displays of different resolutions using a single-frame memory, having the effects of miniaturizing the device and reducing the cost. <P>SOLUTION: This display control device reads out a display data from the single frame buffer 103 which an internal display unit 109 shares with an external display unit 110 and outputs the display data to a high-resolution external display unit 110, while performing resolution conversion processing to the read-out display data, to output the data to the low resolution internal display unit 109, and controls each display data outputted to the internal display unit 109 and the external display unit 110, by timing the signals (clock signal, horizontal and vertical synchronizing signals) transmitted from a timing control part 104. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display control device, method, and program, and more particularly, to a display control device, method, and program capable of simultaneously performing different displays on a plurality of displays having different resolutions.

  Display control technology for simultaneous output to multiple display units is equipped with a frame memory and display control unit corresponding to each display unit, and select and output the desired frame memory and display control unit for each display unit (For example, refer to Patent Documents 1 and 2).

In addition, for the purpose of reducing the frame memory capacity with respect to the above technique, in a display device incorporating a display memory, one frame memory is shared by a plurality of display devices, and there is write access to the frame memory. In this case, a technique for transmitting display data only to a display memory of a corresponding display has been proposed (for example, see Patent Document 3).
Japanese Patent Laid-Open No. 4-90591 JP-A-9-146497 JP-A-6-295167

  However, the conventional techniques according to Patent Documents 1 and 2 have a problem that the scale of the apparatus and the cost increase are caused at the present when the resolution of each display device is increased.

  Further, in the prior art according to Patent Document 3 described above, each display device has a built-in display memory, and since display data is transferred from the frame memory to the display memory, the display memory is built-in. It cannot be applied as is to a normal display that does not exist, and in order to apply it, display data read access frequently occurs from each display to the frame memory, reducing the bus bandwidth and increasing power consumption. There is a problem of being invited.

  The present invention has been made in view of the above problems, and can display simultaneously on a plurality of displays having different resolutions with a single frame memory, which is effective in reducing the size and cost of the apparatus. An object is to provide a display control apparatus and method, and a program.

  To achieve the above object, a display control device according to claim 1 is a display control device connected to a plurality of displays having different resolutions, and stores at least one display data and is shared by the plurality of displays. A single frame memory, a first output means for outputting display data read from the frame memory to a first display having a high resolution, and a predetermined value for the read display data. Display data conversion means for performing conversion processing; second output means for outputting display data converted by the display data conversion means to a second display having a low resolution; and the first and second displays. Control means for controlling display data output to the display device by a timing signal transmitted to the display device.

  In order to achieve the above object, a display control method according to claim 7 is a display control method of a display control apparatus connected to a plurality of displays having different resolutions. A first output step of reading display data from a frame memory and outputting the display data to a first display device having a high resolution; a display data conversion step of performing a predetermined conversion process on the read display data; and the display A second output step of outputting the display data converted in the data conversion step to a second display having a low resolution; and the display data output to the first and second displays. And a control step for controlling by a timing signal to be transmitted.

  According to the present invention, display data is read from a single frame memory shared by a plurality of displays and output to a first display having a high resolution, while the read display data is subjected to predetermined conversion. Since processing is performed and output to the second display having a low resolution, and display data output to the first and second displays is controlled by a timing signal transmitted to the display, a single frame is used. It is possible to simultaneously display on a plurality of displays with different resolutions in the memory, which is effective in reducing the size and cost of the apparatus.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a hardware configuration of a display control apparatus according to the first embodiment of the present invention.

  In FIG. 1, a display control apparatus 100 includes a register setting unit 101, a memory control unit 102, a frame buffer 103 (frame memory), a timing control unit 104, a resolution conversion unit 105, and a format conversion / timing adjustment unit 106. 107, an external output terminal 108, and an internal display 109. The display control device 100 is connected to the external display device 110.

  The register setting unit 101 determines an operation of the display control apparatus 100 in response to an external setting operation. The memory control unit 102 writes display data received from the outside into the frame buffer 103 and reads the display data in accordance with a control signal (timing signal) from the timing control unit 104. The frame buffer 103 stores display data to be displayed.

  The timing control unit 104 controls the timing of the entire apparatus according to the setting received by the register setting unit 101. The resolution conversion unit 105 performs resolution conversion processing on the display data read from the frame buffer 104. The format conversion / timing adjustment units 106 and 107 perform display format change or timing adjustment as necessary according to the specifications of the display units of the internal display unit 109 and the external display unit 110, and the changed or adjusted display. Output data sequentially.

  The external output terminal 108 outputs data to be displayed on the external display device 110. The internal display 109 performs display based on the display data sent from the format conversion / timing adjustment unit 107. These displays 109 and 110 are composed of an LCD (Liquid Crystal Display). A so-called PDA (Personal Digital Assistant) is an example of a device to which such a display is applied.

  Next, referring to FIG. 2 and FIG. 3 for the case of displaying the image of XGA size (1024 × 768) on the external display 110 and displaying the image of VGA size (640 × 480) on the internal display 109. I will explain.

  FIG. 2 shows a timing chart when images are displayed on the internal display 109 and the external display 110. FIG. 3 is a flowchart showing image display processing.

  As a premise of this processing, it is assumed that display data of XGA size is sent from the outside and stored in the frame buffer 103. The storage position of the display data in the frame buffer 103 is determined by the setting in the register setting unit 101.

  The memory control unit 102 receives the control signal from the timing control unit 104, outputs a control signal to the frame buffer 103, and sequentially reads display data of XGA size (step S301). The read display data is sent to the format conversion / timing adjustment unit 106 and the resolution conversion unit 105.

  The display data sent to the format conversion / timing adjustment unit 106 is converted into a format and timing required by the external display 110 in accordance with a control signal from the timing control unit 104, and is sent to the external display 110 via the external output terminal 108. It is output (step S302). At the same time, the dot clock signal CLK 1, the horizontal synchronization signal HSYNC 1, and the vertical synchronization signal VSYNC 1 are output from the timing control unit 104 to the external output terminal 108. Thereby, an XGA size image is displayed on the external display device 110 (step S303).

  On the other hand, the resolution conversion unit 105 performs resolution conversion processing on display data of XGA size and converts it to VGA size (step S304). Since the resolution conversion process is a known technique, its description is omitted. The converted display data is sent to the format conversion / timing adjustment unit 107.

  The display data sent to the format conversion / timing adjustment unit 107 is converted into a format and timing required by the internal display 109 by a control signal from the timing control unit 104, and is sent to the internal display 109 (step S305). At the same time, the dot clock signal CLK2, the horizontal synchronization signal HSYNC2, and the vertical synchronization signal VSYNC2 are sent from the timing control unit 104 to the internal display 109, and a VGA size image is displayed on the internal display 109 (step S306). ).

  In the above configuration, by storing XGA size display data in the frame buffer 103, the XGA size external display unit 110 and the VGA size internal display unit 109 can be read once by reading the XGA size. Different displays at the same time. As a result, the number of memory accesses can be reduced, and particularly when the resolution of the display is high, it is effective in reducing the bus bandwidth and reducing the power consumption.

  According to the first embodiment, the display data is read from the single frame buffer 103 shared by the internal display 109 and the external display 110 and is output to the external display 110 having a high resolution. A timing signal for performing a resolution conversion process on the displayed display data and outputting it to the low-resolution internal display 109 and transmitting each display data output to the internal display 109 and the external display 110 from the timing control unit 104 (Controlled by clock signal, horizontal and vertical sync signals), it is possible to display on multiple displays with different resolutions at the same time with a single frame memory, which is effective in reducing the size and cost of the device. is there.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.

  In the first embodiment, the resolution conversion unit 105 performs resolution conversion processing on the display data read from the frame buffer 103 and displays the same area as the external display 110 on the internal display 109 (however, the resolution However, this may be another process.

  In the second embodiment, an example in which processing for cutting out a part of display data is performed will be described. Furthermore, when displaying the clipped area, the period of the horizontal sync signal and the vertical sync signal may change when the set clipped area is changed, and the display may not be performed properly. It is necessary to cope with the case. In the second embodiment, only differences from the first embodiment will be described.

  FIG. 4 is a block diagram showing a hardware configuration of a display control apparatus according to the second embodiment of the present invention.

  4, the display control apparatus 200 includes a register setting unit 101, a memory control unit 102, a frame buffer 103, a timing control unit 104, a cutout area changing unit 301, a cutout processing unit 302, and a format conversion / timing. Adjustment units 106 and 107, an external output terminal 108, and an internal display 109 are provided. The display control device 200 is connected to the external display device 110 via the external output terminal 108.

  The cutout area changing unit 301 stores the current cutout area setting value and determines an operation when the setting is changed.

  FIG. 5 shows a timing chart when the cutout area does not change, and FIG. 6 shows a timing chart when it changes. FIG. 7 is a flowchart showing image display processing.

  As a premise of this processing, it is assumed that display data of XGA size is sent from the outside and stored in the frame buffer 103. The storage position of the display data in the frame buffer 103 is determined by the setting in the register setting unit 101.

  The memory control unit 102 receives the control signal from the timing control unit 104, outputs a control signal to the frame buffer 103, and reads display data of XGA size (step S701). The read display data is sent to the format conversion / timing adjustment unit 106 and the cutout processing unit 302.

  Next, the display data sent to the format conversion / timing adjustment unit 106 is processed in the same manner as steps S302 and S303 in FIG. 3 in the first embodiment (steps S702 to S703).

  On the other hand, the data sent to the cutout processing unit 302 is subjected to area masking processing according to the setting by the register setting unit 101 (step S704). The cut out display data is sent to the format conversion / timing adjustment unit 107.

  The display data sent to the format conversion / timing adjustment unit 107 is converted into a format and timing required by the internal display 109 by a control signal from the timing control unit 104, and is sent to the internal display 109 (step S705). At this time, the dot clock signal CLK2, the horizontal synchronization signal HSYNC2, and the vertical synchronization signal VSYNC2 are simultaneously output to display the VGA size on the internal display 109 (step S706). In the first embodiment, the relationship between HSYNC1 and VSYNC1 is constant, but in the second embodiment, the relationship between the output timings of HSYNC2 and VSYNC2 changes according to the cutout region. FIG. 4 shows a timing chart when the cutout area does not change, and FIG. 5 shows a timing chart when the cutout area changes. In the figure, the display data is sent to the internal display 109 with respect to the relationship between the VSYNC2 assertion timing and the active data transmission start timing, and the relationship between the active data transmission area, the active data transmission completion timing, and the VSYNC2. It is sent in a format that satisfies the timing required by. In FIG. 6, since the VGA display area changes downward, the period of the vertical synchronization signal changes by + α.

  Next, processing when the register setting unit 101 changes the cutout area setting will be described with reference to FIGS. 8 and 9.

  FIG. 8 is a block diagram showing an internal configuration of the cutout area changing unit 301 in FIG. FIG. 9 is a flowchart illustrating processing executed by the cutout region changing unit 301.

  In FIG. 8, the cutout area changing unit 301 includes a comparison unit 601, a setting storage unit 602, and a rewrite control unit 603.

  In FIG. 9, the setting of the cutout area in the register setting unit 101 is performed by designating the coordinate AREA (X, Y) at the upper left of the cutout area.

  First, the initial setting AREA (X, Y) after power-on is stored as CURRENT_AREA (X0, Y0) in the setting storage unit 602 (step S901). Next, when the new setting information AREA (X, Y) is sent, it is input to the comparator 601 (step S902). The comparator 601 compares the input AREA value (X, Y) with the value CURRENT_AREA (X0, Y0) stored in the setting storage unit 602 (step S903), and the difference value (X−X0, Y−). Y0) is sent to the rewrite control unit 603 (step S904).

  The rewrite control unit 603 performs the following processing for each assertion timing of the vertical synchronization signal (that is, for each frame). The difference value is compared with an allowable difference value (Xmax, Ymax) set in advance from the specifications of the display (step S905). If the difference value is within the allowable range, that is, | X−X0 | ≦ Xmax and | Y−Y0 | If ≦ Ymax (YES in step S906), AREA (X, Y) is read from the comparison unit 601 and sent to the cutout processing unit 302 as it is (step S907).

  On the other hand, when it is out of the allowable range, that is, when | X−X0 |> Xmax or | Y−Y0 |> Ymax (NO in step S906), the difference value is divided into values within the allowable difference value. The data is divided into times and sent to the cut-out processing unit 601 (step S908). Thereafter, CURRENT_AREA (X0, Y0) is rewritten to (X, Y) (step S909).

  For example, as shown in FIG. 6, assuming (X0, Y0) = (350, 90), (X, Y) = (320, 288), and (Xmax, Ymax) = (50, 80). To do. At this time, X−X0 = 30 and X−X0 ≦ Xmax, but Y−Y0 = 198, and therefore Y−Y0> Ymax. Therefore, Y−Y0 = 198 is divided into values (80, 80, 38) within Ymax = 80. Accordingly, (320, 170), (320, 250), and (320, 288) are sent to the cutout processing unit 302 as cutout area setting information for each frame. That is, although the VGA display area is shown to move in one frame in FIG. 6, it actually moves over three frames.

  In the above configuration, by storing XGA size display data in the frame buffer 103, the XGA size external display unit 110 and the VGA size internal display unit 109 can be read once by reading the XGA size. Different displays at the same time. As a result, the number of memory accesses can be reduced, and particularly when the resolution of the display is high, it is effective in reducing the bus bandwidth and reducing the power consumption.

  Even when the display area of the low-resolution internal display 109 is changed, the horizontal synchronization signal or the vertical synchronization signal is out of the allowable range of the internal display 109 and the display is not flickered smoothly. The effect is that it can be changed.

  A combination of the first and second embodiments described above can also be implemented.

  Further, the data conversion process is not limited to the present embodiment, and for example, an aspect ratio conversion process can be considered.

  In the first and second embodiments, the description has been made on the assumption that a low resolution LCD such as a PDA is built in and a high resolution external display device can be connected. It is not limited.

  An object of the present invention is to supply a storage medium storing software program codes for realizing the functions of the above-described embodiments to a system or apparatus, and a computer (or CPU, MPU, or the like) of the system or apparatus as a storage medium. This can also be achieved by reading and executing the stored program code.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

  Examples of the storage medium for supplying the program code include a floppy (registered trademark) disk, a hard disk, a magneto-optical disk, a CD-ROM, a CD-R, a CD-RW, a DVD-ROM, a DVD ± R, and a DVD. -RAM, DVD ± RW, magnetic tape, nonvolatile memory card, etc. can be used. Alternatively, the program code may be downloaded via a network.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) running on the computer based on the instruction of the program code. A case where part or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing is also included.

  Further, after the program code read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. This includes the case where the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but the OS running on the computer based on the instruction of the program code is actually used. Needless to say, the present invention also includes a case where the functions of the above-described embodiments are realized by performing part or all of the processing, and the processing.

  In this case, the program is supplied by downloading directly from a storage medium storing the program or from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like.

It is a block diagram which shows the hardware constitutions of the display control apparatus which concerns on the 1st Embodiment of this invention. The timing chart at the time of displaying an image on the internal display 109 and the external display 110 is shown. FIG. 3 is a flowchart showing image display processing. It is a flowchart which shows an image display process. It is a block diagram which shows the hardware constitutions of the display control apparatus which concerns on the 2nd Embodiment of this invention. The timing chart when a cutout area does not change is shown. The timing chart when a cutout area changes is shown. It is a flowchart which shows an image display process. FIG. 5 is a block diagram illustrating an internal configuration of a cutout area changing unit 301 in FIG. 4. 6 is a flowchart illustrating processing executed by a cutout area changing unit 301.

Explanation of symbols

101 register setting unit 102 memory control unit 103 frame buffer 104 timing control unit 105 resolution conversion unit 106, 107 format conversion / timing adjustment unit 109 internal display unit 110 external display unit 301 cutout region change unit 302 cutout processing unit

Claims (13)

In a display control device connected to a plurality of displays with different resolutions,
A single frame memory storing at least one display data and shared by the plurality of displays;
First output means for outputting display data read from the frame memory to a first display device having a high resolution;
Display data conversion means for performing a predetermined conversion process on the read display data;
Second output means for outputting the display data converted by the display data conversion means to a second display having a low resolution;
A display control apparatus comprising: control means for controlling display data output to the first and second displays by a timing signal transmitted to the display.   The display control apparatus according to claim 1, wherein the display data conversion unit performs resolution conversion.   The display control apparatus according to claim 1, wherein the display data conversion unit performs a clipping process.   When the display area is changed with respect to the second display, the synchronization signal control means for keeping the change in the period of the horizontal and vertical synchronization signals output to the second display within a predetermined range. The display control apparatus according to claim 1, further comprising:   The display control apparatus according to claim 1, wherein the display data conversion unit performs an aspect ratio conversion process.   The display control apparatus according to claim 1, wherein the control unit simultaneously transmits a clock signal, a horizontal synchronization signal, and a vertical synchronization signal as the timing signal. In a display control method of a display control device connected to a plurality of displays having different resolutions,
A first output step of reading display data from a single frame memory shared by the plurality of displays and outputting it to a first display having a high resolution;
A display data conversion step of performing a predetermined conversion process on the read display data;
A second output step of outputting the display data converted in the display data conversion step to a second display having a low resolution;
And a control step of controlling display data output to the first and second display devices by a timing signal transmitted to the display device.   The display control method according to claim 7, wherein the display data conversion step performs resolution conversion.   The display control method according to claim 7, wherein the display data conversion step performs a clipping process.   When the display area is changed with respect to the second display, a synchronization signal control step for keeping the change in the period of the horizontal and vertical synchronization signals output to the second display within a predetermined range. The display control method according to claim 7, further comprising:   The display control method according to claim 7, wherein the display data conversion step performs an aspect ratio conversion process.   The display control method according to claim 7, wherein the timing signal is a clock signal, a horizontal synchronization signal, and a vertical synchronization signal transmitted simultaneously.   A computer-readable program for causing a computer to execute the display control method according to any one of claims 7 to 12.

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