JP5125205B2 - Data signal processing device, image processing device, image output device, and data signal processing method - Google Patents

Description

  The present invention relates to a data signal processing device, an image processing device, an image output device, and a data signal processing method.

  In electronic devices that handle data signals, there are cases where a plurality of types of buses that operate according to different protocols are used. For example, an image processing apparatus inside a projector includes a general-purpose processor such as a CPU and a special-purpose processor such as an image processing circuit. One bus used for data communication by the general-purpose processor and another bus used by the image processing circuit for input / output of image data operate according to different protocols.

  In such a case, when image data handled by a general-purpose processor is transmitted to a special-purpose processor, it is necessary to convert a data signal transmitted on one bus into a data signal transmitted on another bus. Here, a technique is known in which a general-purpose processor expands image data on a memory connected to one bus, and a conversion circuit reads the expanded image data and converts a data signal. (For example, patent document 1).

Japanese Patent Laid-Open No. 2001-45458 JP-A-10-6577

  However, in the above prior art, it is necessary to secure a memory area for developing image data for data signal conversion. Such a problem is not limited to the case of handling image data, but is a problem common to the case of converting a data signal according to a bus protocol.

In order to solve at least a part of the problems described above , the data signal processing device according to the first aspect includes a first bus that transmits a data signal according to a first protocol in synchronization with a predetermined clock signal. A second bus for transmitting a data signal according to a second protocol in synchronization with the clock signal, and a register, and the first data signal transmitted on the first bus is transmitted on the second bus A conversion unit that converts the second data signal to be transmitted to the second data signal, and the conversion unit is read from a read-only storage unit and is synchronized with the clock signal via the first bus. The first data signal written sequentially to the second data signal is sequentially converted into the second data signal in synchronization with the clock signal and output to the second bus, and also synchronized with the clock signal of one cycle. The first data signal when the number of bits of the first data signal written to the register differs from the number of bits of the second data signal output in synchronization with the clock signal of one cycle. Or the output frequency of the second data signal is adjusted. In addition, the present invention can be realized as the following forms or application examples.

  A first application example of the present invention provides a data signal processing device. A data signal processing device according to a first application example includes a first bus that transmits a data signal according to a first protocol, a second bus that transmits a data signal according to a second protocol, and the first bus. A conversion unit that converts a first data signal transmitted over to a second data signal transmitted over the second bus, the conversion unit via the first bus The supply of the first data signal is received, and the second data signal is output to the second bus in synchronization with the supply of the first data signal.

  In the data signal processing device according to the first application example, the conversion unit converts the first data signal supplied via the first bus into a second data signal in synchronization with the supply. Output to bus No.2. Accordingly, since the first data signal can be converted into the second data signal without being developed in the memory device, the first data signal can be efficiently converted into the second data signal while saving memory resources and the like. Can do.

  In the data signal processing device according to the first application example, the conversion unit includes a register, and the conversion unit is sequentially written into the register in synchronization with a clock signal via the first bus. One data signal may be sequentially converted into the second data signal in synchronization with the clock signal and output to the second bus. In this way, the first data signal can be efficiently converted into the second data signal only by temporarily holding the first data signal in a register having a small capacity.

  In the data signal processing device according to the first application example, the number of bits of the register may be equal to the bus width of the data bus in the first bus. In this way, the first data signal can be efficiently converted into the second data signal only by temporarily holding the first data signal in the small-capacity register.

  In the data signal processing device according to the first application example, the number of bits of the first data signal written to the register in synchronization with one cycle of the clock signal and the number of bits of the first data signal output in synchronization with the one cycle of the clock signal When the number of bits of the second data signal is different, the conversion unit may adjust the writing frequency of the first data signal or the output frequency of the second data signal. In this case, the number of bits of the first data signal written to the register in synchronization with the one-cycle clock signal is different from the number of bits of the second data signal output in synchronization with the one-cycle clock signal. Even so, the writing of the first data signal and the output of the second data signal can be synchronized.

  In the data signal processing device according to the first application example, the first bus is a general-purpose data bus that transmits a bit data signal, and the second bus is a dedicated data bus that transmits a specific type of data signal. It may be. In this way, it is possible to efficiently transfer specific types of data from the general-purpose data bus to the dedicated data bus.

  In the data signal processing device according to the first application example, the first data signal is a bit data signal representing image data, and the second data signal transmits the image data together with a control signal in units of pixels. It may be a video data signal. In this way, the bit data signal representing the image data can be converted into a video data signal and efficiently transferred from the first bus to the second bus.

  In the data signal processing device according to the first application example, the control signal includes a data enable signal, and the conversion unit enables the data enable signal when outputting the image data to the second bus. May be. The control signal may include an image synchronization signal, and the conversion unit may output the image synchronization signal in accordance with control of a transmission source of the first data signal.

  In the data signal processing device according to the first application example, the control signal includes an image synchronization signal, and the conversion unit outputs the image synchronization signal according to control of a transmission source of the first data signal. Also good. Thus, a video data signal including an image synchronization signal can be easily generated.

  In the data signal processing device according to the first application example, the control signal includes an image synchronization signal, and the conversion unit is configured to output the image based on address information specified as a write destination of the first data signal. A synchronization signal may be output. In this way, the video data signal including the image synchronization signal can be generated without the sender of the first data signal performing a special operation.

  The present invention can be implemented in various modes in addition to the application examples described above. For example, the present invention is realized as an image processing apparatus including a data signal processing apparatus and an image processing circuit that receives image data as the second data signal via the second bus. Further, the present invention can be realized as an image output device that includes such an image processing device and outputs an image based on an output signal of the image processing device.

  In addition to the above-described aspect of the present invention, the present invention provides a first bus that transmits a data signal according to the first protocol, a second bus that transmits a data signal according to the second protocol, and a conversion unit. It can be implemented as a method invention such as a data signal processing method in an apparatus comprising: Furthermore, the present invention can be realized in the form of a computer program that causes a computer to implement the above apparatus or method, a recording medium that records the computer program, a data signal that includes the computer program and is embodied in a carrier wave, and the like. it can.

  Hereinafter, embodiments of the present invention will be described based on examples with reference to the drawings.

A. First embodiment:
・ Projector configuration:
A configuration of a projector as an image output apparatus according to the first embodiment will be described with reference to FIGS. FIG. 1 is a block diagram showing the configuration of the projector in the first embodiment. FIG. 2 is a block diagram showing the internal configuration of the video signal output unit in the first embodiment. FIG. 3 is a block diagram showing the internal configuration of the data converter in the first embodiment.

  The projector 100 includes an illumination optical system 150, a liquid crystal panel 160, and a projection optical system 170. Illumination light emitted from the illumination optical system 150 passes through the liquid crystal panel 160 and is modulated into image light representing an image. The image light is projected on the screen 20 by the projection optical system 170, whereby an image is displayed on the screen 20.

  The projector 100 further includes an A / D conversion unit 111, a video signal output unit 112, an image processing circuit 113, a liquid crystal panel driving unit 114, a central processing circuit (CPU) 115, and a read only memory (ROM) 116. And a random access memory (RAM) 117.

  The video signal output unit 112, the image processing circuit 113, the liquid crystal panel driving unit 114, the central processing circuit (CPU) 115, the read only memory (ROM) 116, and the random access memory (RAM) 117 are SOC ( It is integrated in one semiconductor device called “System On a Chip”. Each component 112 to 117 of the SOC operates in synchronization with a common clock signal CLK (not shown).

  Each component 112 to 117 of the SOC is connected to each other via the general-purpose bus 101. The general-purpose bus 101 is a so-called “on-chip bus” used to connect various blocks inside a system LSI such as an SOC. For example, an AHB (Advanced High-Performance) defined by the AMBA (registered trademark) standard is used. Bus) is used. The general-purpose bus 101 is a general-purpose bus capable of transmitting various bit data, and can perform bidirectional communication according to a protocol defined by the above-described AMBA standard. The general-purpose bus 101 will be further described later.

  On the other hand, between the A / D converter 111 and the video signal output unit 112, between the video signal output unit 112 and the image processing circuit 113, and between the image processing circuit 113 and the liquid crystal panel driving unit 114, respectively, video buses 102a and 102b. , 102c. The video buses 102a to 102c are dedicated buses for transmitting so-called digital video signals, and perform one-way communication for transmitting digital video signals in the direction indicated by arrows in FIG. The digital video signal is a digital signal representing image data such as a moving image or a still image. The protocol of the video buses 102a to 102c for transmitting digital video signals is simple as will be described below. A circuit (for example, the video signal output unit 112) that transmits a digital video signal via the video buses 102a to 102c transmits a pulse of the vertical synchronization signal VS immediately before or simultaneously with the start of transmission of image data, and pixel data. Send pixel data to the bus. The circuit that transmits the digital video signal enables the enable signal DE while transmitting valid pixel data (in this embodiment, it is set to a high signal). A circuit (for example, the image processing circuit 113) that receives the digital video signal recognizes that new image data is transmitted by receiving the pulse of the vertical synchronization signal VS, and enables it at the rising edge of each clock. When the signal DE is valid (high signal in this embodiment), the signal appearing on the pixel data bus at that time is acquired as valid pixel data.

  The A / D converter 111 performs A / D conversion on an input image signal input via a cable 10 from a DVD player or a personal computer (not shown) as necessary, and converts the digital video signal via the video bus 102a. To the video signal output unit 112.

  The video signal output unit 112 is a block for transmitting a digital video signal to the image processing circuit 113. The video signal output unit 112 can transmit the digital video signal transmitted from the video signal output unit 112 to the image processing circuit 113 via the video bus 102b, and can also transmit the image data transmitted from the CPU 115 to the digital video signal. Can be transmitted to the image processing circuit 113 via the video bus 102b.

  The image processing circuit 113 performs image processing for adjusting the image represented by the digital video signal on the digital video signal transmitted from the video signal output unit 112, and transmits the digital video signal after the image processing via the video bus 102c. To the liquid crystal panel driving unit 114. The image processing to be executed includes, for example, adjustment processing of brightness, contrast, hue, and the like, processing for correcting image distortion such as trapezoidal distortion, and so-called OSD (on-screen display) processing for displaying various setting items on the screen. Is included. The image processing circuit 113 of the present embodiment is connected to both the general-purpose bus 101 and the video bus 102b as shown in FIG. 1, but exchanges control data via the general-purpose bus 101 to perform image processing. The target image data has specifications that can be received only in the form of a digital video signal via the video bus 102b. Therefore, as will be described later, when the CPU 115 sends image data stored in the ROM 116 or the like to the image processing circuit 113, the image data is transmitted by the CPU 115 to the video signal output unit 112 via the general-purpose bus 101. The video signal output unit 112 converts the digital video signal into a digital video signal and sends the digital video signal to the image processing circuit 113 via the video bus 102b.

  The liquid crystal panel driving unit 114 drives the liquid crystal panel 160 based on the digital video signal transmitted from the image processing circuit 113. As a result, an image represented by the digital video signal is formed on the liquid crystal panel 160 and a desired image is projected on the screen 20.

  The CPU 115 executes a control program stored in the ROM 116, and controls the entire projector 100, for example, the video signal output unit 112, the image processing circuit 113, and the liquid crystal panel driving unit 114 described above. Further, the CPU 115 transmits the image data stored in the ROM to the image processing circuit 113 in the form of a digital video signal via the video signal output unit 112, and displays an image represented by the image data on the screen 20. it can. Such processing will be described later.

  The RAM 117 is used by the CPU 115 and the image processing circuit 113 for temporarily storing calculation results and image data.

  Next, the configuration of the video signal output unit 112 will be further described. As shown in FIG. 2, the video signal output unit 112 includes a data conversion unit 120 and a multiplexer 130. The data conversion unit 120 converts the image data transmitted from the CPU 115 via the general-purpose bus 101 into a digital video signal, and transmits the digital video signal to the video signal output unit 112 via the video bus 102d. The video bus 102d is a dedicated bus for transmitting digital video signals similar to the video buses 102a to 102c described above. The multiplexer 130 selects one of the digital video signal transmitted from the video signal output unit 112 via the video bus 102a and the digital video signal transmitted from the data conversion unit 120 via the video bus 102d. Then, the data is transmitted to the image processing circuit 113 via the video bus 102b. Which digital video signal is selected is controlled by a control signal CS transmitted from the CPU 115.

  Before further describing the data conversion unit 120, the general-purpose bus 101 and the video buses 102a to 102d will be further described with reference to FIG.

  The general-purpose bus 101 includes an address bus 1011 for transmitting addresses, a data bus 1012 for transmitting data, and a control bus 1013 for transmitting control signals. In the present embodiment, the address bus 1011 and the data bus 1012 are parallel buses each having a 32-bit bus width. The control bus 1013 is used for transmission / reception of a predetermined control signal defined in the protocol of the general-purpose bus 101, but will not be described in detail because it is not necessary for the description of the first embodiment.

  Video buses 102a-102d include a 24-bit pixel data bus 1022, an enable signal line 1021, and a vertical sync signal line 1023, as shown for video bus 102d in FIG. The video buses 102a to 102d may further include a horizontal synchronizing signal line 1024 as indicated by a wavy line in FIG. A configuration including the horizontal synchronization signal line 1024 will be described later as a modified example. The pixel data bus 1022 is a parallel bus having a bus width of 24 bits. The 24-bit bus width of the pixel data bus 1022 is assigned 8 bits for each of the red (R), green (G), and blue (B) signals, and the pixel data bus 1022 has 8 bits for each of RGB. Is used to transmit pixel data represented by the pixel unit.

  Based on the above, the internal configuration of the data conversion unit 120 will be further described. As shown in FIG. 3, the data conversion unit 120 includes an address decoder 121 and a conversion processing unit 122.

  The address decoder 121 includes an address register M4 connected to the address bus 1011 of the general-purpose bus 101.

  The conversion processor 122 includes a data register M1, a command register M2, and a synchronization signal generator M3. One of the data register M1 and the command register M2 is connected to the data bus 1012 of the general-purpose bus 101 in accordance with a selection signal SEL transmitted from the address decoder 121. The data register M1 is connected to the pixel data bus 1022 of the video bus 102d. The synchronization signal generator M3 is connected to the vertical synchronization signal line 1023 of the video bus 102d.

Operation of Data Conversion Unit The operation of the data conversion unit 120 will be described with reference to FIGS. 4 and 5 in addition to FIG. FIG. 4 is a timing chart for explaining the operation of the data converter in the first embodiment. FIG. 5 is a diagram for explaining writing to the data register M1 and output from the data register M1 in the first embodiment. 4 shows a clock signal CLK, an address signal AD output from the CPU to the address bus 1011 of the general-purpose bus 101, a write data signal WD output from the CPU 115 to the data bus 1012 of the general-purpose bus 101, and a video from the data conversion unit 120. A pixel data signal DTout output to the pixel data bus 1022 of the bus 102d, an enable signal DE output from the data conversion unit 120, and a vertical synchronization signal VS output from the synchronization signal generation unit M3 of the data conversion unit 120 are illustrated. ing. For convenience of explanation, as shown in the uppermost part of FIG. 4, the clock signal CLK shown in FIG. 4 is denoted by a symbol for each cycle, and each clock period is represented by a symbol as clock CLK1, clock CLK2,. Call it. This is the same for other timing charts (FIGS. 9, 12, 14, and 15) described later.

  An example will be described in which the 10 CPU 115 of the conversion processing unit 122 reads out image data representing an image of m + 1 pixel in the vertical direction × n + 1 pixel in the horizontal direction from the ROM 116 and transmits it to the data conversion unit 120. The image data is composed of pixel data of coordinates (0, 0) to (m, n), and each pixel data is 24-bit data composed of 8 bits for each of RGB. The pixel data at the coordinates (a, b) is represented as D (a, b). In the following, expressions such as “write pixel data sequentially” will be used. Here, the order in the case of “sequentially” may be a predetermined order, but in this embodiment, the order generally used for digital video signals is used. In other words, tracing the horizontal columns from the left side to the right side is an order in which the uppermost column is repeated one by one up to the lowermost column.

  First, the CPU 115 writes a command VSC for instructing generation of a vertical synchronization signal to the command register M2 according to the protocol of the general-purpose bus 101, and then sequentially writes pixel data constituting image data to the data register M1. . Specifically, the CPU 115 outputs an address ADM2 designating a predetermined command register M2 on the address bus 1011 as the address signal AD from the clock CLK1 to the rising edge of the clock CLK2. The CPU 115 further outputs a command VSC as a data signal WD onto the data bus 1012 from the clock CLK2 to the rising edge of the clock CLK3. At the same time, that is, from the clock CLK2 to the rising edge of the clock CLK3, the CPU 115 outputs the address ADM1 designating the predetermined data register M1 on the address bus 1011 as the address signal AD. Subsequently, the CPU 115 outputs the first pixel data D (0, 0) on the data bus 1012 as the data signal WD from the clock CLK3 to the rising edge of the clock CLK4. Further, the CPU 115 sequentially outputs the pixel data to the data bus 1012 by one pixel every clock cycle while outputting the address ADM1 to the address bus 1011 after the clock CLK2.

  As a result, the address decoder 121 of the data conversion unit 120 recognizes that the address ADM2 is written in the address register M4 at the rising edge of the clock CLK2, and transmits the selection signal SEL corresponding to the address ADM2 to the conversion processing unit 122. To do. When receiving the selection signal SEL, the conversion processing unit 122 connects the command register M2 corresponding to the address ADM2 to the data bus 1012. Then, the command VSC is written into the command register M2 of the conversion processing unit 122, and the conversion processing unit 122 recognizes the command VSC at the rising edge of the clock CLK3, and immediately generates the vertical synchronization signal VS at the clock CLK3. In FIG. 4, a negative pulse appearing in the clock CLK3 indicates the generated vertical synchronization signal VS. The address decoder 121 recognizes that the address ADM1 is written in the address register M4 at the rising edge of the clock CLK3, and transmits the selection signal SEL corresponding to the address ADM1 to the conversion processing unit 122. When receiving the selection signal SEL, the conversion processing unit 122 connects the data register M1 corresponding to the address ADM1 to the data bus 1012. As a result, the pixel data D (0, 0) is written in the data register M1 of the conversion processing unit 122. The conversion processing unit 122 recognizes the pixel data D (0, 0) at the rising edge of the clock CLK4, and immediately outputs the pixel data D (0, 0) as the pixel data signal DTout on the pixel data bus 1022 at the clock CLK4. To do. Further, the conversion processing unit 122 outputs pixel data D (0, 0) on the pixel data bus 1022 and simultaneously outputs an enable signal DE indicating validity to the enable signal line 1021. In this embodiment, the enable signal DE indicating validity is a high signal.

  After the clock CLK2, the address ADM1 is written to the address register M4 for all pixel data in the clock period immediately before the pixel data is written to the data register M1. While the address ADM1 is written to the address register M4, the data bus 1012 is connected to the data register M1. After the clock CLK4, the conversion processing unit 122 of the data conversion unit 120 outputs the pixel data written in the data register M1 to the pixel data bus 1022 sequentially in the clock cycle at the rising edge of each clock cycle. I will do it. The conversion processing unit 122 always keeps the enable signal DE valid in the clock cycle for outputting the pixel data.

  As described above, the digital video signal including the pixel data signal DTout and the enable signal DE indicating the validity is output from the conversion processing unit 122 in synchronization with the CPU 115 writing the image data as the data signal WD to the data register M1. The As shown in FIG. 5, a data bus 1012 for transmitting a data signal WD can transmit 32-bit bit data in one clock, but the CPU 115 is a data register for each pixel of image data in one clock. Write to M1. That is, the CPU 115 writes 24-bit pixel data D (a, b) (a and b are integers of 0 ≦ a ≦ m and 0 ≦ b ≦ n) into the data register M1 in one clock. Specifically, the 24-bit pixel data D (a, b) is transmitted using the upper 24 bits of the data bus 1012, and the lower 8 bits of the data bus 1012 become invalid data (FIG. 5). The conversion processing unit 122 outputs the bit data written in the data register M1 via the upper 24 bits of the data bus 1012 as it is to the pixel data bus 1022 having a 24-bit bus width. The data register M1 may be a register that holds 32 bits including invalid data, or may be a register that holds only the upper 24 bits.

  The writing of the image data to the data register M1 and the output of the digital video signal from the conversion processing unit 122 are synchronized, and when the CPU 115 stops the writing of the image data, the conversion processing unit 122 of the data conversion unit 120 is digital. The output of the video signal is stopped, and the enable signal DE is disabled (low signal).

  According to the present embodiment described above, when the image data handled by the CPU 115 is converted into a digital video signal and output onto the video bus 102d, the CPU 115 stores the image data on the data register M1 via the general-purpose bus 101. When written, the image data is converted and output from a format (general bit data) transmitted on the general-purpose bus 101 to a format (digital video signal) transmitted on the video bus 102d in synchronization with the writing. The As a result, the projector 100 according to the present embodiment can save the memory resources of the RAM 117 and the bus bandwidth for accessing the RAM 117.

  For ease of understanding, an example of a projector having a conventional configuration will be described as a comparative example with reference to FIG. FIG. 6 is a diagram illustrating a schematic configuration of a projector according to a comparative example. In FIG. 6, a configuration until image data is transmitted from the CPU 115 to the image processing circuit 113 is selectively illustrated, and other configurations such as a liquid crystal panel drive unit and an illumination optical system are not illustrated.

  In the projector 1000 according to the comparative example, a development area 1171 for developing image data is secured in the RAM 117. The projector 1000 according to the comparative example includes a data reading unit 1200 instead of the data conversion unit 120 of the projector 100 according to the example. Since the other configuration is the same as the configuration of the projector 100 according to the embodiment, the same components in FIG. 6 are denoted by the same reference numerals as those in FIG.

  An operation in which the CPU 115 transmits image data to the image processing circuit 113 in the projector 1000 according to the comparative example will be described. First, the CPU 115 reads out image data to be displayed from the ROM 116 and develops the image data in a development area 1171 of the RAM 117. The right side of FIG. 6 conceptually shows a state where image data is developed in the development area 1171. As shown in FIG. 6, the development area 1171 needs to have a capacity corresponding to the size of pixel data × the number of pixels of image data. When the image data is expanded in the expansion area 1171, the CPU 115 causes the data reading unit 1200 to convert the image data expanded on the expansion area 1171 into a digital video signal and output it to the image processing circuit 113. Instruct. Upon receiving an instruction from the CPU 115, the data reading unit 1200 sequentially reads image data from the development area 1171 from the top pixel, generates a digital video signal, and outputs the digital video signal onto the video bus 102b. As described above, the writing of the image data to the development area 1171 by the CPU 115 and the output of the digital video signal to the video bus 102b by the data reading unit 1200 are performed asynchronously.

  In this embodiment, since it is not necessary to develop image data on the RAM 117, it can be understood that the memory resources of the RAM 117 and the bus bandwidth for accessing the RAM 117 can be saved. As a result, it is possible to improve the performance of the SOC, and consequently the performance of the projector 100 as a whole.

  Further, the conventional data reading unit 1200 needs to access the RAM 117 to read out image data and output a digital video signal. However, the data conversion unit 120 in this embodiment uses the data register M1 and the command register M2 by the CPU 115. When a data is written in, a digital video signal is output in synchronization with the writing, so that it can be realized with a simple configuration including a small-capacity register and a simple logic, and suppresses the SOC integration area and power consumption. be able to.

B. Second embodiment:
A second embodiment will be described with reference to FIGS. FIG. 7 is a block diagram showing the internal configuration of the data converter in the second embodiment. FIG. 8 is a diagram conceptually showing an address map recognized by the CPU in the second embodiment. FIG. 9 is a timing chart for explaining the operation of the data converter in the first embodiment.

  The projector according to the second embodiment includes a data converter 120a instead of the data converter 120 of the projector 100 according to the first embodiment. Since the other configuration of the projector in the second embodiment is the same as that of the projector 100 in the first embodiment described with reference to FIGS. 1 and 2, the same components will be described below with reference to FIGS. The same reference numerals are used and the description thereof is omitted.

  As shown in FIG. 7, the data conversion unit 120a in the second embodiment includes an address decoder 121a and a conversion processing unit 122a.

  Similar to the address decoder 121 in the first embodiment, the address decoder 121a is connected to the address bus 1011 and includes an address register M4. The address decoder 121a transmits a read enable signal RE and a synchronization signal generation instruction signal VSE to the conversion processing unit 122a in order to control the conversion processing unit 122a.

  Similar to the conversion processing unit 122 in the first embodiment, the conversion processing unit 122a includes a data register M1 and a synchronization signal generation unit M3. On the other hand, unlike the conversion processing unit 122 in the first embodiment, the conversion processing unit 122a does not include the command register M2. The data register M1 is connected to the data bus 1012 of the general-purpose bus 101 and to the pixel data bus 1022 of the video bus 102d. The synchronization signal generator M3 is connected to the vertical synchronization signal line 1023 of the video bus 102d.

  Next, the operation of the conversion processing unit 122a will be described. The CPU 115 conceptually recognizes an address map AM as shown in FIG. The CPU 115 recognizes this address map AM as a memory area for developing image data representing an image of m + 1 pixel in the vertical direction × n + 1 pixel in the horizontal direction. As shown in FIG. 8, the head address for storing the pixel data D (a, b) constituting the image data is called A (a, b). The address decoder 121a of the conversion processing unit 122a recognizes the same address map AM.

  The CPU 115 sequentially writes pixel data constituting image data in the data register M1 in accordance with the protocol of the general-purpose bus 101. Specifically, the CPU 115 sets the address A (0, 0) for writing the first pixel data D (0, 0) to the command register M2 as the address signal AD on the address bus 1011 from the clock CLK1 to the rising edge of the clock CLK2. Output to. The CPU 115 further outputs the pixel data D (0, 0) as the data signal WD onto the data bus 1012 from the clock CLK2 to the rising edge of the clock CLK3. Further, after the clock CLK2, the CPU 115 sequentially outputs the address A (a, b) for writing each pixel data on the address bus 1011 in each clock cycle, and the next clock for writing the address A (a, b). In a cycle, pixel data D (a, b) corresponding to the written address A (a, b) is sequentially output onto the data bus 1012 one pixel at a time.

  When the address decoder 121a of the data converter 120a recognizes that any of the addresses A (0,0) to A (m, n) recognized by the address map AM is written in the address register M4, The read enable signal RE is validated to notify that valid data is written to the data register M1. When the address decoder 121a further recognizes that the address A (0, 0) of the first pixel is written in the address register M4, the address decoder 121a validates the synchronization signal generation instruction signal VSE.

  When the conversion processing unit 122a recognizes the pixel data D (a, b) written in the data register M1 at the rising edge of the clock, the conversion processing unit 122a immediately uses the pixel data D (a, b) as the pixel data signal DTout at the clock. The data is output onto the pixel data bus 1022. Further, the conversion processing unit 122 a outputs D (a, b) on the pixel data bus 1022 and simultaneously outputs an enable signal DE (high signal) indicating validity to the enable signal line 1021.

  Further, when the pixel data written in the data register M1 is the top pixel data D (0, 0), the conversion processing unit 122a receives the pixel data D (0, 0) and an enable signal DE indicating validity. Simultaneously with the output, a pulse of the vertical synchronization signal VS is output on the vertical synchronization signal line 1023. The conversion processor 122a can recognize from the synchronization signal generation instruction signal VSE transmitted from the address decoder 121a that the pixel data written in the data register M1 is the pixel data D (0, 0).

  As a result, as shown in FIG. 9, the digital video signal is output to the video bus 102d in synchronization with the writing of the image data by the CPU 115. In this embodiment, at the clock CLK3, the top pixel data D (0, 0) is output onto the pixel data bus 1022, and at the same time, the enable signal DE rises and a pulse of the vertical synchronization signal VS is output ( FIG. 9). Thereafter, as in the first embodiment, the image data is sequentially output together with an enable signal DE indicating validity in units of pixel data.

  According to the second embodiment described above, the following actions and effects are produced in addition to the actions and effects similar to those of the first embodiment. In the second embodiment, the vertical synchronization signal VS is automatically generated when the top pixel data D (0, 0) is written by designating the top pixel address A (0, 0). As in the first embodiment, it is not necessary to write the command VSC to the command register M2 prior to writing the image data to the data register M1. As a result, the CPU 115 can obtain the same effect as that of the first embodiment without performing a special operation to generate the vertical synchronization signal VS.

C. Third embodiment:
A third embodiment will be described with reference to FIGS. FIG. 10 is a block diagram showing the internal configuration of the data converter in the third embodiment. FIG. 11 is a block diagram showing the internal configuration of the bit conversion unit in the third embodiment. FIG. 12 is a timing chart for explaining the operation of the data converter in the third embodiment. FIG. 13 is a diagram conceptually showing the output contents of each data register in the third embodiment.

  The projector in the third embodiment includes a data converter 120b instead of the data converter 120 of the projector 100 in the first embodiment. Since the other configuration of the projector in the third embodiment is the same as that of the projector 100 in the first embodiment described with reference to FIGS. 1 and 2, the same components will be described below with reference to FIGS. The same reference numerals are used and the description thereof is omitted.

  As shown in FIG. 10, the data conversion unit 120b in the third embodiment includes an address decoder 121 and a conversion processing unit 122b.

  Since the address decoder 121 is the same as the address decoder 121 in the first embodiment, the description thereof is omitted.

  Similar to the conversion processing unit 122 in the first embodiment, the conversion processing unit 122b includes a command register M2 and a synchronization signal generation unit M3. On the other hand, unlike the conversion processing unit 122 in the first embodiment, the conversion processing unit 122b includes a bit conversion unit M10 instead of the data register M1.

  As shown in FIG. 11, the bit conversion unit M10 includes a first data register M101, a second data register M102, a multiplexer M103, and a control logic M104. Each of the first data register M101 and the second data register M102 is a register capable of holding 32-bit data equal to the bus width of the data bus 1012 in the general-purpose bus 101.

  The first data register M101 is connected to the data bus 1012 of the general-purpose bus 101, and image data is sequentially written by the CPU 115 every 32 bits. The first data register M101 and the second data register M102 are connected by a parallel internal bus having a 32-bit bus width. The 32-bit bit data written to the first data register M101 is configured to be written to the second data register M102 at the clock next to the written clock. As a result, the bit conversion unit M10 holds 64-bit bit data written with two clocks.

  The 64-bit bit data written in the two data registers M101 and M102 of the bit conversion unit M10 is output to the multiplexer M103 via the parallel internal bus at the clock next to the written clock.

  The multiplexer M103 is connected to the pixel data bus 1022. The multiplexer M103 outputs the selected 24-bit bit data on the pixel data bus 1022 in accordance with the status signal STA transmitted from the control logic M104 among the input 64-bit bit data.

  The control logic M104 controls the multiplexer M103 to output appropriate bit data to the pixel data bus 1022 by transmitting a 2-bit status signal STA to the multiplexer M103. Further, the control logic M104 adjusts the writing frequency of image data by the CPU 115 by outputting a standby signal WA for delaying the writing of data to the CPU 115 via the control bus 1013. These processes will be further described later.

Next, the operation of the conversion processing unit 122b will be described. The CPU 115 writes 32-bit image data into the first data register M101 with one clock instead of 24 bits, which is one pixel, with one clock as in the first embodiment. In other words, the CPU 115 transmits image data by effectively using the data bus 1012 having a 32-bit bus width. In this embodiment, 32-bit data written with one clock is divided into the following three types dtype1 to dtype3.
dtype1 = (B _{k + 1} , R _k , G _k , B _k )
_{dtype2 = (G k + 1,} B k + 1, R k, G k)
_{dtype3 = (R k + 1,} G k + 1, B k + 1, R k)
Here, R _k , G _k , and B _k represent 8-bit data representing the red, green, and blue pixel values of the kth pixel of the image data, respectively.

Image data representing an image of m + 1 pixel in the vertical direction × n + 1 pixel in the horizontal direction is divided into 32 bits from the top, and each is set to WD1, WD2,... WDj (j is a natural number) in order from the top. For these 32-bit data WDj, j = 1 to 6 are shown as an example as follows.
WD1 = {B (0,1), R (0,0), G (0,0), B (0,0)} = dtype1WD2 = {G (0,2), B (0,2), R (0,1), G (0,1)} = dtype2
WD3 = {R (0,3), G (0,3), B (0,3), R (0,2)} = dtype3
WD4 = {B (0,5), R (0,4), G (0,4), B (0,4)} = dtype1WD5 = {G (0,6), B (0,6), R (0,5), G (0,5)} = dtype2
WD6 = {R (0,7), G (0,7), B (0,7), R (0,6)} = dtype3
Here, B (a, b) represents bit data of a blue pixel value of pixel data at coordinates (a, b). Pixel data D (a, b) = {R (a, b), G (a, b), B (a, b)}.

  As can be seen from the above, the 32-bit data WDj is a repetition of the above-described three types dtype1 to dtype3. Then, pixel data D (a, b) for four pixels is included in three consecutive 32-bit data WDj. Therefore, if the pixel data D (a, b) is output four times for the writing of the 32-bit data WDj three times, the pixel data D (a, b) is synchronized with the writing of the image data by the CPU 115. ) Including digital video signals can be output.

  More specific description will be given with reference to FIGS. 12 and 13. The CPU 115 writes the command VSC in the command register M2 by the operation described in the first embodiment, generates the vertical synchronization signal VS in the synchronization signal generation unit M3, and then stores the image data in the first data register M101. Write sequentially in 32 bits. Similar to the first embodiment, the address is written in the address register M4 and then the data is written in the first data register M101 according to the protocol of the general-purpose bus 101.

  Since this operation has been described in the first embodiment, the illustration of the address signal AD and the vertical synchronization signal VS is omitted in FIG. In FIG. 12, in addition to the clock signal CLK, the data signal WD, and the enable signal DE, the output 1stR from the first data register M101 to the second data register M102 and the multiplexer M103, and the output from the second data register M102 to the multiplexer M103 2ndR, an output DTout from the multiplexer M103 to the pixel data bus 1022, and a status signal STA transmitted from the control logic M104 to the multiplexer M103 are illustrated.

  For example, the first 32-bit data WD1 written to the first data register M101 as the data signal WD at the clock CLK1 is output from the first data register M101 at the next clock CLK2 (see FIG. 12: 1stR), and further It is output from the second data register M102 at the clock CLK3 (see FIG. 12: 2ndR).

  Each time the 32-bit data WDj is written three times, the control logic M104 generates a valid standby signal WA (low signal in this embodiment) for one clock period and transmits it to the CPU 115 (FIG. 12: WA). reference). In the protocol of the general-purpose bus 101 of this embodiment, when the data transmission side (CPU 115 in this embodiment) receives a valid standby signal WA from the reception side, it delays transmission of the data signal WD representing the next data. The data signal WD representing the currently transmitted data is maintained on the data bus 1012. When the CPU 115 receives a valid standby signal WA while transmitting certain 32-bit data WDj, the CPU 115 delays transmission of the next 32-bit data WDj + 1 according to the protocol of the general-purpose bus 101, and transfers the 32-bit data WDj on the data bus 1012. To maintain.

  For example, in the example shown in FIG. 12, since a valid standby signal WA is generated from the clock CLK3 to the rising edge of the clock CLK4, the CPU 115 recognizes this standby signal WA at the rising edge of the clock CLK4. The next 32-bit data WD4 is not transmitted, and the 32-bit data WD3 is maintained on the data bus 1012 (see FIG. 12: WA and WD).

  13A to 13E show the specific contents of the 32-bit output 1stR of the first data register M101 and the 32-bit output 2ndR of the second data register M102 in the example shown in FIG. Each clock period of .about.CLK6 is shown. In each of FIGS. 13A to 13E, the bit data surrounded by a thick line is selected by the multiplexer M103 from the 64-bit outputs of the two data registers M101 and M102, and the pixel data is used as the pixel data signal DTout. The bit data of 24 bits (one pixel) output on the bus 1022 is shown.

  There are four types of patterns for selecting and outputting 24 bits out of the 64-bit outputs of the two data registers M101 and M102, and these four types of patterns are repeated. In FIGS. 13A to 13E, the portions indicated by bold lines indicate 24 bits output in the corresponding clock. FIGS. 13A to 13D show four different patterns, respectively, and FIG. 13E is the same pattern as FIG. 13A. As described above, the status signal STA for controlling the multiplexer M103 is a 2-bit signal and can take four types of values. The four types of values of the status signal STA respectively indicate four types of selection / output patterns to the multiplexer M103. 12 and 13, four types of values of the status signal STA are represented by 0 to 3. The status signal STA is sequentially switched each time the pixel data D (a, b) for one pixel is output as the pixel data signal DTout, and the above four types of values are repeated (see FIG. 12: STA). ).

  Through the operation described above, it can be seen that pixel data for four pixels is output on the pixel data bus 1022 of the video bus 102d as the pixel data signal DTout in synchronization with the writing of 32-bit data by the CPU 115 three times ( FIG. 12, FIG. 13: Refer to DTout).

  According to the third embodiment described above, the following actions and effects are produced in addition to the actions and effects similar to those of the first embodiment. When developing image data on the RAM, it is a normal operation to send the image data to the RAM using the entire width of the data bus, instead of flowing the data to the bus in units of pixels. In this embodiment, the CPU 115 can be allowed such normal operation. Further, the control logic M104 provided in the bit conversion unit M10 of the data conversion unit 120 adjusts the writing frequency of the image data by the CPU 115 by transmitting the standby signal WA to the CPU 115. As a result, even when the bus width of the data bus 1012 of the general-purpose bus 101 is different from the bus width of the pixel data bus 1022 of the video signal, the output of the digital video signal and the writing of the image data by the CPU 115 are synchronized. Can take. The process related to the standby signal WA is a process defined by a protocol of a bus connected to the CPU such as the general-purpose bus 101 (for example, a protocol defined by the AMBA standard), and the CPU 115 operates according to the protocol of the general-purpose bus 101. Just do it. Therefore, the CPU 115 only needs to perform the same processing as that for developing image data in the RAM 117 as in the prior art. As a result, the CPU 115 can obtain the same effect as that of the first embodiment without performing a special operation such as data transmission in units of pixels in order to convert image data into a digital video signal.

D. Variations:
In each of the embodiments described above, the digital video signal includes only the vertical synchronization signal VS as the synchronization signal, because the protocol of the video buses 102a to 102d uses only the vertical synchronization signal VS. When using a video bus having a protocol that requires the horizontal synchronization signal HS, the data conversion unit is preferably configured to generate the horizontal synchronization signal HS.

・ First modification:
One example of the process of generating the horizontal synchronization signal HS will be described as a first modification example with reference to FIG. FIG. 14 is a timing chart for explaining the operation of the data conversion unit in the first modification.

  The configuration of the projector in the first modification is different from the configuration of the projector 100 in the first embodiment in that the video buses 102a to 102d include the horizontal synchronization signal line 1024 as shown by the wavy lines in FIG. Since the other configuration of the projector in the first modification is the same as the configuration of the projector 100 in the first embodiment described with reference to FIGS. 1 to 3, hereinafter, the first embodiment will be described with respect to the same components. The same names and symbols are used, and the description thereof is omitted.

  A specific operation of the data conversion unit 120 in the first modification will be described. The CPU 115 replaces the command VSC instructing the generation of the vertical synchronization signal VS in the first embodiment with the vertical data just before writing the pixel data of the first pixel (coordinate (0, 0)) of the image data into the data register M1. A command HVSC instructing generation of both the synchronization signal VS and the horizontal synchronization signal HS is written to the command register M2 (see FIG. 14: WD). When the command HVSC is written to the command register M2, the synchronization signal generator M3 outputs a pulse of the vertical synchronization signal VS to the vertical synchronization signal line 1023 at the next clock, and the horizontal synchronization signal line 1024 receives the horizontal synchronization signal HS. A pulse is output (see FIG. 14: VS, HS).

  The CPU 115 immediately before writing the pixel data of the first pixel (coordinates (a, 0) (1 ≦ a ≦ m)) of each horizontal pixel column (except the highest column) in the image data into the data register M1. A command HSC instructing generation of only the horizontal synchronizing signal HS is written in the command register M2 (see FIG. 14: WD). When the command HSC is written in the command register M2, the synchronization signal generator M3 outputs a pulse of the horizontal synchronization signal HS to the horizontal synchronization signal line 1024 at the next clock (see HS in FIG. 14).

  Other operations of the CPU 115 and the data converter 120 are the same as those in the first embodiment. According to this modification, even when a video bus having a protocol that requires the horizontal synchronization signal HS is used, the same operation and effect as in the first embodiment can be obtained.

・ Second modification:
Another example of the process of generating the horizontal synchronization signal HS will be described as a second modification example with reference to FIG. FIG. 15 is a timing chart for explaining the operation of the data conversion unit in the second modification.

  The configuration of the projector in the second modification is different from the configuration of the projector in the second embodiment in that the video buses 102a to 102d include the horizontal synchronization signal line 1024 as shown by the wavy lines in FIG. Since the other configuration of the projector in the second modification is the same as that of the projector in the second embodiment shown in FIGS. 1, 2, and 7, hereinafter, the same components will be described below. The same names and symbols as in the second embodiment are used, and the description thereof is omitted.

  A specific operation of the data conversion unit 120a in the second modification will be described. The CPU 115 sequentially writes the image data into the data register M1 by the same operation as in the second embodiment. In this modification, when the address decoder 121a of the conversion processing unit 122a recognizes that the address A (0, 0) of the first pixel is written in the address register M4, both the vertical synchronization signal and the horizontal synchronization signal are generated. Is transmitted to the conversion processing unit 122a. As a result, when the pixel data written in the data register M1 is the first pixel data D (0, 0), the conversion processing unit 122a outputs the pixel data D (0, 0) and the enable signal DE indicating validity. At the same time, a pulse of the vertical synchronizing signal VS is outputted on the vertical synchronizing signal line 1023 and a pulse of the horizontal synchronizing signal HS is outputted on the horizontal synchronizing signal line 1024 (see FIG. 15: VS, HS).

  Further, in the present modification, the address decoder 121a of the conversion processing unit 122a stores the first pixel (coordinates (a, 0) (1)) in the horizontal direction in each pixel column (excluding the highest column) in the image data in the address register M4. If it is recognized that the address A (a, 0) of .ltoreq.a.ltoreq.m)) is written, an instruction signal instructing the generation of only the horizontal synchronizing signal is transmitted to the conversion processing unit 122a. As a result, when the pixel data written in the data register M1 is the top pixel data D (a, 0) of each horizontal pixel column (excluding the highest column), the conversion processing unit 122a Simultaneously with the output of the pixel data D (a, 0) and the enable signal DE indicating validity, the pulse of the horizontal synchronization signal HS is output on the horizontal synchronization signal line 1024 (see HS in FIG. 15).

  The other operations of the CPU 115 and the data converter 120a are the same as in the second embodiment. According to this modification, even when a video bus having a protocol that requires the horizontal synchronization signal HS is used, the same operation and effect as in the second embodiment can be obtained.

・ Third modification:
In the third embodiment, the bit number of the data signal WD on which the image data to be written to the data register M1 by the CPU 115 is 32 bits, and the bit number of the pixel data signal output from the data converter 120b onto the video bus 102d is Although it is 24 bits, the number of bits of these signals is not limited to this. For example, when the image data is composed of 16-bit pixel data composed of 5-bit R data, 6-bit G data, and 5-bit B data, the data conversion unit 120b outputs the data on the video bus 102d. The number of bits of the pixel data signal to be performed is 16 bits per clock.

  In such a case, the CPU 115 writes the image data 32 bits at a time into the 32-bit data register. The control logic of the data conversion unit transmits a pulse of the standby signal WA to the CPU 115 every time the image data is written by the CPU 115 once (for 32 bits). Then, the same 32-bit data is held in the data register for two clock periods. Then, lower 16 bits and upper 16 bits are alternately selected by a multiplexer, and pixel data is divided into two clocks and output onto the video bus 102d by one pixel (16 bits). As described above, when the number of bits of the data signal written to the data register by the CPU 115 is larger than the number of bits of the pixel data signal output from the data converter 120b onto the video bus 102d, the standby signal WA is set to the number of bits of both. The writing frequency of the CPU 115 may be adjusted by generating it according to the ratio, and the writing to the data register by the CPU 115 and the output of the pixel data signal by the data conversion unit 120b may be synchronized.

  Conversely, when the number of bits of the data signal written by the CPU 115 to the data register is smaller than the number of bits of the pixel data signal output from the data converter 120b onto the video bus 102d, the data converter 120b outputs the pixel data signal. It is only necessary to synchronize the writing to the data register by the CPU 115 and the output of the pixel data signal by the data conversion unit 120b by adjusting the frequency of the data conversion. Specifically, the number of bits of the data signal written to the data register by the CPU 115 is 16 bits (for example, when the bus width of the data bus 1012 of the general-purpose bus 101 is 16 bits), and the data conversion unit 120b is connected to the video bus. There are cases where the number of bits of the pixel data signal to be output onto 102d is 32 bits (for example, when the image data is 32-bit data of 8 bits for each of RGB and the bus width of the video bus is 32 bits). is there. In such a case, every time the CPU 115 writes 16-bit data to the data register twice, the data conversion unit 120b may output a pixel data signal for one pixel on the video bus.

-Fourth modification:
In each of the above embodiments, each component such as the CPU 115, the data conversion unit 120, and the image processing circuit 113 is integrated as one SOC in one semiconductor device, and the general-purpose bus 101 and the video bus are internal buses of the SOC. Of course, the general-purpose bus 101 and the video bus are not limited to the internal buses of the SOC. For example, when the CPU 115, the data conversion unit 120, the image processing circuit 113, and the like are separate semiconductor devices, the general-purpose bus 101 includes a PCI bus (Peripheral Components Interconnect bus) and an ISA bus (Industrial Standard Architecture bus). Various buses can be used. In general, the general-purpose bus 101 may be a bus that transmits a bit data signal that can be used for data transmission between a CPU and a memory device such as a RAM.

  In addition, since the present embodiment is a projector 100 that handles image data, the video buses 102a to 102d are used. For example, in the case of an audio processing device that handles digital audio data, an audio signal is used instead of the video bus. A bus can be used. In general, a dedicated data bus for transmitting a data signal carrying a specific type of data such as image data and audio data can be used as a component corresponding to the video buses 102a to 102d in the embodiment.

-5th modification:
In each of the embodiments described above, the CPU 115 writes image data to the data conversion unit. However, the present invention is not limited to this, and other circuits may write image data to the data conversion unit. For example, the projector is equipped with hardware specialized for a predetermined function, which is configured using an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), and the hardware converts the image into the data conversion unit. Data may be written. As a specific example of such hardware, a DMAC (Dynamic Memory Access Controller) or a JPEG decoder can be used. The DMAC is a module that performs data transfer between memories. For example, the DMAC may read image data from the ROM 116 and write the image data to the data conversion unit via the general-purpose bus 101 in accordance with an instruction from the CPU 115. Similarly, image data is stored in the JPEG format in the ROM 116, and the JPEG decoder reads out the JPEG data from the ROM 116 and decodes it into pixel data in accordance with an instruction from the CPU 115, and sequentially converts it to the data conversion unit via the general-purpose bus 101. It may be configured to write. Of course, the CPU 115 itself may be configured to sequentially write the pixel data to the data conversion unit while performing decoding from such a predetermined compression format.

-6th modification:
In the above embodiment, the image processing apparatus configured as an SOC including the CPU 115, the data conversion unit, and the image processing circuit 113 is mounted on the projector 100. If the image processing executed in the image processing circuit 113 is changed according to the device mounted, it can be mounted not only on the projector but also on various devices such as an image display device and an image output device. Specifically, the SOC can be mounted on an image display device such as a liquid crystal television. Further, if the image processing circuit 113 is configured as a circuit that generates raster data using image data supplied as a digital video signal for printing, the SOC can be mounted on a printing apparatus.

-Seventh modification:
In the third embodiment, as in the first embodiment, the CPU 115 writes the command VSC for generating the vertical synchronization signal VS to the first data register M101. Instead, as in the second embodiment, the CPU 115 writes the image data to the first data register M101 by 32 bits while referring to the address map AM, and designates the first address of the image data by designating the first image. The data converter 120b may automatically generate the vertical synchronization signal VS when data is written to the first data register M101.

  As mentioned above, although the Example and modification of this invention were demonstrated, this invention is not limited to these Example and modification at all, and implementation in a various aspect is possible within the range which does not deviate from the summary. It is.

FIG. 2 is a block diagram showing a configuration of a projector in the first embodiment. The block diagram which shows the internal structure of the video signal output part in 1st Example. The block diagram which shows the internal structure of the data converter in 1st Example. The timing chart explaining operation | movement of the data conversion part in 1st Example. The figure explaining the write to the data register in 1st Example, and the output from a data register. FIG. 3 is a diagram illustrating a schematic configuration of a projector according to a comparative example. The block diagram which shows the internal structure of the data conversion part in 2nd Example. The figure which shows notionally the address map which CPU recognizes in 2nd Example. The timing chart explaining operation | movement of the data conversion part in 1st Example. The block diagram which shows the internal structure of the data conversion part in 3rd Example. The block diagram which shows the internal structure of the bit conversion part in 3rd Example. The timing chart explaining operation | movement of the data conversion part in 3rd Example. The figure which shows notionally the content of the output of each data register in 3rd Example. The timing chart explaining operation | movement of the data converter in a 1st modification. The timing chart explaining operation | movement of the data conversion part in a 2nd modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 ... Screen 100 ... Projector 101 ... General purpose bus 102a-102d ... Video bus 111 ... A / D conversion part 112 ... Video signal output part 113 ... Image processing circuit 114 ... Liquid crystal panel drive part 115 ... CPU
120, 120a, 120b ... data converter 121, 121a ... address decoder 122, 122a, 122b ... conversion processor 130 ... multiplexer 150 ... illumination optical system 160 ... liquid crystal panel 170 ... projection optical system 1011 ... address bus 1012 ... data bus 1013 ... control bus 1021 ... enable signal line 1022 ... pixel data bus 1023 ... vertical synchronization signal line 1024 ... horizontal synchronization signal line M101 ... first data register M102 ... second data register M103 ... multiplexer M104 ... control logic M1 ... data register M2 ... Command register M3 ... Synchronization signal generator M4 ... Address register

Claims (10)

A data signal processing device,
A first bus for transmitting a data signal in accordance with a first protocol in synchronization with a predetermined clock signal ;
A second bus for transmitting a data signal in accordance with a second protocol in synchronization with the clock signal ;
A conversion unit including a register and converting a first data signal transmitted on the first bus into a second data signal transmitted on the second bus;
With
The converter is
The first data signal read from the read-only storage unit and sequentially written to the register in synchronization with the clock signal via the first bus is synchronized with the clock signal. Are sequentially converted to the data signal and output to the second bus,
The number of bits of the first data signal written to the register in synchronization with the clock signal of one cycle differs from the number of bits of the second data signal output in synchronization with the clock signal of one cycle. In this case , the data signal processing device adjusts the writing frequency of the first data signal or the output frequency of the second data signal . The data signal processing device according to claim 1 ,
The data signal processing device, wherein the number of bits of the register is equal to the bus width of the data bus in the first bus. The data signal processing device according to claim 1 or 2 ,
The first bus is a general-purpose data bus that transmits a bit data signal;
The second bus is a data signal processing device, which is a dedicated data bus for transmitting a specific type of data signal. The data signal processing device according to any one of claims 1 to 3 ,
The first data signal is a bit data signal representing image data;
The data signal processing device, wherein the second data signal is a video data signal for transmitting the image data together with a control signal in units of pixels. The data signal processing device according to claim 4 ,
The control signal includes a data enable signal,
The conversion unit is a data signal processing device that validates a data enable signal when outputting the image data to the second bus. The data signal processing device according to claim 4 ,
The control signal includes an image synchronization signal,
The conversion unit is a data signal processing device that outputs the image synchronization signal in accordance with control of a transmission source of the first data signal. The data signal processing device according to claim 4 ,
The control signal includes an image synchronization signal,
The data signal processing device, wherein the conversion unit outputs the image synchronization signal based on address information designated as a writing destination of the first data signal. Image processing apparatus including a data signal processing apparatus, an image processing circuit that receives the image data as the second data signal through the second bus according to any one of claims 1 to 7. An image output device comprising the image processing device according to claim 8 and outputting an image based on an output signal of the image processing device. A first bus for transmitting a data signal according to a first protocol in synchronization with a predetermined clock signal; a second bus for transmitting a data signal according to a second protocol in synchronization with the clock signal; and a register A data signal processing method in an apparatus including a conversion unit,
Read the first data signal from a read-only storage unit,
In synchronization with the clock signal, the first data signal is sequentially written to the register via the first bus,
In synchronization with the clock signal, the first data signal is sequentially converted into the second data signal and output to the second bus,
The number of bits of the first data signal written to the register in synchronization with the clock signal of one cycle differs from the number of bits of the second data signal output in synchronization with the clock signal of one cycle. In this case, a data signal processing method of adjusting a writing frequency of the first data signal or an output frequency of the second data signal .

Images