JP3389062B2 - Instantaneous interruption switching method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is based on the assumption that the jitters on the transmission lines of the active system and the standby system are absorbed by the preprocessing, and the steady phase difference between the systems due to the difference in the transmission path length between the systems is When absorbed in the corresponding memory, the capacity of those memories is minimized to absorb the steady phase difference between the systems, and the system is switched without interruption. Even if the stationary phase difference between systems fluctuates due to the fault transfer on the backup transmission line, the steady phase difference between the systems after the fault transfer is absorbed and system switching is performed without interruption. The present invention relates to a non-instantaneous system switching method.

[0002]

2. Description of the Related Art Up to now, when a transmission line (for example, an optical fiber transmission line) is configured as a duplicate, the jitter on the transmission line of each of the operating system (active system) and the standby system (standby system) In order to absorb the inter-system phase difference due to the difference in the inter-system transmission path length, etc., which is already absorbed, for example, the one described in Japanese Patent Laid-Open No. 7-327018 is known. In this case, the relative phase lead between the systems /
In addition to determining the delay relationship and the steady phase lead / lag amount at that time, input data from the system in the phase lead state (m · p (m: integer of 2 or more, p: integer of 1 or more A multi-frame (MF) signal consisting of frames is delayed and stored in a memory provided in common for the system by the amount of phase lead with respect to another system, and then read out from the memory. The input data from the system in the phase advance state is delayed on the memory by the amount of the phase advance, so that the phase synchronization state with the input data from the other system is achieved. However, in the operating state of the transmission system, the system that is in the phase delay state is the standby system, and the faulty transfer to the backup system transmission line side (the standby system transmission line is temporarily in the disconnection state (during failure transfer)) Assuming that a change occurs in which the transmission path length is extended / reduced), the trouble transfer cannot be dealt with any longer.

In addition to the above, a 2p frame capacity memory is provided for each system, and among the active system and the standby system,
It is also considered to use the phase in either one of the systems as a reference phase and absorb the inter-system phase difference in these memories. Regardless of the presence or absence of trouble transfer, if the inter-system phase difference is less than p frames, it is possible to re-absorb the inter-system phase difference. 2p
A frame capacity memory is required, and a large amount of memory capacity is required.

Further, it is considered that a p-frame capacity memory is provided for each system and the phase difference between the systems is absorbed in these memories. However, the block configuration of the non-interruptive system switching device according to this method. Is shown in FIG. This configuration and its operation will be described below.

That is, in the MF synchronizing circuit 1-1 in the operating system receiving section, it is assumed that the input data from the operating system transmission line has already absorbed the phase fluctuation due to the jitter,
While the MF synchronization is established by the synchronization processing, the MF synchronization signal is extracted every m · p frame cycle. From this MF synchronization signal, this is also used as a time reference in a memory (specifically, For example, the write reset signal (write initial setting signal) to the elastic memories 1-3 having the p frame capacity is generated every p frame cycles using the MF synchronization signal as the head write reset signal. Each time the write reset signal is generated, the memory 1-
3, the input data for the p frames is sequentially stored from the initial address in the order of continuous addresses. This situation is the same in the standby system. In the MF synchronization circuit 2-1 in the standby system reception section, it is assumed that the input data from the standby system transmission line has already absorbed the phase fluctuation due to the jitter, and the MF synchronization signal is established by the MF synchronization process. Is extracted every m · p frame period, and from this MF synchronization signal, this is also used as a time reference to write to a memory (specifically, an elastic memory of p frame capacity) 2-3. The reset signal is generated every p frame periods using the MF synchronization signal as the head write reset signal.

A phase difference (constant) due to a difference in transmission path length or the like usually exists between input data on the active transmission path and input data on the protection transmission path. However, this phase difference can be detected every m · p frame period as a relative phase difference between the MF synchronization signal extracted by the operation system and that extracted by the standby system. More specifically, the phase comparison circuits 1-2 and 2-2
In each of them, the phase advance / delay amount of the other system with respect to the MF synchronization signal of the own system is known by comparing the phases of the MF synchronization signals for each m · p frame period. Therefore, when the MF synchronization signal extracted by the standby system is in phase delay with respect to the MF synchronization signal extracted by the active system, the MF synchronization signal extracted by the standby system is used as a time reference, and vice versa. If the MF sync signal extracted by the standby system is in a phase delay state with respect to the MF sync signal extracted by the standby system, the memories 1-3, 2 are used with the MF sync signal extracted by the active system as a time reference. -3 The input data may be sequentially read from each of them at the same timing and the same address. Specifically, for example, the phase comparison result in which the MF synchronization signal in the active system is in a phase delay state corresponding to time α as compared with that in the standby system is the phase comparison circuit 1-
Assuming the case obtained from each of 2 and 2-2, the delay amounts t _d and t _d for absorbing the inter-system phase difference at that time from each of the phase comparison circuits 1-2 and 2-2. + Α (t _d : preset delay amount (≠ 0)) is obtained, and these delay amounts t
Based on _d and t _d + α, the memory read control circuit 1-
Read reset signals (read initial setting signals) are sequentially generated from each of 4 and 2-4 at the same timing and every p frame period. Each time this read reset signal is generated, the input data already stored from the memories 1-3 and 2-3 in the order of continuous addresses from the initial address thereof and before the delay amounts t _d and t _d + α. Are sequentially read as read data. In other words, the same input data is always read out from the memories 1-3 and 2-3 as a state in which the systems are always phase-synchronized.

By the way, normally, from the hitless switching section 3,
The read data from the active system compatible memory 1-3 is selectively output, and is received and processed by the subsequent device (not shown) in a predetermined manner. Assuming that the standby system and the standby system are switched to the new standby system and the new active system at the same time, respectively, the read data from the new active system is always in phase synchronization with the read data from the new standby system. Since the system itself is always the same, it is possible to always switch the system without any interruption.

According to Japanese Patent Laid-Open No. 8-149114, the same data from each transmitter is temporarily held in a buffer memory and read by the frame synchronization / phase difference detection function as a phase synchronization state from each buffer memory. After being sent out, the data error is monitored while being held in the memory. As a result of the monitoring, when a data error is detected from the data to one of the memories, the data read from the other memory is selectively obtained as the reception data.

[0009]

As shown in FIG. 4, the phase lead / delay amount between MF sync signals has been constant until now, but the phase difference between MF sync signals has been constant. In addition to the phase lead / delay amount at m / p frame period, the delay amount for absorbing the inter-system phase difference is determined every m / p frame period. In this case, it may not be possible to deal with the trouble transfer on the backup side. This is because, for example, when the standby system is in a constant phase delay state with respect to the operating system, the standby system phase changes due to trouble transfer on the backup system transmission line side, and therefore the read reset signal is periodically generated due to the phase change. This is because, as a result of not being guaranteed temporarily, the read data from each of the active system and the standby system is temporarily placed in a discontinuous state.

FIG. 5 shows the operation of an example of the hitless switching device shown in FIG. 4, but as will be understood from this,
In this example, before the trouble transfer, the standby system is in a constant phase delay with respect to the active system, so that the read reset signal to each memory may be constantly generated based on the standby system MF synchronization signal. It is supposed (point a). However, if the standby system phase changes due to the subsequent trouble transfer, and the standby system phase is in a phase lead state compared to the active system phase (point b), from that point onward, the standby system MF synchronization signal is used. Instead, as a result that the read reset signal to each memory is constantly generated based on the MF synchronization signal of the operation system, the phase timing of the memory read reset signal changes before and after the trouble transfer, and the read reset signal from each of the operation system and the standby system is changed. It can be seen that a discontinuous state (non-instantaneous interruption state) temporarily occurs in the read data (point c).

A first object of the present invention is to minimize the capacity of these memories when the system compatible memories absorb a wide range of stationary phase differences between the systems due to differences in the transmission path length between the systems. In this state, a stationary phase difference between the systems is absorbed, and a system switching method capable of performing system switching without instantaneous interruption is provided. A second object of the present invention is that when a steady phase difference between systems over a wide range due to a difference in transmission path length between systems is absorbed in a system corresponding memory, even if there is a trouble transfer on the standby system transmission line. However, there is an uninterruptible system switching method in which the stationary phase difference between the systems before and after the trouble transfer is absorbed and the system switching can be performed without interruption. A third object of the present invention is to absorb a steady phase difference between systems over a wide range due to a difference in inter-system transmission path length, etc. in a system corresponding memory, and after failure transfer before and after failure transfer on a backup system transmission path. In consideration of the maximum possible phase delay of the backup system phase, the steady phase difference between the systems before and after the trouble transfer is absorbed and the system switching is performed while the memory capacity is suppressed to the required minimum. Is to provide a method of switching without interruption without interruption. A fourth object of the present invention is to provide a non-instantaneous system switching method in which the system-compatible memory can absorb the stationary phase difference between systems every time the system-compatible memory cannot absorb it. is there. A fifth object of the present invention is to prevent a malfunction in the posterior device when the system compatible memory is made to be able to absorb the steady phase difference between the systems each time the system compatible memory cannot absorb it. In order to prevent this, there is provided a non-instantaneous interruption system switching method capable of returning to an absorbable state while being notified of a specific pattern.

[0012]

A first object of the present invention is to provide a system-compatible write initialization signal which is created every p frame cycles from a system-compatible multi-frame synchronization signal. While the multi-frame data for one frame is written in the order of consecutive addresses, after the system that is in the phase delay state is once selected by the inter-system phase comparison of the system-related initial multi-frame synchronization signal, the system-related write initialization is performed. In response to the signal, every time a reading initial setting signal common to the system is generated every p frame period as soon as possible in terms of memory control, multiframe data for p frames continues from the memory corresponding to the system. This is achieved by reading in address order.

The second object is to support the backup system along with trouble transfer on the backup system transmission line in a state where p frames of multi-frame data are read out in the order of consecutive addresses from the system-compatible memory. Even if the creation of the write initial setting signal is temporarily stopped and the steady phase difference between systems changes due to the trouble transfer, the steady phase difference between the systems before and after the trouble transfer is changed except during trouble transfer. Is achieved by being constantly absorbed.

Further, the third object is to cope with the system assuming that the maximum possible phase delay of the spare system phase after the trouble transfer on the protection system transmission line before the trouble transfer is β (≠ 0) frames. After the multi-frame data for p frames is written in the memory of, in the order of consecutive addresses, the system in the phase delay state is once selected by the inter-system phase comparison of the initial multi-frame synchronization signals extracted for each system. In the system, the read initialization of the common system is performed as a delayed state with respect to the system-related write initialization signal for the selected system, which is delayed by the sum of the β frame and the minimum required capacity for memory control. Each time a signal is created every p frame periods,
In the state where multi-frame data for p frames is read out in the order of continuous addresses from the memory corresponding to the above system, at least (p + β) frames and a minimum memory capacity required for memory control are combined. Using a memory having a capacity, in addition to the steady phase difference between systems within a period corresponding to p frames, the creation of the standby system-corresponding write initialization signal is temporarily stopped due to the fault transfer on the standby system transmission line, and Even if the steady phase difference between systems changes by β frames or less due to the transfer, it can be achieved by always absorbing the steady phase difference between systems before and after the trouble transfer except during trouble transfer.

Still further, the fourth object is that, while the phase difference of the write initializing signal corresponding to the spare system with respect to the read initializing signal common to the system is constantly monitored, trouble transfer on the spare system transmission line, etc. As a factor, every time system switching is performed in a state where the phase difference is outside the non-instantaneous-interruption system switching allowable range, the phase difference is returned to the non-instantaneous-interruption system switching allowable range again so that the system common This is achieved by resetting the timing phase of the read initialization signal.

The fifth object is also that, when the timing phase of the read initialization signal common to the system is reset, the multi-frame signal read as the active system has a fixed time before and after the resetting of the phase timing. This is achieved by reading as a state in which the specific pattern data is replaced in order to prevent malfunction due to disturbance of the multi-frame data due to momentary interruption.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. First, the non-stop system switching device according to the present invention will be described. FIG. 1 shows a basic block configuration in an example thereof. As shown in the figure, the block configuration is substantially different from that shown in FIG. 4 described above, that is, a new component, that is, the insertion / removal detection units 1-5 and 2
-5, operation status monitoring unit 1-6, 2-6, write / read phase comparison circuit 1-7, 2-7, mask circuit 1-8, 2-
8 and timer circuits 1-9 and 2-9 are provided. If the minimum memory capacity required for memory control is ignored, the memory 1-3, 2−
As the memory capacity of each of the three, at least the p-frame capacity, specifically, the maximum possible phase delay of the backup system phase before and after the failure transfer on the backup system transmission path is β frames. If at least (p +
β) It should be set as the frame capacity.

Hereinafter, assuming that the minimum memory capacity required for memory control is ignored, the insertion / removal detection units 1-5 and 2-5, and the operation state monitoring unit 1 among these components are first described.
-6 and 2-6, the insertion / removal detection units 1-5 and 2-5 constantly monitor the insertion / removal state of the other system receiving unit, and the monitoring result is The operating status monitoring units 1-6 and 2-6 have been notified, but the operating status monitoring units 1-6 and 2-6 each have their own operating status,
As shown in Tables 1 and 2 below, the operating state and operating phase of the own system are selected from the operating state of the other system and the inserting / extracting state of the other system.

[0019]

[Table 1]

[0020]

[Table 2]

As can be seen from the above, in each of the active system and the standby system, the phase comparison circuits 1-2 and 2-2 have not performed phase comparison adjustment of the MF initial synchronization signal with each other. (Before phase adjustment) and when the receiving unit of the other system is not in the inserted state, the reading control from the memory is performed under the autonomous control regardless of the other system. That is,
In the operation system, every time the MF synchronization signal is extracted, the memory read control circuit 1-
From 4 onward, the read reset signal may be periodically generated for the memories 1-3, and this situation is the same in the standby system. Also, in each of the active system and the standby system, the own system is not yet phase-adjusted with the other system (before phase adjustment), and the other system receiving section itself is in the inserted state, Are both MF
When the phase is adjusted once with the other system after being placed in the initial synchronization state, as a general rule, after that time, the own system will receive data from the other system and memories 1-3 and 2-3 respectively. It can be seen that the read phase is in the hold state (self-propelled state). That is, after the system in the phase delay state is once selected by the inter-system phase comparison of the system-corresponding initial MF synchronization signals, it is assumed that the system-corresponding write reset signal is delayed by at least one address or β frames. The system common read reset signal is generated every p frame periods. If the memory capacity in each of the memories 1-3 and 2-3 is at least (p + β) frame capacity, and the system common read reset signal is generated every p frame cycles with a delay of β frames. The maximum phase delay (for β frames) that can be assumed for the phase shift at that time is not only for coping with the trouble transfer related to the reduction of the backup transmission path length but also for the trouble transfer related to the extension. ) The following can be easily dealt with.

From the above description, the hold state in the active system is directly related to the present invention. While the active system is in the hold state, the write reset signal is also generated in the standby system. Whether or not the phase difference with respect to the system common read reset signal is within the allowable range is constantly monitored. That is, for example, while the active system is in the hold state, in the standby system, the write / read phase comparison circuit 2-7 constantly monitors whether or not the phase difference between the write reset signal and the read reset signal is within the allowable range. However, even if trouble transfer is performed on the backup side, as long as the phase difference between the write reset signal and the read reset signal is within the allowable range, it is not necessary to adjust the phase timing of the read reset signal. The input data is always read from the standby system in a state in which the system can be switched without interruption. However, assuming that the phase of the backup system changes significantly due to the trouble transfer on the backup system side, the phase difference between the write reset signal and the read reset signal also changes significantly, and there is no momentary loss on the backup system side. It is clear that the disconnectable state cannot be guaranteed. Therefore, each time the write / read phase comparison circuit 2-7 detects that the phase difference between the write reset signal and the read reset signal is out of the allowable range, the phase timing of the read reset signal is reset as desired. In this case, even if there is a temporary discontinuity in the read data from the active system, the phase difference can be restored to within the allowable range, and the input data from the standby system is constantly switched without interruption. It can be read as a valid state. Further, when the phase timing is reset, the mask circuit 1-reads the read data from the operation system for a certain period of time before and after the reset by the timer circuit 1-9.
When the specific pattern data (for example, fixed pattern data of all “1”) is read via 8 and is received and recognized by the succeeding device, the succeeding device recognizes the specific pattern data and the opposite device, That is, necessary measures are taken to prevent a malfunction while the specific pattern is detected while the fault related to the system switching in the own device is recognized.

The non-instantaneous system switchable state on the standby system side will now be described with reference to FIG. 2. As shown in the figure, the write reset signal WR and the read reset signal RR are both p frame periods (= p × 125 μs), the no-interruption system switching guarantee time is q (s) (p> q), and the phase comparison circuit 1
−2, 2-2 is the relative phase difference between the systems detected by r
If (s), it becomes possible to know which of the active system and the standby system is in the phase delay state from the phase comparison results of the phase comparison circuits 1-2 and 2-2. There is. In this example, it is assumed that the active system is in the phase delay state. As a result, first, in the active system, the read reset signal RR and the write reset signal WR are generated as described above on the basis of the active system MF synchronization signal. The phase difference is generated as a state set within p × 125 μs−q.
On the other hand, in the standby system, the write reset signal WR is generated based on the standby system MF synchronization signal as in the active system, but the read reset signal RR is generated at the same timing as the read reset signal RR in the active system. Has become. If the inter-system relative phase difference r (s) is q> r, the write reset signal WR in the backup system falls within the “instantaneous interruption guaranteed range”, which is within the guaranteed range without interruption. The read reset signal RR common to the system eliminates the phase difference between the read data from the active system and the read data from the standby system, and the system can be switched without interruption.

Finally, the sequence from the time when the power to the active system is turned on to the time when the active system is put in the hold state will be described with reference to the flow shown in FIG. Assuming that both the operating system receiving unit and the standby system receiving unit are inserted, if only the operating system receiving unit is powered on first, the insertion / removal detection unit 1-5 sends an insertion notification to the standby system. On the other hand, in the operation status monitoring unit 1-6, the insertion / removal detection unit 1 also
Based on the notification from -5 (no backup system inserted, before phase adjustment) and the operation status in the own system (before phase adjustment), as shown in Table 1 above, the operation phase is under the operation system autonomous control. In addition, the reading control from the memory is performed regardless of the backup system. In such a state, if the standby receiving unit is also powered on, the insertion / removal detecting unit 2-5
From the above, an insertion notice is sent to the operational system. By this notification, in the operating status monitoring unit 1-6, the standby system is changed to the state before the insertion and the phase adjustment, and as the operating phase in the operating system, as shown in Table 1 above, the inter-system relative as the phase comparison result. Based on the delay amount adjusted in each system by the phase difference, a read reset signal common to the system is generated and read control from the memory is performed. Based on the delay amount adjusted by the relative phase difference between the systems as a result of the phase comparison, a read reset signal common to the systems is generated, and read control from the memory is performed. At this point, both the active system and the standby system are already in the state after phase adjustment, but in order to confirm this state mutually,
The completion of phase adjustment is notified to other systems. In this way, after mutual phase adjustment completion notifications,
The operational states of both the active system and the standby system are after the phase adjustment, and therefore, the operational phase is set to the hold state. In this state, even if the standby system phase changes due to the trouble transfer in the standby system,
For trouble transfer within the range where the standby system can switch to the non-stop system, the operating system remains in the hold state regardless of the standby system, and the non-stop system is also available. It can be switched.

[0025]

As described above, according to the first aspect of the present invention, when a system-compatible memory absorbs a wide inter-system steady phase difference due to a difference in inter-system transmission path length, etc. In the state where the capacity is suppressed to the necessary minimum, the steady phase difference between the systems is absorbed, and the system can be switched without interruption. When the phase difference is absorbed by the system compatible memory, and in the case of claim 2, when the system compatible memory absorbs a wide range of steady phase difference between the systems due to the difference in the transmission path length between the systems, Even if there is a trouble transfer on the standby system transmission line, the steady phase difference between the systems before and after the trouble transfer is absorbed, and the system can be switched without interruption.
According to claim 3, when a wide range of steady phase differences between systems due to differences in transmission path length between systems are absorbed in the system memory, after the failure transfer before and after the failure transfer on the backup system transmission path. In consideration of the maximum possible phase delay of the backup system phase, the steady phase difference between the systems before and after the trouble transfer is absorbed and the system switching is performed while the capacity of those memories is suppressed to the necessary minimum. It can be performed without interruption, and according to claim 4, every time the system switching is performed in a state where the steady phase difference between the systems cannot be absorbed in the system compatible memory, the system can be directly supported immediately after the system switching. The absorption in the memory can be enabled again, and in the case according to claim 5, again, every time the system switching is performed in a state where the system compatible memory cannot absorb the steady phase difference between the systems, immediately after the system switching. When it can be absorbed again in the system compatible memory, Te has a one hitless system switching method of malfunction can be prevented in the subsequent position device by it is notified to the succeeding device is obtained, respectively.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic block configuration in an example of a hitless switching system switching device according to the present invention.

FIG. 2 is a diagram for explaining a state in which a standby system can switch to a non-instantaneous system.

FIG. 3 is a diagram showing an example of the flow from the time when power is supplied to the active system to the time when the active system is put in a hold state.

FIG. 4 is a diagram showing a block configuration of an example of a hitless system switching device according to a conventional technique.

FIG. 5 is a diagram for explaining an operation of an example of the hitless system switching device.

[Explanation of reference numerals] 1-1, 2-1 ... MF synchronization circuit, 1-2, 2-2 ... Phase comparison circuit, 1-3, 2-3 ... Memory, 1-4, 2-4 ...
Memory read control circuit, 1-5, 2-5 ...
1-6, 2-6 ... Operation status monitoring unit, 1-7, 2-7 ... Write / read phase comparison circuit, 1-8, 2-8 ... Mask circuit, 1-9, 2-9 ... Timer circuit, 3 ... No interruption switch

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kinji Yoshida               216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa               Information & Communication Division, Hitachi, Ltd.               Within (72) Inventor Senji Kawamura               3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo               Inside Telegraph and Telephone Corporation (72) Inventor Hiroshi Sugawara               3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo               Inside Telegraph and Telephone Corporation                (56) Reference JP-A-6-327076 (JP, A)                 Japanese Patent Laid-Open No. 7-13892 (JP, A)                 JP-A-7-327018 (JP, A)                 JP-A-8-149114 (JP, A)                 JP-A-9-153877 (JP, A)

Claims (5)

(57) [Claims] 1. A steady phase difference between systems of p (integer of 1 or more) frames or less is absorbed, assuming that the phase difference between systems due to the jitter on the transmission lines of the active system and the standby system is already absorbed. , A system for switching between systems without interruption without interruption, comprising m · p (m: integer of 2 or more) frames from each of the working transmission line and the protection transmission line. A multi-frame synchronization signal is extracted from the multi-frame signal for each m · p frame period in a system-corresponding manner, and each time a system-corresponding write initialization signal is created from the multi-frame synchronization signal in every p frame period Multi-frame data for p frames is written in the order of consecutive addresses on the system-corresponding memory, while the inter-system phase comparison of the initial multi-frame synchronization signals extracted for the system temporarily determines that the system is in a phase lag state. After being selected, with respect to the system-corresponding write initialization signal for the selected system,
In memory control, every time a read initialization signal common to the system is generated every p frame period as soon as possible after memory control, multiframe data for p frames is read from the memory corresponding to the system in the order of continuous addresses. By using a memory having a capacity of at least p frames and a minimum memory capacity required for memory control, p
A non-instantaneous interruption system switching method in which a systematic switching is performed in a non-instantaneous interruption state of a multi-frame signal while a steady phase difference between systems within a frame equivalent is always absorbed. 2. Assuming that the inter-system phase difference due to the jitter on the transmission line of each of the active system and the standby system is already absorbed, before and after the trouble transfer on the standby system transmission line of p (integer of 1 or more) frames or less. While the steady phase difference between the
A non-interruptive system switching method in which the system switching is performed without interruption after the trouble transfer, wherein m / p (m: 2 or more) from each of the operating system transmission line and the standby system transmission line is used. A multi-frame synchronization signal is extracted from the multi-frame signal composed of (integer) frames for each m / p frame cycle, and a system-dependent write initialization signal is created for each p frame cycle from the multi-frame synchronization signal. Each time, the multi-frame data for p frames is written in the memory corresponding to the system in the order of continuous addresses, while the initial multi-frame synchronization signal extracted for the system is in phase lag due to inter-system phase comparison. After the system is once selected, with respect to the system corresponding write initialization signal for the selected system,
In memory control, every time a read initial setting signal common to the system is generated every p frame cycle as soon as possible, p frame multi-frame data is read from the memory corresponding to the system in the order of continuous addresses. In this state, even if the preparation of the write initialization signal corresponding to the standby system is temporarily stopped due to the trouble transfer on the backup system transmission line, and the steady phase difference between the systems changes due to the trouble transfer. , A non-interruptive system switching method that enables system switching in a non-interruptive state of a multi-frame signal while always absorbing the steady phase difference between the systems before and after the fault transfer, except during the fault transfer. 3. The maximum possible phase difference between the system before and after the trouble transfer on the protection system transmission line is already absorbed by the inter-system phase difference due to the jitter on the transmission lines of the working system and the protection system. Assuming that the phase delay is β (≠ 0) frames, steady phase differences between the systems before and after the trouble transfer on the backup system transmission line, which is p (an integer of 1 or more and> β) or less, are absorbed, A method for switching a system without instantaneous interruption so that system switching is performed without interruption, and is a multi-frame consisting of m / p (m: an integer of 2 or more) frames from each of an active transmission line and a standby transmission line. A multi-frame synchronization signal is extracted from the frame signal for each m · p frame cycle in a system-corresponding manner, and a system-related write initialization signal is created for each p frame cycle from the multi-frame synchronization signal. In the corresponding memory, p frame While the multi-frame data corresponding to the system is written in the order of consecutive addresses, the system in the phase delay state is once selected by the inter-system phase comparison of the initial multi-frame synchronization signals extracted for the system, and then the selected system is selected. For the system compatible write initialization signal for
Every time a read initialization signal common to the system is created every p frame cycles in a delayed state by the sum of the β frame and the minimum required capacity for memory control, it is read from the memory corresponding to the above system. Is a state in which multi-frame data for p frames is read out in the order of consecutive addresses, and a memory having a capacity for at least (p + β) frames and a minimum memory capacity required for memory control is used. ,
In addition to the steady phase difference between systems within the amount equivalent to p frames, the creation of the backup initialization write initialization signal is temporarily stopped due to the trouble transfer on the protection system transmission line. Even when the steady phase difference between systems changes,
A non-interruptive system switching method that enables system switching in a non-interruptive state of a multi-frame signal while always absorbing the steady phase difference between the systems before and after the fault transfer, except during the fault transfer. 4. The phase difference of the write initialization signal corresponding to the spare system with respect to the read initialization signal common to the system is constantly monitored, due to trouble transfer on the spare transmission line, etc.
In order to restore the phase difference to within the non-instantaneous interruption system switching permissible range each time the system is switched while the phase difference is outside the non-instantaneous interruption system switching permissible range, a read initial setting signal common to all the systems. 4. The non-interruptive system switching method according to claim 1, wherein the timing phase is reset. 5. When the timing phase of the read initial setting signal common to the system is reset, the multi-frame signal read as the active system is a multi-frame signal due to a momentary interruption for a certain period of time before and after resetting the phase timing. 5. The non-instantaneous interruption system switching method according to claim 4, wherein in order to prevent malfunction due to disturbance of frame data, the pattern data is read as being replaced with the specific pattern data.