JP2829602B2 - Transmission data phase matching method and instantaneous interruption switching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to multiplexing of a large-capacity long-distance transmission system for multiplexing, for example, low-speed signals, generating high-speed signals, and then transmitting data to a distant location via an inter-station transmission path. The present invention relates to a hitless switching device used for a relay device.

[0002]

2. Description of the Related Art In a multiplex repeater of a large-capacity long-distance transmission system, a plurality of data transmission paths are prepared in order to ensure high reliability. Usually, the transmission path is automatically switched to the transmission path of In this case, a non-stop switching device is used in order not to affect the data being transmitted.

FIG. 9 is a diagram showing the basic configuration of a conventional non-interruptible switching device of this type.
The system branches to one system (one system is set to 0 system and the other system is set to 1 system), and the data being transmitted (hereinafter referred to as “transmission data”) is selectively disconnected without instantaneous interruption while ensuring phase synchronization by the instantaneous interruption switching device SW. This is an example of switching. In the figure, a,
b, a ', and b' represent path lengths. In FIG. 9, (a)
In the initial state, when the path length a of the system 0 is longer than the path length b of the system 1 in the initial state, (b) shows that the path length b of the system 1 changes to b ′, and is longer than the path length a of the system 0. In this case, (c) shows a case where re-phase adjustment is performed. FIG. 10A,
9 (b) and 9 (c) respectively show FIGS.
The relationship between the memory write phase and the memory read phase in the state (c) is shown.

The instantaneous-interruption switching device SW includes delay circuit sections 11 and 1 for providing an arbitrary amount of delay to transmission data of the 0-system and 1-system.
2, a phase determining unit 13 for variably controlling the delay amount in the delay circuit units 11 and 12 by determining the phase state of the transmission data of each system, and selectively switching the output of each of the delay circuit units 11 and 12 for output. And a selector 14 that performs the operation.

In FIG. 9 (a), the instantaneous interruption switching device SW
The transmission data of each system input to the delay circuit unit 1
After being written to 1,12, they are read at a certain phase.
In the initial state, as shown in FIG.
Write phase (input phase, the same applies hereinafter) aW, bW according to b
Are set so that the readout phases (output phases, hereinafter the same) t0 and t1 are the same. As a result, the phases of the transmission data after the memory circuit units 11 and 12 become the same in the 0/1 system, so that the selector 14 can switch without instantaneously interrupting the transmission data.

Here, as shown in FIG. 9B, the path length b changes for some reason to b ′, and FIG.
, The read phases t0 and t1 are the write phases b 'of the system.
If a situation in which W is overtaken occurs, transmission data cannot be read correctly. Therefore, the phase determination unit 13 monitors the presence or absence of an abnormality in the phase relationship between the transmission data of the two systems, and when the abnormality is detected, the switching operation of the selector 14 is prohibited, and the read operation is performed as shown in FIG. Phase t
0 'and t1' are delayed. That is, the phase is delayed by a fixed amount with respect to the writing phase of the system having a large phase delay, and re-phase adjustment is performed. Thus, as shown in FIG. 10C, the read phases t0 'and t1' always follow the write phases aW and b'W, so that the transmission data can be correctly read.

FIG. 11 is a specific configuration diagram of the instantaneous interruption switching device SW. In FIG. 11, transmission data of system 0 and system 1 are input to delay circuit units 11 and 12, respectively. Each of the delay circuit units 11 and 12 has the same configuration and is modularized independently of each other. Each delay circuit unit 11, 12
Transmits the transmission data of its own system to the delay control memory (M
EM) 111, 121 and synchronization detection circuit (SYNC) 11
2, 122. Each synchronization detection circuit 112, 122
Is for detecting a bit synchronization signal from the input transmission data, and the synchronization signal detected here is supplied to write address counters (W-CTR) 113 and 123, respectively. Write address counters 113 and 123
Counts the input synchronization signals,
A write address for the memories 111 and 121 is generated.
That is, the transmission data of the 0-system and the 1-system is written into the memories 111 and 121 at the inherent synchronization bit timing.

The synchronization signal is supplied to a variable delay circuit (D
LY) 114, 124 to the read address counters (R-CTR) 115, 125. Each of the read address counters 115 and 125 counts the input synchronizing signal, so that the memories 111 and 12 are read.
1 is generated. That is, the memory 11
The transmission data written in 1,121 is transmitted to the variable delay circuit 1
The selector (SE) is read out after the elapse of the delay time set in the 14, 14 and becomes a low-speed interface.
L) 14.

Here, the read address counter 11
5, 125, for example, in a data of 64 frames, inputs and outputs a pulse signal indicating a read 64 multi-frame position to adjust read timing. Further, the write address outputs of the write address counters 113 and 123 are supplied to the phase determination unit 13 to be subjected to the above-described phase determination.

During operation, the phase judging unit 13 monitors whether the write / read phase of the 0/1 system is in a normal phase range, that is, in a phase range where instantaneous interruption switching can be performed, and deviates from the normal phase range. If so, re-phase adjustment is automatically performed. This re-phase adjustment is performed as follows. First,
At the time of initial phase setting, it is determined which system has the longer path length, the phase on the longer path length side is detected, and the phase delay amount of the path is set to the minimum value. After that, the read phases on the short path length side and the long path length side are fetched, and the read phases of both systems are matched. Thereafter, the phase relationship is constantly monitored during operation, and when an abnormal phase becomes such that instantaneous interruption switching cannot be performed, the above operation is repeated again. As a result, instantaneous interruption switching can be realized at any time regardless of the path length of the switching destination / switching source. However, since the phases of both systems are forcibly adjusted, one instantaneous interruption of transmission data occurs for one re-phase adjustment.

[0011]

The conventional instantaneous interruption-free switching device SW has the following problems. Now, if the phase is adjusted based on the path on the long delay side and the delay circuit unit on the long delay side is in a standby state, if the standby module is removed for replacement or the like and reinserted, the synchronization recovery may be lost. Even if the returned phase is within the normal phase range in the phase relationship at the time of the initial setting, re-phase adjustment is performed on the large delay side. That is, the read phase is reset to a point where a predetermined amount of delay has occurred from the write phase on the longer delay side. However, the phase to be reset is likely to be different from the initial state due to phase fluctuations of the transmission path, etc., and therefore, re-phase adjustment may occur and the transmission data of the operation system may be momentarily interrupted. Yes, the reliability is impaired. The same applies to the case where the delay circuit unit on the small delay side is on standby and the standby system module is removed and reinserted.

FIG. 12 specifically shows this.
(A) and (b). Here, the system with a large delay is 1
FIG. 12A shows an example in which a system with a small delay is set to the system 0 and a module of the system 1 in standby is inserted and removed, and FIG. 12B shows an example in which a module of the system 0 in standby is inserted and removed. Is shown in In the figure, A is the read phase, A 'is the reset read phase, and indicates the frame start position of the transmission data for convenience. For example, in the case of FIG. 12A, the readout phase (third A from the left) at the time when the synchronization is restored by re-inserting the standby module of the first system is within the normal phase range. However, if the write phase of the first system is shifted to the position shown by the broken line after the synchronization recovery, re-alignment is performed based on this write phase, resulting in instantaneous interruption. FIG. 12 (b)
In the case of (1), if the relative phase difference from the writing phase of the first system is shifted to the position shown by the broken line, re-phase adjustment is performed based on the writing phase of the first system, and the same result is obtained. The above-mentioned problem similarly occurs not only in the system of the second system such as the system 0 and the system 1 but also in the same type of system having the modules of the system 3 or more, or the instantaneous interruption switching device.

[0013] Accordingly, an object of the present invention is to provide a non-instantaneous interruption switching device having a plurality of system modules through which transmission data passes, to minimize re-phase matching in each system to a necessary minimum and to cause the re-phase matching. An object of the present invention is to provide an improved phase matching method capable of preventing occurrence of instantaneous interruption as much as possible.

[0014]

According to a phase matching method provided by the present invention, a delay circuit for delaying an output phase of the transmission data is provided to each of a plurality of modules to which the same transmission data is input; and a phase controller for controlling the delay amount of the circuit section, the phase control unit in each system, is input to the self-system
The phase of the transmission data is determined and the delay is determined.
The phase of the transmission data output from the circuit is determined, and
These phase judgment results and the phase state of the transmission data after delay
Information is passed to the phase control unit of the other system, and the phase
Delay after insertion / removal of own module by referring to state information
It is determined whether or not the amount control is necessary.
And executes the control.

The phase control unit of each system is preferably configured as follows. (1) It is necessary to control the delay amount in the own system and other
Configured to control the delay amount of the delay circuit portion of the self-system to match the output phase of the transmission data of the other system if the phase matching has been finished in the phase control section of the system. (2) A non-volatile memory that holds phase matching information indicating whether or not phase matching of transmission data has been completed between the own system and the other system, and a synchronization state and input / output of transmission data of the own system and the other system Means for monitoring the phase, and means for resetting the phase matching information in the memory in accordance with the monitoring result, wherein control of the delay circuit unit of the own system is performed in accordance with the presence or absence of the phase matching information in the memory. It is configured to determine whether or not it is not. (3) means for detecting the relative phase delay amount of the own system by comparing the phases of the transmission data input to the modules of the own system and the other system, and determining whether the detected phase delay amount is within a predetermined range. Is further provided, and it is configured to determine whether control of the delay circuit unit of the own system is necessary or not in accordance with the result of the determination. (4) When one of the plurality of systems is an active system and the other is a standby system, and a standby system module can be inserted into and removed from a transmission line of the system, the phase of the standby system module inserted after removal is provided. The control unit, when the control of the delay circuit unit is required in the system, fetches the output phase of the transmission data from the operating system module whose phase has been adjusted, and controls the delay circuit of the own system so as to match the fetched output phase. The unit is configured to be controlled. (5) The phase control unit included in the operating system module resets the phase matching information in the memory of the own system when the relative phase delay amount in the own system deviates from the predetermined range, and resets the other system. Is configured to reset the phase matching information in the memory.

The present invention also provides an instantaneous interruption switching device employing the above-described phase matching method. The instantaneous interruption switching device includes a first delay circuit for delaying transmission data input to a first system, a phase determination of transmission data input to the first system, and the first delay circuit. A first module including a first phase control unit that performs phase determination of transmission data output from the delay circuit unit, and controls a delay amount of the first delay circuit unit based on each phase determination result. A second delay circuit for delaying transmission data input to the second system, and a phase determination of transmission data input to the second system and output from the first delay circuit. A second delay circuit for controlling a delay amount of the second delay circuit unit based on each phase determination result.
A second module having a phase control unit, and data switching means for selectively outputting transmission data output from the first and second modules, wherein the first and second modules are provided.
The phase control unit of the present embodiment, respectively, passes the phase determination result and the phase state information of the transmission data after the delay, and executes the delay amount control after the insertion and removal of the own system module with reference to the phase state information of both systems. It is a feature.

It should be noted that in the instantaneous interruption switching device, the first
When one of the first and second systems is an active system and the other is a standby system, the first and second delay circuit units and the first and phase control units are configured as follows, for example. That is, the first
And a second delay circuit section, respectively, based on a synchronization detection circuit for detecting a synchronization signal from the input transmission data, a memory for sequentially writing the input transmission data, and a synchronization signal detected by the synchronization detection circuit. Memory write control means for performing write control on the memory, a variable delay circuit for delaying the synchronization signal, and a transmission data written to the memory based on the synchronization signal delayed by the variable delay circuit. A memory read control unit for performing read control, wherein the first and second phase control units receive control information of a self-system and another system memory write control unit and control information of a memory read control unit, respectively. A delay amount control means for judging the phase state of both systems from the input information and controlling the delay amount of the variable delay circuit so that the phases of the two systems match each other, and a delay amount control means for controlling the delay amount. Storage means for storing the delay amounts of the two systems as phase matching information, and a re-phase for transmitting the phase matching information stored in the storage means to the standby module when performing phase alignment after insertion and removal of the standby module. A matching execution means.

This instantaneous interruption switching apparatus performs phase adjustment based on the phase determination result at the time of initial phase setting, maintains a phase relationship capable of executing instantaneous interruption switching at all times during operation, and eliminates unnecessary re-phasing at the time of standby module insertion / removal. This is to prevent instantaneous interruption due to the combination.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a basic configuration diagram of a hitless switching device that realizes the phase matching method of the present invention.
Here, for the sake of convenience, similarly to the conventional apparatus shown in FIG. 9, the data transmission path is divided into two systems of path lengths a and b (one is set to 0).
System and the other as one system)
An example in which the switching is selectively performed without instantaneously interrupting the transmission data of the active system while securing the phase synchronization.

In FIG. 1, (a) shows that, when the path length a of the system 0 is longer than the path length b of the system 1 in the initial state, the path length b of the system 1 changes to b ', and A case where the phase is longer than the path length a of the system and the phases are re-aligned is shown. In FIG. 1, the same parts as those in FIG. 9 are denoted by the same reference numerals, and duplicate description will be omitted.

In this embodiment, the delay circuit section is set to 0/1
The system is realized by separate modules, and the delay circuit units are configured to communicate with each other. In other words, each module (delay circuit unit) of the 0/1 system includes a phase determination unit X1, Y1, a memory circuit unit X2,
Y2, phase control units X3 and Y3,
During Y3, the phase determination result and the phase matching state information are exchanged with each other, and the fact that the system has been phase-matched is stored in both system modules, thereby controlling the execution of re-phase matching by inserting and removing the standby system module. I do.

FIG. 2 is a specific configuration diagram of the instantaneous interruption switching device SW. Note that, for convenience, FIG.
The same functional parts as those described above are denoted by the same reference numerals, and duplicate description is omitted here. The phase determination units X1, Y1 and the phase control units X3, Y3 in FIG.
T) 116 and 126 correspond to the memory circuit unit X in FIG.
2, Y2 are the delay control memories (MEM) 11 of FIG.
1, 121, synchronization detection circuit (SYNC) 112, 12
2. Write address counter (W-CTR) 113, 12
3. Variable delay circuits (DLY) 114 and 124 and read address counters (R-CTR) 115 and 125 correspond. That is, the point that the instantaneous interruption switching device SW of this embodiment is greatly different from the conventional product shown in FIG. 11 is that the delay circuit unit has a phase control unit (CONT) 11 having the same configuration.
6,126. Note that the synchronization detection circuit 11
2 in that the detection result of the second system is notified to the phase control units 116 and 126 of both systems.

Next, the phase controllers 116 and 126 will be described in detail with reference to FIGS. FIG. 3 shows the phase controller 11.
6 is an overall configuration diagram of No. 6,126. The phase control units 116 and 126 according to the present embodiment are provided with a self-system write address W-ADD.
And the other system write frame pulse W-FP, and compares the frame phases of the two systems to determine whether the system having a phase delay is the main side (Main) or the local side (Local). A1 and the own-system write address W-ADD and the own-system read frame pulse R-FP to monitor the range of the write phase and the read phase based on the out-of-synchronization information of the own system and the notification of the completion of the phase alignment, and perform the write / read. A phase monitoring unit A2 that outputs as a determination result (hereinafter, a W / R determination result), and a phase-matched notification based on the output of the phase monitoring unit A2, the W / R determination result of another system, and the out-of-synchronization information of the other system. And a phase matching trigger controller A for outputting a phase matching trigger (command FP) based on the out-of-synchronization information of the own system and the other system and the notification of the completion of the phase matching of the other system.
4 and a plurality of logic gates G1, G2, G3.

Note that "Main" is the delay side, that is,
Refers to the system used as a reference for re-phase matching.
l ”is a small delay side system, ie,“ M
ain ”refers to a system that refers to the readout phase of the system. However, the relationship between them is changed at any time. Further, the read phase set based on the “Main” system is a read phase common to both systems. Hereinafter, for convenience, a case will be described in which attention is focused on the phase control unit 116 of the first system. In this case, the own system is system 1 and the other system is system 0.

As shown in FIG. 4A, the phase judging unit A1 outputs the write address W-ADD from the own system write address counter 113 and the write frame pulse W-FP from the other system write address counter 123. For example, 64 multi-frame pulses are input, and a system (Main / Local) in which a phase delay occurs is determined. For example, FIG.
As shown in (b), in the transmission data of the 64-frame configuration, the other-system write frame pulse W-FP is changed to the own system write address W-FP.
If ADD is between "32" and "63", it is determined that the transmission data of the own system is relatively delayed, and the determination result is the main side (Main). This determination result is used as information for determining a reference at the time of executing re-phase matching. In addition,
In the figure, (i) means input and (o) means output.

As shown in FIG. 5 (a), the phase monitoring section A2 outputs the own system out-of-synchronization information, the own system phase matching notification, the own system write address W-ADD, and the own system read frame pulse RF.
P, for example, a readout 64 multi-frame pulse is input, and the fluctuation of the write phase and the readout phase is monitored. Then, the monitoring result is output as a W / R determination result. That is, FIG.
As shown in (1), it is determined that the out-of-synchronization information by the synchronization detection circuit 112 of the own system is OK and the own system is within the normal phase range when the own system is phase-matched. When abnormal (NG)
In addition to resetting the phase-matched register unit A3 of the own system, the other system is notified of the reset, and the phase-matched register unit A3 of the other system is reset. The other system's phase-matched register unit A3 is reset only when the own system is in operation.

The phase-adjusted register section A3 is shown in FIG.
As shown in (a), according to the trigger input timing from the phase adjustment trigger control unit A4, the W /
The R determination result and the input of the out-of-synchronization information of the own system or the other system passing through the AND gate G2 are monitored, and when these are input as prescribed, the phase adjustment indicating that the phase adjustment of both systems has been completed. Output notification. As shown in FIG. 6B, the phase-adjusted register unit A3 is set at the trigger input timing, and the own system W / R phase determination result NG, the other system W / R phase determination result NG, and the AND gate G2 ( Reset when both systems are out of synchronization). Note that the phase-matched notification is output to the other-system phase control unit 126 as phase matching information together with the W / R phase determination result.

The phase adjustment trigger control unit A4 is configured as shown in FIG.
As shown in (a), an output of an OR gate G1 for determining the logical sum of the own / other system out-of-synchronization information, and an output of an AND gate G2 for determining the logical product of the own / other system out-of-synchronization information,
AND for judging the logical product of self-system / other-system phase-matched notification
The output of the gate G3 is input. Then, as shown in FIG. 7B, in a state where the phase-matched registers A3 of both systems are reset (phase-matched notification NG), conditions such as synchronization recovery and a normal phase range are satisfied. Is determined, and the phase matching trigger (command FP) and the trigger input timing are given to the variable delay circuit (DLY) 114 as phase matching control information. When the phase adjustment is completed, the output of the command FP and the trigger input timing is stopped.

In the above description, the phase control unit 12 of the 0 system
In 6, the same applies to the case where the own system is set to 0 system and the other system is set to 1 system. Further, the above example includes an explanation of the operation for correctly operating the re-phase matching function when the phase relationship between the two systems changes after the standby system module is inserted and removed. That is,
In the case where the phases have been adjusted, if the phase after the standby system has returned is within the normal phase range and it is not necessary to perform the re-phase adjustment, the phase monitoring unit A2 of the standby system determines that there is no abnormality. In this case, the standby phase control unit fetches the readout phase of the active module and adjusts the phase. In other words, in the initial state, if the phase is within the normal phase range at the time of recovery from loss of synchronization between the two systems, a phase matching trigger is generated by the phase matching trigger control unit A4, and the variable delay circuit 114 , And 124, a fixed amount of delay is applied, and phase adjustment of both systems is executed. At this time,
By setting the phase-matched register section A3,
It is stored that both systems have been phase-matched.

Here, since the normal phase range cannot be determined at the time of module removal, re-phase adjustment is performed every time synchronization recovery is performed in the conventional method, and thus instantaneous interruption occurs. For the active module, the phase matching register unit A3 is not reset, the phase matching information is recognized when the standby module is inserted, and if the standby system and the active system are phase-matched, the operation is performed without changing the readout phase. As a result, there is no instantaneous interruption of the active system.

During operation, both the active module and the standby module monitor the state of the write phase / read phase of their own system by the phase monitor A2. When it is determined that the phase relationship has changed until the phase deviates from the normal phase range, "abnormal" is output as the W / R determination result, and the phase-matched register unit A3 is reset. In this case, if the system in which the W / R determination result is “abnormal” is the standby system module, the read phase of the active module is fetched, and the read phase of the system is adjusted to the fetched read phase. On the other hand, if the module is an active module, both the phase-matched register units A3 of the relevant system and the other system (standby system) are reset (set). As a result, re-phase adjustment is performed. Preferably, the configuration is as described above, but when the standby module is “abnormal”, if the phase adjustment of the standby module cannot be normally performed even by the read phase read from the active module, From the standby module to the working module,
May be reset, and re-phase adjustment may be performed.

As described above, the instantaneous interruption switching device SW of the present embodiment does not affect the readout phase of the active module at the time of module insertion / removal. In this case, the re-phase adjustment is performed only when an abnormality occurs in the active module or in a special case where the phase adjustment of the standby module cannot be performed, so that the occurrence of instantaneous interruption can be prevented as much as possible.

[0033]

Next, embodiments of the present invention will be described specifically.
In this embodiment, when each of the system modules is inserted or removed due to a failure or the like in a state where the phases of the system 0 and the system 1 have been adjusted with reference to the read phase on the large delay side (system 1) at the time of initial setting or resetting. Here is an example.

As a premise, it is assumed that the phase matching information is held in the phase matched register section A3 of each system, and that when the standby module is removed, the readout phase of the operating module does not change. In other words, if the active module holds the phase-matched state when the standby module is inserted, even if the standby module is a module that generates a reference phase for phase matching even if the delay module is on the large delay side, The read phase of the system module is fetched, and thereafter it can be operated as it is within the normal phase range.

First, an example in which the first system module is inserted and removed will be described with reference to FIG. In this case, the 1-system module is a standby system module, and the 0-system module is an operation module. The 1-system module restores synchronization after re-insertion, and refers to the phase matching information from the 0-system module that is the active system. Then, the phase state at the time of insertion is determined, and if the deviation due to the phase fluctuation is out of the normal phase range, the readout phase of the 0-system module is taken in and the phase is adjusted.
It should be noted that, even within the normal phase range, there is no problem in taking in the readout phase of the 0-system module and performing phase adjustment. At this time, the reference of the readout phase has not been changed from the initial setting even if there is a slight change in the transmission path phase, and thereafter, both modules continue to operate as they are. As a result, instantaneous interruption due to unnecessary re-phase adjustment can be prevented.

Next, with reference to FIG. 8B, an example in which the standby system module on the small delay side is inserted and removed will be described. In this case, the 1-system module is an operating module, and the 0-system module is a standby module. The 0-system module restores the synchronization after the re-insertion, and refers to the phase matching information from the 1-system module. Then, the phase state at the time of insertion is determined, and the shift due to the phase fluctuation is determined. However, since the delay amount is small in this system, in most cases, the readout phase of the active system of one system (that is, the phase on the large delay side) is changed. It suffices to just take in and perform phase matching. That is, there is no need to perform re-phase adjustment. At this time, even if there is some fluctuation in the transmission line phase, the reference of the readout phase has not been changed from the initial setting. Therefore, if it is within the normal phase range, both modules continue to operate. As described above, according to the present invention, it is possible to realize an automatic phase matching method in which re-phase matching does not occur when a module is inserted or removed.

[0037]

As is clear from the above description, according to the present invention, the automatic phase matching method which minimizes the re-phase matching and minimizes the instantaneous interruption caused by the re-phase matching, and the method according to the present invention. The adopted instantaneous interruption switching device can be realized.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of an instantaneous interruption switching device according to an embodiment of the present invention. FIG. 1A shows a case where a path length a is larger than a path length b, and FIG. The case of is shown.

FIG. 2 is a specific configuration diagram of the hitless switching device of the present embodiment.

FIG. 3 is a more detailed configuration diagram of a phase control unit shown in FIG. 2;

FIG. 4A is an explanatory diagram of input / output signals of a phase determination unit,
(B) shows the own system write address W- input to the phase determination unit.
FIG. 9 is a timing chart showing ADD and another system write frame pulse W-FP and a phase determination result output from the phase determination unit, and shows an example in which transmission data of the own system is later than transmission data of the other system. .

FIG. 5A is an explanatory diagram of input / output signals of a phase monitoring unit,
(B) is the information of the self-system out-of-synchronization, the self-system phase matching notification, the self-system write address W-ADD, and the self-system read frame pulse R-FP that are input to the phase monitoring unit, and are output from the phase monitoring unit. FIG. 9 is a timing chart showing a write / read (W / R) determination result.

6A is an explanatory diagram of input / output signals of a phase-matched register unit, FIG. 6B is a trigger input timing input to the phase-matched register unit, W / R determination results of own system and another system, FIG. 9 is a timing chart showing information on the out-of-synchronization of the own system or the other system and the conditions for setting / resetting the phase-matched notification output from the phase-matched register unit.

FIG. 7A is an explanatory diagram of input / output signals of a phase matching trigger control unit, and FIG. 7B is an OR gate for determining a logical sum of self-system / other-system out-of-synchronization information input to the phase matching trigger control unit; G1 output, output of AND gate G2 for determining logical product of self-system / other system out-of-synchronization information, output of AND gate G3 for determining logical product of self-system / other system phase-matched notification, and phase matching trigger control FIG. 7 is a timing chart showing a command FP output from a unit and output / stop conditions of trigger input timing.

8A and 8B are timing charts for explaining the operation in the circuit configuration shown in FIG. 2; FIG. 8A shows a case where a side with a large delay amount is inserted and removed; FIG. Here is an example.

FIG. 9 is a basic configuration diagram of a conventional hitless switching device, and (a) of FIG.
Shows the case where path length a> path length b, (b) shows the case where path length b> path length a, and (c) shows the case where path length b> path length a (after re-phase matching).

FIGS. 10 (a) to (c) show FIGS. 5 (a) to (c), respectively.
FIG. 9 is a timing chart for explaining the operation in the case of FIG.

FIG. 11 is a configuration diagram of a conventional hitless switching device.

12A and 12B are timing charts for explaining the operation in the configuration shown in FIG. 7; FIG. 12A shows an example in which a side with a large delay amount is inserted and removed; Is shown.

[Explanation of symbols]

 X1, Y1, 13 Phase determination unit X2, Y2, memory circuit unit X3, Y3 Phase control unit 14 Selector A1 Phase determination unit A2 Phase monitoring unit A3 Phase adjusted register unit A4 Phase alignment trigger control unit 111, 121 Delay control memory (MEM) 112, 122 Synchronization detection circuit (SYNC) 113, 123 Write address counter (W-CTR) 114, 124 Variable delay circuit (DLY) 115, 125 Read address counter (R-CTR) 116, 126 Phase control unit (CONT) G1 OR gate G2, G3 AND gate

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshiaki Kikuchi 3-18-21 Shibaura, Minato-ku, Tokyo Nippon Electric Engineering Co., Ltd. (56) References JP-A-3-181243 (JP, A) (58 ) Surveyed field (Int.Cl. ⁶ , DB name) H04L 1/22 H04J 3/00

Claims (8)

(57) [Claims] A delay circuit for delaying an output phase of the transmission data; and a phase controller for controlling a delay amount of the delay circuit. The phase control unit of each system performs the transmission data input to its own system.
And the output from the delay circuit section
Phase determination of the transmitted data
And the phase status information of the transmission data after delay
To the control unit and refer to the phase status information of both systems to
Determines whether delay control is required after system module is inserted or removed
Phasing method is, and executes the control of the delay amount in a case requiring control. Wherein said phase control section of the system, in the self-system
It said delay amount control was required and the self-system of the delay circuit to match to the other system output phase of the transmission data if the <br/> phasing in the phase control unit of the other system is been finished in 2. The phase matching method according to claim 1, wherein the delay amount is controlled. 3. A non-volatile memory for holding phase matching information indicating whether or not phase matching of transmission data between the own system and another system has been completed, wherein the phase control unit of each system includes: Means for monitoring the synchronization state and input / output phase of the transmission data of the other system, and means for resetting the phase matching information in the memory according to the monitoring result. 3. The phase matching method according to claim 1, wherein the control unit determines whether control of the delay circuit unit of the own system is necessary. 4. A means for comparing each phase of transmission data input to a module of the own system and a phase of transmission data input to a module of another system to detect a relative phase delay amount of the own system, 3. The phase according to claim 1, further comprising means for determining whether or not the amount of phase delay is within a predetermined range, and determining whether control of the delay circuit unit of the own system is necessary or not according to the determination result. Matching method. 5. When one of the plurality of systems is an active system and the other is a standby system, and a standby system module can be inserted into and removed from a transmission line of the system, the standby module inserted after removal is removed. When the control of the delay circuit unit is required in the system, the phase control unit includes an output phase of the transmission data from the operating system module whose phase has been adjusted, and controls the own system so as to match the acquired output phase. 4. The phase matching method according to claim 1, wherein the delay circuit section is controlled. 6. The phase control unit included in an operation system module resets phase matching information in the memory of the own system when the relative phase delay amount in the own system deviates from the predetermined range. 6. The phase matching method according to claim 5, wherein the phase matching information in the memory of another system is reset. 7. A first delay circuit section for delaying transmission data input to a first system, and a first delay circuit for determining a phase of the transmission data input to the first system. The phase of the transmission data output from the section is determined,
A first module including a first phase control unit that controls a delay amount of the first delay circuit unit based on each phase determination result; and a second module that delays transmission data input to a second system. A delay circuit unit, and a phase determination of transmission data output from the first delay circuit unit while performing a phase determination of transmission data input to the second system, based on each phase determination result A second module including a second phase control unit for controlling a delay amount of the second delay circuit unit; and a data switch for selectively outputting transmission data output from the first and second modules. Means, wherein the first and second phase control units respectively transfer the phase determination result and phase state information of the transmission data after delay, and refer to the phase state information of both systems to determine the own module. Delay control after insertion and removal of Hitless switching apparatus characterized by rows. 8. One of the first and second systems is an active system,
The other is a standby system, the first and second delay circuit units each include a synchronization detection circuit for detecting a synchronization signal from input transmission data, a memory for sequentially writing input transmission data, Memory write control means for performing write control on the memory based on the synchronization signal detected by the detection circuit; a variable delay circuit for delaying the synchronization signal;
A memory read control unit for performing read control of transmission data written in the memory based on the synchronization signal delayed by the variable delay circuit, wherein the first and second phase control units each And the control information of the memory write control means and the control information of the memory read control means of the other system, and the variable delay circuit which determines the phase state of both systems from the input information so that the phases of both systems match. Delay amount control means for controlling the delay amount of the two systems, storage means for storing the delay amounts of both systems obtained by the delay amount control means as phase matching information, and the phase matching information stored by the storage means 8. A re-phasing execution means for sending to the standby module at the time of executing the phase matching after the module is inserted and removed.
The instantaneous interruption switching device according to the above.