JP2746203B2 - Transmission path non-stop switching system and method - Google Patents

Transmission path non-stop switching system and method

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Publication number
JP2746203B2
JP2746203B2 JP7130214A JP13021495A JP2746203B2 JP 2746203 B2 JP2746203 B2 JP 2746203B2 JP 7130214 A JP7130214 A JP 7130214A JP 13021495 A JP13021495 A JP 13021495A JP 2746203 B2 JP2746203 B2 JP 2746203B2
Authority
JP
Japan
Prior art keywords
main signal
transmission line
standby
signal
working
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7130214A
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Japanese (ja)
Other versions
JPH08331105A (en
Inventor
唱也 福島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7130214A priority Critical patent/JP2746203B2/en
Publication of JPH08331105A publication Critical patent/JPH08331105A/en
Application granted granted Critical
Publication of JP2746203B2 publication Critical patent/JP2746203B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Maintenance And Management Of Digital Transmission (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、伝送路無瞬断切替シス
テムおよび方法に関し、特に複数の現用系伝送路のうち
の1つを予備系伝送路に無瞬断で切り替える伝送路無瞬
断切替システムおよび方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system and method for instantaneously switching transmission lines, and more particularly, to a transmission line without instantaneous interruption in which one of a plurality of active transmission lines is switched to a standby transmission line without interruption. The present invention relates to a switching system and method.

【0002】[0002]

【従来の技術】従来、1つの現用系伝送路に対して1つ
の予備系伝送路が設けられている1:1の冗長系伝送路
を無瞬断で切り替える切替システムは、図4に示すよう
な構成となっていた(例えば、特開平4−243335
号公報など)。送信装置50に入力された主信号は、識
別信号挿入部51で所定の識別信号が挿入され、分岐部
52で分岐され同一の主信号が現用系伝送路L10およ
び予備系伝送路L11に出力される。
2. Description of the Related Art Conventionally, a switching system for switching a 1: 1 redundant transmission line in which one active transmission line is provided for one active transmission line without instantaneous interruption is shown in FIG. (For example, Japanese Patent Application Laid-Open No. 4-243335).
Issue publication). The main signal input to the transmitting device 50 is inserted with a predetermined identification signal by an identification signal insertion unit 51, is branched by a branching unit 52, and the same main signal is output to the working transmission line L10 and the protection transmission line L11. You.

【0003】受信装置60の時間差検出部61により現
用系および予備系の主信号に挿入されている識別信号に
基づいて両主信号の時間差が検出され、この時間差に基
づいて制御部62により各遅延部63,64の遅延時間
が制御される。これにより遅延部63,64から出力さ
れる現用系および予備系主信号の時間差がなくなり、切
替部65にて現用系から予備系に無瞬断で切り替えらる
ものとなっていた。
The time difference between the two main signals is detected by the time difference detecting section 61 of the receiving apparatus 60 based on the identification signals inserted into the main signals of the working system and the standby system, and each delay is controlled by the control section 62 based on the time difference. The delay times of the units 63 and 64 are controlled. As a result, the time difference between the active system and the standby main signal output from the delay units 63 and 64 is eliminated, and the switching unit 65 switches from the active system to the standby system without interruption.

【0004】[0004]

【発明が解決しようとする課題】したがって、このよう
な従来の伝送路無瞬断切替方法を、複数の現用系伝送路
に対して1つの予備系伝送路が設けられている1:Nの
冗長系伝送路に用いた場合には、1つの現用系と予備系
とを組として遅延時間の制御が行われるものとなるが、
各組の現用系の遅延時間がそれぞれの線路長などにより
異なることから、共通に用いられる予備系の遅延時間が
定まらず、各伝送路の受信側に設けられている遅延部の
制御が複雑化するとともに、主信号がより高速な場合に
はその処理遅延が主信号に影響を与えかねないという問
題点があった。本発明はこのような課題を解決するため
のものであり、簡単な遅延制御で1:Nの冗長系伝送路
における無瞬断切替を実現することが可能な伝送路無瞬
断切替システムおよび方法を提供することを目的として
いる。
Therefore, such a conventional transmission line non-stop switching method is applied to a 1: N redundancy system in which one protection transmission line is provided for a plurality of active transmission lines. When used for the system transmission line, the delay time is controlled as one set of the working system and the protection system.
Since the delay time of each working system differs depending on the line length, etc., the delay time of the commonly used protection system is not determined, and the control of the delay unit provided on the receiving side of each transmission line becomes complicated. In addition, when the speed of the main signal is higher, there is a problem that the processing delay may affect the main signal. The present invention is intended to solve such a problem, and a transmission line non-interruptible switching system and method capable of realizing non-interruptible switching in a 1: N redundant transmission line with simple delay control. It is intended to provide.

【0005】[0005]

【課題を解決するための手段】このような目的を達成す
るために、本発明による伝送路無瞬断切替システムは、
送信側に、それぞれの現用系伝送路に出力される現用系
主信号に所定の基準フレーム信号を重畳する基準フレー
ム信号重畳部手段と、基準フレーム信号が重畳された各
現用系主信号のうちいずれかを選択し予備系主信号とし
て予備系伝送路に出力する第1の切替手段とを備え、受
信側に、各現用系伝送路および予備系伝送路ごとに設け
られ、受信したそれぞれの現用系主信号および予備系主
信号を一時的に記憶するバッファメモリと、各現用系伝
送路ごとに設けられ、各現用系主信号を対応するバッフ
ァメモリに書込む書込み制御を行う第1の主信号インタ
ーフェース手段と、予備系主信号を対応するバッファメ
モリに書込む書込み制御を行うとともに、予備系主信号
に重畳されている基準フレーム信号に基づく同一タイミ
ングですべてのバッファメモリに記憶されている現用系
主信号および予備系主信号を読出す読出し制御を行う第
2の主信号インターフェース手段と、各現用系伝送路ご
とに設けられ、各現用系主信号と予備系主信号とのいず
れかを選択出力する第2の切替手段とを備え、第1の切
替手段と第2の主信号インターフェース手段との間に設
けられ、すべての現用系主信号に比較して受信側におけ
る受信位相が最も遅れるように予備系主信号に対して遅
延を与える遅延手段を備えたものである。
In order to achieve the above object, a transmission line non-stop switching system according to the present invention comprises:
On the transmitting side, reference frame signal superimposing means for superimposing a predetermined reference frame signal on the working main signal output to each working transmission line, and any of the working main signals on which the reference frame signal is superimposed. And first switching means for selecting the active system and outputting the standby system main signal to the standby system transmission line. The first switching unit is provided on the receiving side for each of the active system transmission line and the standby system transmission line. A buffer memory for temporarily storing a main signal and a standby main signal, and a first main signal interface provided for each active transmission line and performing write control for writing each active main signal to a corresponding buffer memory Means and write control for writing the standby system main signal into the corresponding buffer memory, and all buffers are controlled at the same timing based on the reference frame signal superimposed on the standby system main signal. Second main signal interface means for performing read control for reading the active main signal and the standby main signal stored in the active memory, and provided for each active transmission line, each active main signal and the standby main signal. A second switching means for selecting and outputting any one of a signal and a signal provided between the first switching means and the second main signal interface means. And a delay means for delaying the standby system main signal so that the reception phase of the signal is the most delayed.

【0006】また、本発明による伝送路無瞬断切替方法
は、受信側であって、各現用系伝送路および予備系伝送
路ごとに、各現用系伝送路および予備系伝送路から受信
したそれぞれの現用系主信号および予備系主信号を一時
的に記憶するバッファメモリを設けて、送信側から、各
現用系伝送路に出力される現用系主信号に対して所定の
基準フレーム信号を重畳して送信するとともに、基準フ
レーム信号が重畳された各現用系主信号のうち切替対象
となる現用系主信号を選択し予備系主信号として予備系
伝送路に送信し、すべての現用系主信号に比較して受信
側における受信位相が遅れるように予備系主信号に対し
て遅延を与え、受信側で、各現用系主信号および遅延が
与えられた予備系主信号を各バッファメモリに順次記憶
し、遅延が与えられた予備系主信号に重畳されている基
準フレーム信号に基づく同一タイミングで、各バッファ
メモリに記憶されている各現用系主信号および予備系主
信号を読出し、切替対象となる現用系主信号と予備系主
信号のいずれかを切替出力するようにしたものである。
Further, the method for instantaneously switching transmission lines according to the present invention is characterized in that, on the receiving side, for each of the working transmission line and the protection transmission line, each of the transmission lines received from each of the working transmission line and the protection transmission line. A buffer memory for temporarily storing the working main signal and the protection main signal is provided, and a predetermined reference frame signal is superimposed on the working main signal output from the transmitting side to each working transmission line. Of the active system main signal on which the reference frame signal is superimposed, select the active system main signal to be switched, transmit it to the standby system transmission line as the standby system main signal, and send it to all the active system main signals. In comparison, a delay is given to the standby main signal so that the reception phase on the receiving side is delayed, and each active main signal and the delayed standby main signal are sequentially stored in each buffer memory on the receiving side. Given the delay At the same timing based on the reference frame signal superimposed on the standby main signal, the active main signal and the standby main signal stored in each buffer memory are read out, and the active main signal to be switched and the standby main signal are read out. One of the system main signals is switched and output.

【0007】[0007]

【作用】したがって、送信側から、各現用系伝送路に出
力される現用系主信号に対して所定の基準フレーム信号
が重畳されて送信されるとともに、基準フレーム信号が
重畳された各現用系主信号のうち切替対象となる現用系
主信号が選択されて予備系主信号として予備系伝送路に
送信され、受信側で、各現用系主信号および遅延が与え
られた予備系主信号が各バッファメモリに順次記憶さ
れ、遅延が与えられた予備系主信号に重畳されている基
準フレーム信号に基づく同一タイミングで、各バッファ
メモリに記憶されている各現用系主信号および予備系主
信号が読出され、切替対象となる現用系主信号と予備系
主信号のいずれかが切替出力される。
Therefore, a predetermined reference frame signal is superimposed on the working main signal output to each working transmission line from the transmitting side and transmitted, and each working main signal on which the reference frame signal is superimposed is transmitted. The active main signal to be switched among the signals is selected and transmitted to the standby transmission line as a standby main signal, and on the receiving side, each active main signal and the standby main signal to which a delay is given are buffered. The active main signal and the standby main signal stored in each buffer memory are read out at the same timing based on the reference frame signal superimposed on the standby main signal which is sequentially stored in the memory and delayed. Either the active main signal or the standby main signal to be switched is switched and output.

【0008】[0008]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例である伝送路無瞬断切替シ
ステムのブロック図であり、特に2つの現用系伝送路と
1つの予備系伝送路とからなる1:N(N=2)の冗長
系伝送路を例として示している。
Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a transmission line non-stop switching system according to one embodiment of the present invention. In particular, a 1: N (N = 2) 1: N system including two working transmission lines and one protection transmission line. A redundant transmission line is shown as an example.

【0009】同図において、1は送信装置、2は受信装
置、L0は予備系伝送路、L1,L2は独立した現用系
伝送路である。送信装置1において、11,12は各現
用系伝送路の現用系主信号に対して所定の基準フレーム
信号を重畳する基準フレーム信号重畳部、13,14は
基準フレーム信号が重畳された現用系主信号のうちのい
ずれかを予備系主信号として予備系伝送路L0に送信す
るための切替部(第1の切替手段)、15はすべての現
用系主信号に比較して受信側における予備系主信号の受
信位相が最も遅れるように予備系主信号を遅延させる遅
延部である。
In FIG. 1, 1 is a transmitting device, 2 is a receiving device, L0 is a protection transmission line, and L1 and L2 are independent working transmission lines. In the transmitting apparatus 1, reference numerals 11 and 12 denote reference frame signal superimposing sections for superimposing a predetermined reference frame signal on an active main signal of each active transmission line. A switching unit (first switching means) 15 for transmitting any one of the signals as a standby system main signal to the standby system transmission line L0, a standby system main unit 15 on the receiving side as compared with all the active system main signals. This is a delay unit that delays the standby main signal so that the reception phase of the signal is the most delayed.

【0010】受信装置2において、21,22は現用系
および現用系伝送路L1,L2から受信した現用系主信
号から基準フレーム信号を抽出し、書込み制御信号3
5,36を生成出力する主信号インターフェース部(以
下、主信号I/F部という:第1の主信号インターフェ
ース手段)、23は予備系伝送路L0から受信した予備
系主信号から基準フレーム信号を抽出し、書込み制御信
号37および読出し制御信号38を生成出力する主信号
インターフェース部(以下、主信号I/F部という:第
2の主信号インターフェース手段)、24〜26は各書
込み制御信号35〜37に基づいて各伝送路の主信号を
順次記憶するとともに、読出し制御信号38に基づいて
各主信号を同一位相で出力するバッファメモリ部、2
7,28は各現用系主信号と予備系主信号とのいずれか
を切替出力する切替部(第2の切替手段)である。
In the receiving apparatus 2, reference numerals 21 and 22 extract a reference frame signal from a working system and a working system main signal received from the working system transmission lines L1 and L2, and write control signal 3
A main signal interface section (hereinafter, referred to as main signal I / F section: first main signal interface means) for generating and outputting 5, 36 generates a reference frame signal from the standby main signal received from the standby transmission line L0. A main signal interface section (hereinafter, referred to as a main signal I / F section: second main signal interface means) that extracts and generates and outputs a write control signal 37 and a read control signal 38; A buffer memory unit for sequentially storing the main signals of the respective transmission paths based on the read control signal and outputting the main signals in the same phase based on the read control signal;
Reference numerals 7 and 28 denote switching units (second switching means) for switching and outputting any of the active system main signal and the standby system main signal.

【0011】また図2は、バッファメモリ部24〜26
を示すブロック図であり、同図において、32は読出し
制御信号38に応じて所定値から計数動作を開始するこ
とにより読出しアドレスを生成するカウンタ、31は書
込み制御信号35に基づいて主信号を順に記憶するとと
もに、カウンタ32の読出しアドレスに基づいて記憶し
ている主信号を出力するバッファメモリ(エラスティッ
クストア)である。
FIG. 2 shows buffer memory sections 24-26.
In the figure, reference numeral 32 denotes a counter for generating a read address by starting a counting operation from a predetermined value in response to a read control signal 38, and 31 a main signal in order based on a write control signal 35. A buffer memory (elastic store) that stores and outputs the stored main signal based on the read address of the counter 32.

【0012】次に、図3を参照して、本発明の動作とし
て、現用系伝送路L1から予備系伝送路L0に切替制御
する場合について説明する。図3は伝送路切替手順を示
すフローチャートである。まず、送信装置1に入力され
た各主信号は、基準フレーム信号重畳部11,12にて
所定の基準フレーム信号が重畳される。ここで、送信装
置1の切替部13が現用伝送路L1側に切り替えられ、
現用系伝送路L1の主信号と同一の主信号が遅延部15
に出力される(ステップ41)。
Next, with reference to FIG. 3, a description will be given of the operation of the present invention in which the switching from the working transmission line L1 to the protection transmission line L0 is controlled. FIG. 3 is a flowchart showing a transmission path switching procedure. First, a predetermined reference frame signal is superimposed on each main signal input to the transmitting apparatus 1 by the reference frame signal superimposing units 11 and 12. Here, the switching unit 13 of the transmission device 1 is switched to the working transmission line L1 side,
The same main signal as the main signal of the working transmission line L1 is supplied to the delay unit 15
(Step 41).

【0013】遅延部15には、各伝送路による遅延量の
バラツキを考慮して、予備系主信号が受信装置2の受信
位相においてすべての現用系主信号よりも遅延するよう
な遅延量が予め設定されており、予備系主信号はいずれ
の現用系主信号よりも遅延した位相で受信装置2にて受
信される。各現用系主信号および予備系主信号は、受信
装置2の主信号I/F部21〜23で受信され、それぞ
れ所定の書込み位相(例えば、受信したJ1バイトの6
4マルチフレーム位相)を有する書込み制御信号35〜
37が生成され、バッファメモリ部24〜26内のバッ
ファメモリ31に書込まれる。
In the delay unit 15, a delay amount such that the standby main signal is delayed from all the active main signals in the reception phase of the receiving device 2 is considered in advance in consideration of the dispersion of the delay amount due to each transmission path. The protection main signal is set, and is received by the receiver 2 with a phase delayed from any of the working main signals. Each of the active system main signal and the standby system main signal is received by the main signal I / F sections 21 to 23 of the receiving device 2 and has a predetermined write phase (for example, 6 bits of the received J1 byte).
Write control signal 35 to
37 is generated and written into the buffer memory 31 in the buffer memory units 24-26.

【0014】また、予備系の主信号I/F部23では、
予備系主信号に重畳されている基準フレーム信号を基準
とし、さらに予備系の位相変動分を加えた読出し制御信
号38が生成され、各バッファメモリ部24〜26に対
して共通に供給される。したがって、最も遅延している
予備系の基準フレーム信号に基づく読出し制御信号38
が各バッファメモリ部24〜26に出力された時点で、
各現用系主信号および予備系主信号のバッファメモリ3
1への書込みがすでに終了していることになり、この読
出し制御信号38に基づいて書くバッファメモリ31か
ら主信号が同一タイミングで読出される(ステップ4
2)。
In the main signal I / F section 23 of the standby system,
A read control signal 38 is generated based on the reference frame signal superimposed on the standby main signal and further added with the amount of phase fluctuation of the standby system, and is commonly supplied to the buffer memory units 24 to 26. Therefore, the read control signal 38 based on the reference frame signal of the standby system which is delayed most.
Is output to each of the buffer memory units 24-26,
Buffer memory 3 for each working main signal and standby main signal
1, the main signal is read from the buffer memory 31 to be written based on the read control signal 38 at the same timing (step 4).
2).

【0015】この場合、各バッファメモリ部24〜26
のカウンタ32は、主信号の伝送レートに応じた速度で
常に計数動作しており、読出し制御信号38に応じてそ
のカウンタ値すなわちアドレスがリセットされ、所定の
アドレスすなわち主信号の書込み先頭アドレスから順に
読出しアドレスを生成出力する。このようにして現用系
主信号および予備系主信号は、各バッファメモリ部24
〜26から同一タイミングで読出され、切替部27でい
ずれかが選択され出力される(ステップ43)。
In this case, each of the buffer memory units 24-26
Counter 32 always counts at a speed corresponding to the transmission rate of the main signal, and its counter value, that is, the address, is reset in response to the read control signal 38. Generates and outputs a read address. In this way, the active main signal and the standby main signal are stored in each buffer memory unit 24.
To 26 are read out at the same timing, and one is selected and output by the switching unit 27 (step 43).

【0016】このように、予備系主信号を遅延させる遅
延部15を設けて、すべての現用系主信号に比較して予
備系主信号が受信側で最も遅延するようになし、その予
備系主信号の基準フレーム信号に基づいて生成された読
出し制御信号38に基づいて各現用系主信号および予備
系主信号をバッファメモリ31から読出すようにしたの
で、1:Nの冗長系伝送路においても比較的簡単な遅延
制御で正確な無瞬断切替が実現される。
As described above, the delay unit 15 for delaying the standby main signal is provided so that the standby main signal is delayed most on the receiving side as compared with all the active main signals. Since each of the active main signal and the standby main signal is read from the buffer memory 31 based on the read control signal 38 generated based on the reference frame signal of the signal, even in the 1: N redundant transmission line, Accurate instantaneous interruption switching is realized by relatively simple delay control.

【0017】なお、以上の説明において、予備系主信号
を遅延させる遅延部15を送信装置1に設けた場合につ
いて説明したが、切替部13以降であって主信号I/F
部23より前段の予備系であればいずれに設けてもよ
く、例えば受信装置2内であって主信号I/F部23よ
り前段に設けた場合でも、前述と同様の作用効果を奏す
るものとなる。また、現用系伝送路L1を予備系伝送路
L0に切り替える場合について説明したが、現用系伝送
路L2を予備系伝送路L0に切り替える場合、さらに現
用系伝送路が多数存在する場合でも前述と同様の作用効
果を奏するものである。
In the above description, a case has been described where the delay unit 15 for delaying the standby main signal is provided in the transmitting apparatus 1. However, the main signal I / F is provided after the switching unit 13.
It may be provided at any stage as long as it is a standby system upstream of the unit 23. For example, even in the case of being provided in the receiving device 2 and upstream of the main signal I / F unit 23, the same operation and effect as described above can be obtained. Become. Also, the case where the active transmission line L1 is switched to the standby transmission line L0 has been described, but the same applies to the case where the active transmission line L2 is switched to the standby transmission line L0 and also when there are many active transmission lines. The operation and effect of the present invention are achieved.

【0018】[0018]

【発明の効果】以上説明したように、本発明は、すべて
の現用系主信号に比較して受信側における受信位相が最
も遅れるように予備系主信号に対して遅延を与える遅延
手段を設けて、送信側から、所定の基準フレーム信号が
重畳された切替対象となる現用系主信号を予備系主信号
として予備系伝送路に送信し、受信側で、遅延手段によ
り遅延が与えられた予備系主信号に重畳されている基準
フレーム信号に基づいて、各バッファメモリに記憶され
ている各現用系主信号および予備系主信号を同一タイミ
ングで読出して、切替対象となる現用系主信号と予備系
主信号のいずれかを切替出力するようにしたので、複雑
な遅延制御を必要とすることなく、すべての現用系主信
号と予備系主信号とが同位相で出力されることになり、
1:Nの冗長系伝送路においても比較的簡単な遅延制御
で正確な無瞬断切替を実現することが可能となる。
As described above, according to the present invention, the delay means for delaying the backup main signal so that the reception phase on the receiving side is the most delayed compared to all the active main signals is provided. The transmitting side transmits a working main signal to be switched, on which a predetermined reference frame signal is superimposed, to the standby transmission line as a standby main signal, and the receiving side delays the standby system by the delay means. Based on the reference frame signal superimposed on the main signal, each active main signal and standby main signal stored in each buffer memory are read out at the same timing, and the active main signal to be switched and the standby main signal are read out. Since any one of the main signals is switched and output, all the working main signals and the standby main signal are output in the same phase without requiring complicated delay control,
Even in a 1: N redundant transmission line, accurate instantaneous interruption switching can be realized with relatively simple delay control.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の一実施例による伝送路無瞬断切替シ
ステムのブロック図である。
FIG. 1 is a block diagram of a transmission line hitless switching system according to an embodiment of the present invention.

【図2】 バッファメモリ部を示すブロック図である。FIG. 2 is a block diagram illustrating a buffer memory unit.

【図3】 伝送路切替手順を示すフローチャートであ
る。
FIG. 3 is a flowchart showing a transmission path switching procedure.

【図4】 従来の伝送路無瞬断切替システムのブロック
図である。
FIG. 4 is a block diagram of a conventional transmission path non-stop switching system.

【符号の説明】[Explanation of symbols]

1…送信装置、11,12…基準フレーム信号重畳部、
13,14…切替部(第1の切替手段)、15…遅延
部、2…受信装置、21,22…主信号インターフェー
ス部(主信号I/F部:第1の主信号インターフェース
手段)、23…主信号インターフェース部(主信号I/
F部:第2の主信号インターフェース手段)、24〜2
6…バッファメモリ部、27,28…切替部(第2の切
替手段)、31…バッファメモリ、32…カウンタ、3
5〜37…書込み制御信号、38…読出し制御信号、L
0…予備系伝送路、L1,L2…現用系伝送路。
1 ... Transmission device, 11 and 12 ... Reference frame signal superimposing unit,
13, 14 switching unit (first switching unit), 15 delay unit, 2 receiving device, 21, 22 main signal interface unit (main signal I / F unit: first main signal interface unit), 23 ... Main signal interface (main signal I /
F part: second main signal interface means), 24-2
6 buffer memory section, 27, 28 switching section (second switching means), 31 buffer memory, 32 counter, 3
5 to 37: write control signal, 38: read control signal, L
0: protection transmission line, L1, L2: working transmission line.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 送信側と受信側とを結ぶ複数の現用系伝
送路に対して1つの予備系伝送路が設けられている冗長
系伝送路に用いられ、主信号を瞬断させることなく現用
系伝送路のいずれかを予備系伝送路に切り替える伝送路
無瞬断切替システムにおいて、 送信側に、 それぞれの現用系伝送路に出力される現用系主信号に所
定の基準フレーム信号を重畳する基準フレーム信号重畳
部手段と、 基準フレーム信号が重畳された各現用系主信号のうちい
ずれかを選択し予備系主信号として予備系伝送路に出力
する第1の切替手段とを備え、 受信側に、 各現用系伝送路および予備系伝送路ごとに設けられ、受
信したそれぞれの現用系主信号および予備系主信号を一
時的に記憶するバッファメモリと、 各現用系伝送路ごとに設けられ、各現用系主信号を対応
するバッファメモリに書込む書込み制御を行う第1の主
信号インターフェース手段と、 予備系主信号を対応するバッファメモリに書込む書込み
制御を行うとともに、予備系主信号に重畳されている基
準フレーム信号に基づく同一タイミングですべてのバッ
ファメモリに記憶されている現用系主信号および予備系
主信号を読出す読出し制御を行う第2の主信号インター
フェース手段と、 各現用系伝送路ごとに設けられ、各現用系主信号と予備
系主信号とのいずれかを選択出力する第2の切替手段と
を備え、 第1の切替手段と第2の主信号インターフェース手段と
の間に設けられ、すべての現用系主信号に比較して受信
側における受信位相が最も遅れるように予備系主信号に
対して遅延を与える遅延手段を備えることを特徴とする
伝送路無瞬断切替システム。
The present invention is used for a redundant transmission line in which one protection transmission line is provided for a plurality of active transmission lines connecting a transmission side and a reception side. In a transmission line hitless switching system that switches any one of the system transmission lines to a protection system transmission line, a reference that superimposes a predetermined reference frame signal on the working main signal output to each working transmission line on the transmitting side. Frame signal superimposing means; and first switching means for selecting one of the working main signals on which the reference frame signal is superimposed and outputting the selected main signal to the protection transmission line as a protection main signal. A buffer memory provided for each of the working transmission line and the protection transmission line and temporarily storing the received main and protection main signals, and a buffer memory provided for each of the working transmission lines. Working main signal First main signal interface means for performing write control for writing to a corresponding buffer memory; and reference frame signal for performing write control for writing a standby system main signal to a corresponding buffer memory and superimposed on the standby system main signal. Second main signal interface means for performing read control for reading the active main signal and the standby main signal stored in all the buffer memories at the same timing based on A second switching means for selectively outputting either the working system main signal or the protection system main signal; provided between the first switching means and the second main signal interface means; A transmission line having a delay means for delaying a backup main signal so that a reception phase on the receiving side is delayed most as compared with the main signal. Cross-sectional switching system.
【請求項2】 送信側と受信側とを結ぶ複数の現用系伝
送路に対して1つの予備系伝送路が設けられている冗長
系伝送路に用いられ、主信号を瞬断させることなく現用
系伝送路のいずれかを予備系伝送路に切り替える伝送路
無瞬断切替システムにおいて、 受信側であって、各現用系伝送路および予備系伝送路ご
とに、各現用系伝送路および予備系伝送路から受信した
それぞれの現用系主信号および予備系主信号を一時的に
記憶するバッファメモリを設けて、 送信側から、各現用系伝送路に出力される現用系主信号
に対して所定の基準フレーム信号を重畳して送信すると
ともに、基準フレーム信号が重畳された各現用系主信号
のうち切替対象となる現用系主信号を選択し予備系主信
号として予備系伝送路に送信し、 すべての現用系主信号に比較して受信側における受信位
相が遅れるように予備系主信号に対して遅延を与え、 受信側で、各現用系主信号および遅延が与えられた予備
系主信号を各バッファメモリに順次記憶し、遅延が与え
られた予備系主信号に重畳されている基準フレーム信号
に基づく同一タイミングで、各バッファメモリに記憶さ
れている各現用系主信号および予備系主信号を読出し、
前記切替対象となる現用系主信号と予備系主信号のいず
れかを切替出力するようにしたことを特徴とする伝送路
無瞬断切替方法。
2. A redundant transmission line provided with one standby transmission line for a plurality of active transmission lines connecting a transmission side and a reception side, and is used without instantaneous interruption of a main signal. In the transmission line uninterruptible switching system for switching any of the system transmission lines to the protection system transmission line, on the receiving side, for each of the working system transmission line and the protection system transmission line, each of the working system transmission line and the protection system transmission line A buffer memory is provided for temporarily storing each of the active main signal and the standby main signal received from the transmission line, and a predetermined reference is made to the active main signal output from the transmission side to each of the active transmission lines. The superimposed frame signal is transmitted, and the active main signal to be switched is selected from among the active main signals on which the reference frame signal is superimposed, and transmitted as a standby main signal to the standby transmission line. Compare with the current main signal Then, a delay is given to the backup main signal so that the reception phase on the reception side is delayed. At the reception side, each working main signal and the standby backup main signal given delay are sequentially stored in each buffer memory, At the same timing based on the reference frame signal superimposed on the delayed standby main signal, each active main signal and standby main signal stored in each buffer memory are read out,
A method for non-instantaneous transmission line switching, wherein one of the working main signal and the standby main signal to be switched is switched and output.
JP7130214A 1995-05-29 1995-05-29 Transmission path non-stop switching system and method Expired - Lifetime JP2746203B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7130214A JP2746203B2 (en) 1995-05-29 1995-05-29 Transmission path non-stop switching system and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7130214A JP2746203B2 (en) 1995-05-29 1995-05-29 Transmission path non-stop switching system and method

Publications (2)

Publication Number Publication Date
JPH08331105A JPH08331105A (en) 1996-12-13
JP2746203B2 true JP2746203B2 (en) 1998-05-06

Family

ID=15028823

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7130214A Expired - Lifetime JP2746203B2 (en) 1995-05-29 1995-05-29 Transmission path non-stop switching system and method

Country Status (1)

Country Link
JP (1) JP2746203B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5194997B2 (en) * 2008-04-28 2013-05-08 沖電気工業株式会社 Redundant switching control system, method and program

Also Published As

Publication number Publication date
JPH08331105A (en) 1996-12-13

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