JP3196891B2 - Frame phase synchronization / bit phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame phase synchronization / bit phase synchronization phase synchronization circuit, and more particularly to a frame phase synchronization / bit phase synchronization phase synchronization circuit in a digital line transmission apparatus.

[0002]

2. Description of the Related Art In the prior art, a phase synchronization circuit (frame phase synchronization / bit phase synchronization) is examined for each phase synchronization system, and in each system, a phase difference detection unit and a phase difference adjustment unit are used as basic components. Consists of

FIG. 3 is a block diagram showing a configuration of a conventional bit phase synchronization circuit.

Referring to FIG. 3, in a conventional bit phase synchronization circuit, a bit phase difference detecting section 306 receives clocks 330 and 331 from each network, detects a bit phase difference between clocks, and detects a bit phase difference. A bit phase control 370 corresponding to the bit phase difference is output to adjusting section 305. The bit phase difference adjusting unit 305 includes clocks 330 and 3 from each network.
31 and the data 360 and 361 are input, and the data 36 is synchronized with the clocks 330 and 331 from each network by the bit phase control 370 from the bit phase difference detector 306.
2, 363 are output to perform bit phase synchronization.

FIG. 4 is a block diagram showing a configuration of a conventional frame phase synchronization circuit.

Referring to FIG. 4, in a conventional frame phase synchronization circuit, a frame phase difference detecting section 308 detects clocks 330 and 331 and a frame pulse 34 from each network.
0 and 341 are input, a frame phase difference is detected, and a frame phase control 371 according to the frame phase difference is output to the frame phase difference adjusting unit 307. Frame phase difference adjuster 3
07 is a clock 330, 331 and data 3 from each network.
60 and 361 are input, and the data 362 and 363 are output in synchronization with the clocks 330 and 331 from the respective networks by the frame phase control 371 from the frame phase difference detector 308 to perform frame phase synchronization.

[0007] Recently, there are few techniques for realizing each phase synchronization with the minimum necessary delay amount by sharing the above phase synchronization circuits.
For example, in a conventional example disclosed in Japanese Patent Application Laid-Open No. 5-83239, a two-stage configuration of a bit phase buffer / frame phase buffer shares a phase synchronization circuit. Unnecessary delay occurs due to the buffer. Also, Japanese Patent Application Laid-Open No. Hei 4-200227
In the conventional example disclosed in Japanese Patent Application Laid-Open Publication No. H11-176, each frame / bit phase synchronization is realized, but it is assumed that the phase synchronization target is between dependent synchronization stations, and is applied to phase synchronization between different networks. Can not.

[0008]

A first problem is that, in the prior art, when an apparatus for concentrating and transmitting digital lines between different networks performs phase synchronization (frame phase synchronization / bit phase synchronization), bit synchronization is difficult. This means that an unnecessary amount of delay occurs during the execution of the phase synchronization.

This is a phase synchronization circuit for frame phase synchronization, in which each phase synchronization of the frame phase synchronization and the bit phase synchronization is performed. Therefore, a delay in the frame synchronization circuit which is unnecessary in the bit phase synchronization is included. This is because

A second problem is that, in the prior art, when phase synchronization (frame phase synchronization / bit phase synchronization) is performed by a device for concentrating and transmitting digital lines between different networks,
The provision of both phase-locked loops in order to distribute the phase-locked loops to the respective phase-locked loops suitable for each line and to provide the phase-locked loop increases the circuit scale.

The reason is that there is no phase synchronization circuit prepared which can cope with both the frame phase synchronization and the bit phase synchronization.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase synchronization circuit for frame phase synchronization / bit phase synchronization in which the circuit scale is small and the amount of delay during bit phase synchronization is minimized.

[0013]

A frame phase synchronizing / bit phase synchronizing circuit according to the present invention is a frame phase synchronizing circuit which outputs data synchronized with a clock and a frame pulse on an input side in synchronization with a clock or a frame pulse on an output side. The synchronization / bit phase synchronization circuit outputs a write clock synchronized with the input-side frame pulse and a read clock synchronized with the write-side frame pulse when frame pulse synchronization (frame synchronization) is instructed from outside. Timing generation means for outputting the write clock synchronized with the input clock and the read clock synchronized with the output clock when clock synchronization (bit synchronization) is instructed from the outside, and the write clock Input data is written using the Storage means for the written data is read out to output the clock as a timing reference out, characterized in that it comprises a.

Further, in the frame phase synchronization / bit phase synchronization circuit according to the present invention, in the frame phase synchronization / bit phase synchronization circuit described above, the timing generating means outputs two systems of the write clock and the read clock, The storage means is provided with two systems, and performs the bidirectional frame synchronization or the bit synchronization.

Further, in the frame phase synchronization / bit phase synchronization circuit according to the present invention, in the frame phase synchronization / bit phase synchronization circuit described above, the write clock of one system is common to the read clock of the other system. Features.

Further, a frame phase synchronization / bit phase synchronization circuit according to the present invention is characterized in that in the above frame phase synchronization / bit phase synchronization circuit, the storage means is a FIFO.

[0017]

Next, the configuration of an embodiment of the present invention will be described with reference to FIG.

A mode setting instruction 10 for instructing whether the phase synchronization between the networks A and B is performed by the frame phase synchronization or the bit phase synchronization is given externally, for example, by software control. When receiving the mode setting instruction 10, the mode switching unit 3 outputs a phase synchronization start instruction 20 to the timing generation unit 4. The timing generation unit 4 always receives clocks 30 and 31 and frame pulses 40 and 41 from each network, and receives a phase synchronization start instruction 2 from the mode switching unit 3.
When it receives 0, it takes timing for each phase synchronization method,
The clocks 50 and 51 for phase synchronization are supplied to the memory units 1 and 2. Two memory units 1 prepared for each line bidirectional,
2 is a phase synchronization clock 5 from the timing generator 4
Data 60 and 61 are written and data 62 and 63 are read in synchronization with 0 and 51.

The write clock 52 and the read clock 55 may be common, and the write clock 5
3 and the read clock 54 may be common.

Next, the operation of the embodiment of the present invention will be described with reference to FIG.

When the line to be phase-synchronized is in frame phase synchronization, for example, the mode switching unit 3 is controlled by software.
Is given a frame phase synchronization setting instruction 10. When the mode switching unit 3 receives the frame phase synchronization setting instruction 10, it instructs the timing generation unit 4 to start the frame phase synchronization start instruction 20.
Is output. When the timing generation unit 4 receives the frame phase synchronization start instruction 20 from the mode switching unit 3, the clocks 30 and 31 and the frame pulse 4 input from each network
Write clocks 52 and 53 and read clocks 54 and 55 synchronized with 0 and 41 are supplied to the memory units 1 and 2.
Two memory units 1 and 2 prepared for line bidirectional use
Write clocks 52 and 53 from the timing generator 4
, Data 60 and 61 are written in synchronization with. Further, data 62 and 63 are read from the memory units 1 and 2 in synchronization with the read clocks 54 and 55 from the timing generation unit 4. Since the memory units 1 and 2 perform data writing / reading using clocks synchronized with the frame pulses 40 and 41 from each network received from the timing generation unit 4, frame phase synchronization is realized.

When the line to be phase-synchronized is bit-phase-synchronized, the mode switching unit 3 is controlled by software control, for example.
Is given a bit phase synchronization setting instruction 10. When receiving the bit phase synchronization setting instruction 10, the mode switching unit 3 outputs a bit phase synchronization start instruction 20 to the timing generation unit 4. When the timing generator 4 receives the bit phase synchronization start instruction 20 from the mode switching unit 3, the timing generator 4 writes the write clock 5 synchronized with the clocks 30 and 31 input from each network.
2, 53 and read clocks 54, 55
Feed to 2. At this time, the frame pulses 40 and 41 are not used. Data 60 and 61) are written into the two memory units 1 and 2 prepared for line bidirectional in synchronization with the write clocks 52 and 53 from the timing generation unit 4 and synchronized with the read clocks 54 and 55. Then, the data 62 and 63 are read from the memory units 1 and 2. The timing generator 4 generates a write / read clock in synchronization with only the clocks 30 and 31 from each network. Therefore,
Writing / reading of data to / from the memory units 1 and 2 is performed in synchronization with only the clocks 30 and 31 from each network, so that bit phase synchronization is realized. At this time, the frame pulses 40 and 41 are not used, and the frame pulse 4
Unnecessary delay for synchronizing with 0 and 41 is suppressed.

[0023]

As described above, according to the present invention,
The delay amount in the phase synchronization circuit at the time of the bit phase synchronization operation can be suppressed to a necessary minimum.

When implementing bit phase synchronization,
The clock (timing) for phase synchronization is not the frame phase synchronization but the clock (timing) for bit phase synchronization
Because it switches to.

Further, according to the present invention, the circuit mounting area can be reduced.

This is because the phase synchronization circuit is shared between the frame phase synchronization and the bit phase synchronization, and only each phase synchronization clock (timing) is switched to perform the phase synchronization.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a frame phase synchronization / bit phase synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a frame phase synchronization / bit phase synchronization circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a bit phase synchronization circuit according to a conventional example.

FIG. 4 is a block diagram illustrating a configuration of a frame phase synchronization circuit according to a conventional example.

[Explanation of symbols]

 1, 2 memory unit 3 mode switching unit 4 timing generation unit 10 mode setting instruction 20 phase synchronization start instruction 30 network A clock 31 network B clock 40 network A frame pulse 41 network B frame pulse 50, 51 phase synchronization clock 60 to 63 data

Continuation of front page (56) References JP-A-62-224135 (JP, A) JP-A-2-239736 (JP, A) JP-A-3-36828 (JP, A) JP-A-61-256842 (JP) JP-A-4-20027 (JP, A) JP-A-5-83239 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 7/00 H04J 3/06

Claims (4)

(57) [Claims] 1. A frame phase synchronization / bit phase synchronization circuit for outputting data synchronized with a clock and a frame pulse on an input side in synchronization with a clock or a frame pulse on an output side. There outputs the read clock synchronized to the write clock synchronized with the input side of the frame pulse and the previous SL output side of the frame pulse when prompted, the when the external clock synchronization (bit synchronization) is instructed Timing generating means for outputting the write clock synchronized with the clock on the input side and the read clock synchronized with the clock on the output side; and writing the input data with the write clock as a timing reference and the read clock as a timing reference. Read the written data Frame phase synchronization / bit phase synchronizing circuit, characterized in that it comprises storage means, the to and output. 2. The system according to claim 1, wherein said timing generation means outputs two systems of said write clock and said read clock, and said storage means is provided with two systems to perform bidirectional frame synchronization or bit synchronization. Item 2. A frame phase synchronization / bit phase synchronization circuit according to item 1. 3. The frame phase synchronization / bit phase synchronization circuit according to claim 2, wherein a write clock of one system is common to a read clock of the other system. 4. The frame phase synchronization / bit phase synchronization circuit according to claim 1, wherein said storage means is a FIFO.