JP2974390B2 - Frame signal reproduction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention is used, for example, in a synchronous communication network terminal device,
The present invention relates to a frame signal reproducing circuit for reproducing a frame signal on a receiving side.

(Prior Art) As is well known, in a synchronous communication network terminal device, it is necessary to transmit and receive a frame, a clock, and data within or between devices. At this time, since there is a difference in propagation delay due to a difference in transmission speed, a phase difference occurs between signals on the receiving side. Therefore, in such a system, it is necessary to provide a synchronization circuit on the receiving side to maintain synchronization.
Particularly, in some systems, the transmission speed of the clock and the frame signal has a difference of the order of 10 ³ to 10 ⁶ , and a circuit for reproducing the frame signal in phase with the clock is required. Further, in order to minimize the fluctuation of the signal propagation delay difference due to the change of the system, a method of using a frame signal obtained by phase-modulating a frame signal with a reference clock has been proposed.

FIG. 4 shows the configuration of such a phase modulation type frame signal reproducing circuit, and FIG. 5 shows its operation timing diagram.

The In Figure 4, the EX-OR (exclusive OR) gates G ₁ and the clock CLK to be PFCLK and criteria phase-modulated frame signal FCLK is input, the AND gate G ₃ and its output constituting the selection circuit Is supplied to one of the input terminals. Selection circuit, a frame signal FCLK to one input terminal of the AND gate G ₂
Enter the inputs a selection signal to the other input terminal, and the inverting input of the selection signal to the other input terminal of the AND gate G _3,
Further, the outputs of the AND gates G ₂ and G ₃ are output via the OR gate G ₄ . The output of this OR gate G ₄ is D
It is supplied to the D terminal of the flip-flop FF. This flip-flop FF is synchronized with the clock CLK, and its Q output becomes the output frame signal OFCLK.

That is, the input phases of the clock CLK, the frame signal FCLK, and the frame signal PFCLK phase-modulated by the clock CLK supplied to the frame signal reproducing circuit are almost the same. When PFCLK is selected by the selection signal SEL, PFCLK
The frame signal is reproduced by taking the EX-OR of the frame signal and CLK. Even if the input phase is shifted between CLK and PFCLK, D
Spiking does not occur when the flip-flop FF strikes again with CLK. When FCLK is selected,
The frame signal is reproduced only by being latched by CLK in the D flip-flop FF, and is output as OFCLK.

In an ordinary device, FCLK is used for an input frame signal. At this time, the propagation delay difference between the signals may be changed due to the insertion / removal of the board or the change of the system. In such a case, the use of PFCLK can minimize the change in the propagation delay difference between signals.
Therefore, two types of frame signals FCLK and PFCLK are selected as selection signals.
It can be used selectively by SEL.

However, in the above-described frame signal reproducing circuit, two types of frame signals can be used in preparation for a system change or the like, but it is necessary to provide a selection signal from outside each time these frame signals are switched. . In order to enhance the compatibility of the apparatus, it is desirable that the frame signal can be reproduced for either frame signal without an external selection signal.

On the other hand, in the above circuit, the number of components and the number of input signals of the circuit are increased as compared with the case where only one type of frame signal is used. On the other hand, when this circuit is formed into a gate array or the like, it is desirable that the circuit be as simple as possible and the number of input signals be as small as possible due to limitations on the number of usable cells, the power consumption, and the number of terminals.

(Problems to be Solved by the Invention) As described above, in the frame signal reproducing circuit shown in FIG. 4, in order to use two types of frame signals, a selection signal is supplied from outside each time the frame signal is switched. There is a drawback that the number of circuit components and the number of input signals increase as compared with the case where only one type of frame signal is used.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and has a simple configuration and a simple configuration without an external selection signal.
An object of the present invention is to provide a frame signal reproducing circuit capable of reproducing a frame signal having a fixed phase relationship with a reference clock from various kinds of frame signals.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a clock and a frame signal which are almost aligned in phase or a frame signal which has been phase-modulated by the clock. A frame signal reproducing apparatus for reproducing a frame signal synchronized with a clock distribution unit for distributing and outputting the clock to a plurality of systems with a delay time of not less than a half cycle and not more than one cycle, and a clock distributed by the clock distribution unit. And a D flip-flop for supplying the frame signal or the phase-modulated frame signal supplied to an input terminal to a D input terminal and reproducing and outputting a frame signal synchronized with the clock from a Q output terminal. .

(Operation) In the frame signal reproducing circuit having the above configuration, the clock is input to the D flip-flop with a delay regardless of whether the frame signal is a normal frame signal or a phase-modulated frame signal. A frame signal synchronized with a clock can be reproduced and output without using a signal.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG. 1 and FIG.

FIG. 1 shows the configuration. In this circuit, one of a frame signal FCLK and a phase-modulated frame signal PFCLK is supplied to a D input terminal of a D flip-flop 11 in accordance with the system. The clock CLK is supplied to a clock distribution unit 12, where the clock CLK is distributed to a plurality of systems (three systems in FIG. 1) required in a subsequent circuit, one of which is supplied to a clock input terminal CK of a D flip-flop 11. You. FC
The input timings of LK, PFCLK, and CLK have the same phase as in the case of the circuit in FIG.

The operation when PFCLK is input in the above configuration will be described with reference to FIG. FIG. 2A shows a frame signal PFCLK subjected to phase modulation, and FIG.
This shows the input timing of the clock CLK when there is no clock. The delay time t _D of the clock distribution unit 12 is set to t _MIN <t _D <t _MAX . However, the duty of the clock CLK 1/2, when the period is T, and _{t MIN = T / 2 + t} S t MAX = T-t H. t _S is the setup time of the D flip-flop 11, and t _H is the hold time of the D flip-flop 11.
FIG. 2C shows the output timing of the clock CLK when t _D = t _MIN , and FIG. 2D shows the clock CLK when t _D = t _MAX.
This shows the output timing.

Now, assuming that t _D = t _{MIN, as} is apparent from FIGS. 2A and 2C, CLK is always input to the D flip-flop 11 with a delay of t _S from PFCLK. Therefore, the frame signal OFCLK shown in FIG. 2 (e) is reproduced and output from the Q terminal of the D flip-flop 11. Further, if t _D = t _{MAX, as} is apparent from FIGS. 2 (a) and 2 (d), D
CLK is always T / 2−t than PFCLK in flip-flop 11.
Input delayed by _H. For this reason, the frame signal OF shown in FIG.
CLK is reproduced and output.

Further, as shown in FIG. 3, even if provided with a _{t H <t D <T /} 2-t delay unit 13 which gives _S becomes the delay time tD on the input of the FCLK or PFCLK, second
The phase relationship is the same as in the figure, and the frame signal is reproduced.

In the case of a normal frame signal FCLK, the frame signal can be reproduced only by inputting this FCLK to the D flip-flop 11 and hitting it with the clock CLK.
This is the same as in the case of FIG.

Therefore, the frame signal reproducing circuit having the above configuration can be reproduced with a simple circuit configuration regardless of FCLK and PFCLK without an external selection signal.

Figure 3 is shows another embodiment according to the present invention, in the frame signal reproducing apparatus receives the frame signal FCLK or PFCLK the delay unit 13, the delay time T _D within a half cycle of the clock CLK The data is supplied to the D input terminal of the D flip-flop 11. Even with this configuration, since FCLK or PFCLK is reliably input to the D flip-flop 11 with a delay from the clock CLK, both FCLK and PFCLK can be reproduced without an external selection signal. .

[Effects of the Invention] As described above, according to the present invention, a frame signal having a fixed phase relationship with a reference clock can be reproduced from two types of frame signals with a simple configuration and without an external selection signal. And a frame signal reproducing circuit capable of performing the above.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a frame signal reproducing circuit according to the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment, and FIG. 3 is another embodiment according to the present invention. FIG. 4 is a block circuit diagram showing a configuration of a frame signal reproducing circuit of a phase modulation system,
FIG. 5 is a timing chart for explaining the operation of the circuit shown in FIG. 11: D flip-flop, 12: Clock distribution unit, CL
K: clock, FCLK: frame signal, PFCLK: phase modulation frame signal, OFCLK: reproduced frame signal.

Claims (2)

(57) [Claims] 1. A frame signal reproducing apparatus for reproducing a frame signal synchronized with a clock by inputting a clock and a frame signal having substantially the same phase or a frame signal which has been phase-modulated by the clock. A clock distribution unit for distributing and outputting to a plurality of systems with a delay time within one cycle as described above, and a clock distributed by the clock distribution unit is supplied to a clock input terminal, and the frame signal or the phase-modulated frame signal is supplied to a D input terminal. And a D flip-flop for reproducing and outputting a frame signal synchronized with the clock from the Q output terminal. 2. A frame signal reproducing apparatus which receives a clock and a frame signal having substantially the same phase or a frame signal which has been phase-modulated by the clock and reproduces a frame signal synchronized with the clock. A delay unit that gives the delay time of the frame signal to the frame signal; and the clock is supplied to a clock input terminal, and the frame signal delayed by the delay unit is supplied to a D input terminal;
A frame signal reproducing device comprising: a D flip-flop for reproducing and outputting a frame signal synchronized with the clock from a Q output terminal.