JPS6331244A - Loop transmitter - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a transmitter by indefinite data by providing a gate for closing the output of a memory for a constant time after a power source is energized to prevent the indefinite data generated at the time of energizing the power source from being transmitted to a loop. CONSTITUTION:The data of an elastic store memory 10 after the power source is energized is indefinite. Therefore, there is provided the gate 15 with the output of the elastic store memory 10 and the gate 15 is closed for a constant period in order to prevent the transmission of the indefinite data to the loop. Thereby, the back-end transmitter does not perform a malfunction without receiving the indefinite data. During this period, the data fed through the loop from other transmitter is written in the elastic store memory 10 and the indefinite data at the time of energizing the power source is cleared off.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a transmission device using a loop transmission method in which a plurality of transmission stations are connected in a loop and data is transmitted between each transmission station, and in particular, The present invention relates to a loop transmission device in which a backup memory that absorbs transmission delays is provided with a function of clearing undefined data that is entered when the power is turned on.

[Conventional technology]

In conventional loop transmission equipment, if the transmission path includes a transmission path that is relatively prone to jitter or phase difference, such as a few microphone lines, the phase difference between the transmitted and received transmission information becomes extremely large and cannot be absorbed by the buffer memory. I can't bear it anymore. In order to eliminate such drawbacks, as described in Japanese Unexamined Patent Application Publication No. 161949/1989, data loops can be prevented even if there is a large phase difference between transmitted transmission information or a frequency deviation that occurs in a loop-type transmission line. In order to absorb the delay, a memory is provided to absorb the phase difference between the received transmission information and the transmitted transmission information, and the received transmission information is determined based on the difference between the writing position of the received transmission information and the position where the transmitted transmission information is written in this buffer memory. Then, a means is provided to determine the phase difference between each transmission information to be transmitted, and expand or contract the frame length of the transmission information to be transmitted depending on the magnitude of this phase difference. When the frequency deviation reaches an amount equivalent to the deviation, the frequency deviation should be brought close to zero (by adjusting the slots of the non-information part of the transmitted information and varying the frame length, a means is used to absorb large phase differences and frequency deviations). However, no consideration was given to means to prevent the data in the memory from becoming undefined due to the undefined data generated when the power is turned on, which would cause malfunctions in the subsequent transmission equipment.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology takes into consideration a means for preventing the data in the memory for absorbing the transmission delay of the loop from becoming unstable when the power is turned on, and from sending this data to the loop. There was a problem that there was a risk of malfunction.

An object of the present invention is to provide a highly reliable loop transmission system that prevents undefined data from being sent to the loop when power is turned on.

[Means for solving problems]

The above purpose is to prohibit the output of the elastic memory from sending data onto the loop for a certain period after the power is turned off, in order to absorb frame phase shifts due to loop delay, and to prevent data from being sent from the transmission HIM on the loop during this period. This is accomplished by providing a gate that writes the received data into the elastic memory and wipes out undefined data.

[Effect]

After the power is turned on, the data in the elastic memory is undefined. For this reason, a gate is set at the output of the elastic memory, and the gate is closed for a certain period of time to prevent undefined data from being sent to the loop.

As a result, the subsequent transmission device will not receive undefined data and will not malfunction. Also, data sent from other transmission devices via a loop during this period can be loaded into the elastic memory, thereby making it possible to wipe out undefined data when the power is turned on.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

FIG. 1 is a block diagram of a loop transmission system to which the present invention is applied.

In the figure, this system includes multiple loop transmission devices [1 to
4 are connected in a loop through a transmission path 9, and each loop transmission device 1-4 is comprised of one control station 1 and a plurality of slave stations 2-4. 5 to 8 are terminal interfaces, and 21 to 24 are terminal devices.

The control station 1 is the only one of the loop transmission devices that generates a frame pattern in order to regenerate timing so that data can be received.

The receiving circuit of each transmission HWjt1 to HWjt4 (including the control station) is as follows:
It has the function of determining the receiving clock by detecting the frame pattern, knowing the data delimiter, and allowing data to be sent and received.

FIG. 2 is a block diagram showing the configuration of the loop transmission device. This loop transmission itt includes an elastic store memo 1JID, a terminal interface 11, a timing circuit 12, a frame pattern generation circuit 13, and a selector 14.
, a gate 15, an oscillation circuit 16, a fast-in-fast-out (FIFO) memory 17, a selector 18, a reception circuit 19, a transmission buffer 2o, a reception buffer 25 constituting the reception circuit 19, a timing recovery circuit 26, and a data terminal 27. It is configured.

The loop transmission device of the present invention is configured as described above.4.

As shown in FIG. 5, the received data RD input from the loop-shaped transmission line 9 is sent to the terminal interface 11 via the receiving circuit 19. The receiving circuit 19 reproduces the receiving a-crack RXC from the received data RD, detects a frame pattern, and generates a frame reference signal FTIM serving as a frame reference.

The terminal interface 11 performs data transfer or throughput, and sends data to an elastic store memory (hereinafter referred to as ESM) 10 as transmission data TXD.
and the selector 18.

The selector 18 is a selector that selects the data route between the control station and the slave station. In the case of the slave station, it selects the transmission data TXD from the terminal interface 11, and in the case of the control station, it selects the transmission data TXD from the terminal interface 11, and in the case of the control station, it selects the data route TXD from the terminal interface 11. A gate 15 for prohibiting the output of the ESM10% ESM10 that adjusts the phase of the frame, a frame pattern generation circuit 13 that generates a frame pattern as a frame reference, a timing circuit 12 that generates timing signals to each part, and a frame pattern FL. A selector 14 that selects Afp and data from ESAflo based on timing, an oscillation circuit 16 that generates a system reference clock, and a fast-in-fast-out C and below FI that performs bit phase alignment of data.
The data synchronized with the free-running route a (abbreviated as FO) is selected by the signal MDDE and sent to the loop data transmission buffer 20.

Next, frame phase alignment at the control station 1 will be explained with reference to FIG.

Figure 3 shows the frame sending and receiving circuit 19 in the control station 1.
This shows the frame reception timing.

In the figure, FLMS is an activation signal for the frame pattern generation circuit 13 to generate a frame pattern.
EL is the selector 140 control signal for sending the frame pattern to the loop, SD is the transmission data sent to the loop, RD is the reception data that has gone around the loop and returned to the control station 1 with a delay of tDLY from the transmission data SD, FTIM detects a frame pattern included in the received data 11D and indicates a data reception standard that is used as a standard when receiving data.

Frame phasing is performed by manipulating write and read addresses to ESMlo.

That is, when sending out data RD to ESMlo, the write address is preset using the frame pattern detection standard signal FTIM, the data is written, the address is updated, and this process is repeated. When reading, a read address at which the sending data RD can be reproduced is preset using the frame pattern generation starting signal FLM5K, and reading is repeated.

As described above, the data delayed in the loop 9 is phase-aligned with the free-running timing of the control station 1, and each receiving circuit of the transmission device can receive data without disrupting synchronization.

Now, if we consider the case where there is no gate 15 to inhibit the output of ESAllo, the data of ESMlo is undefined when the power is turned on, so by chance there is data with the same bit pattern string as the complaint pattern. .

If this existing data is sent to the loop, the receiving circuit of the subsequent transmission device will erroneously detect it as a frame pattern, and the frames will be out of synchronization, making correct reception impossible.

In order to solve the above problems, the present invention provides I! :S J/1
The gate 15 is set to the output of 0, and after the power is turned on, the gate 15 is set constant during "υ" and the filling gate 15 is connected to the power turned on.
The B signal is turned off and closed to prevent the output of ESAflo from being sent to the loop 9 via the selector 14.

As a result, the received data RD sent from the transmission device fi1'4 at the front stage of the control station 1 also contains undefined data (and by passing this data to ESMlo, it is possible to eliminate the need to provide a dedicated clearing circuit (for ESMlo). Undefined data can be cleared.

As described above, each transmission device on the loop can send and receive data without malfunctioning.

〔Effect of the invention〕

According to the present invention, it is possible to prevent malfunctions of the transmission equipment due to insufficient ESH data that occurs when the power is turned on, thereby constructing a highly reliable loop transmission system.

I can do it.

[Brief explanation of the drawing]

Each of the figures shows an embodiment of the present invention; Fig. 1 is a block diagram of a loop transmission system, Fig. 2 is a block diagram of a transmission device, and Fig. 3 is a timing diagram when performing frame phase matching. It is. 1...Control station 2*394...Slave station5.
6, 7, 8, 11...Data terminal interface 9.
...Transmission line 10...Elastic store memory 12...Timing circuit 13...Frame pattern generation circuit 11.18...Selector 15...Kate 16
...Excavation circuit 17...F IFO memory 19...Reception circuit 20-Transmission buffer 21
, 22 , 25 , 24 , 27 . . . Data terminal 25 . . . Reception buffer 26 . . . Timing basic circuit

Claims (1)

[Claims] 1. Close the output of the elastic store memory for a certain period of time after the power is turned on to prevent undefined data generated when the power is turned on from being sent to the loop, which is used to absorb frame phase shifts due to loop delays. A loop transmission device characterized by having a gate and a function to clear undefined data in memory.