JPH11122230A - Synchronizing method for data communication system and data communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need of adding a synchronizing signal to all response signals and to improve the efficiency of communication between transmission/ reception by permitting a transmission side to transmit transmission data in accordance with an inner reference signal, and permitting a reception side to generate a clock based on a transmission signal and to send the response signal to the transmission side in synchronizing with the clock. SOLUTION: A PLL circuit 8 phase-synchronizes the output clock with a reception signal. A shaping circuit 11 samples the reception signal at a sample clock and holds the value. When a SYNC circuit 10 receives the prescribed quantity of received bit strings matched with a synchronizing signal pattern, the PLL circuit 8 is locked and the output of the matching circuit 11 is written in a memory 9 in synchronizing with a bit clock Bitclk'. At the time of returning the response signal after reception terminates, the response signal is transmitted in synchronizing with the bit clock Bitclk'. On the other hand, the transmission side samples the response signal in accordance with the reception timing of the response signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication system which transmits a transmission signal having a synchronization signal from a transmission side to a reception side, and transmits a response signal having no synchronization signal from the reception side to the transmission side. It is.

[0002]

2. Description of the Related Art In the prior art, when a response from the receiving side is required in simplex, a synchronization signal is also added to a response signal. The reason for adding the synchronization signal to the response signal is as follows. Since the response signal is generated based on the internal oscillator of the receiving side, if the synchronization signal is not added to the response signal, the transmitting side cannot fetch the response signal in synchronization with the clock of the receiving side. In order to prevent such a situation from occurring, a synchronization signal is also added to the response signal.

FIG. 1A is a diagram for explaining a conventional transmission signal and reception signal. The transmission signal and the reception signal are bit strings. The transmission signal includes a synchronization signal (SYNC), a header, data, and the like. The synchronization signal is, for example, a repetition of 1010 and has a size of 128 bits or 256 bits. The header has a transmission source name, a destination name, a data start code, and the like. The response signal is a synchronization signal,
It consists of a header, status, etc. The status is, for example, a positive response or a negative response.

The transmitting side sends a transmitting signal having a synchronization signal at the head to the receiving side. Upon receiving the transmission signal, the receiving side sends a response signal having a synchronization signal at the top to the transmitting side. If the transmission signal has been received correctly and is ready to receive the next transmission signal, the status of the response signal is acknowledged.

[0005]

However, in the above-mentioned prior art, since a synchronizing signal is added to all response signals, communication between the transmitting side and the receiving side cannot be performed efficiently. there were. The present invention has been made in view of this point, and eliminates the need to add a synchronization signal to all response signals, and can efficiently perform communication between a transmission side and a reception side. And a data communication system.

[0006]

According to a first aspect of the present invention, there is provided a synchronization method for a data communication system, wherein a transmitting side sends a transmission signal to a receiving side, and the receiving side sends a response signal to the transmitting side when receiving the transmitting signal. The transmitting side transmits a next transmission signal to the receiving side on condition that the response signal is received, wherein the transmitting side transmits the transmission data according to the internal reference signal, and transmits the response signal. Holding the reception timing, sampling a response signal according to the reception timing,
The sample result is written into the memory, and the receiving side generates a clock based on the transmission signal transmitted from the transmitting device,
A response signal is sent to the transmission side in synchronization with the clock.

A data communication system according to a second aspect of the present invention
The transmission signal is read from the memory and sent to the receiving device, and the response signal sent from the receiving device is stored in the memory.The transmission signal sent from the transmitting device is stored in the memory and read from the memory. A data communication system comprising a receiving device for sending the response signal to the transmitting device, wherein the transmitting device is accessed in synchronization with a reference clock generator and a bit clock output from the reference clock generator. A memory, a PLL circuit for synchronizing an output clock with a response signal, a synchronization detection circuit for detecting a synchronization signal existing at the head of the response signal, and a response signal based on a sample clock generated from the output clock of the PLL circuit. And a shaping means for holding a sampled value, and when the synchronization detection circuit detects a synchronization signal,
The LL circuit is locked, the output data of the shaping means is written to the memory, and the receiving apparatus comprises: a PLL circuit for synchronizing an output clock with a transmission signal in phase; a memory accessed in synchronization with the output clock of the PLL circuit; A synchronization detection circuit for detecting a synchronization signal existing at the head of the signal;
Sample the transmit signal based on the output clock of the circuit,
And a shaping means for holding the sample value, and when the synchronization detecting circuit detects the synchronizing signal, the PLL circuit is locked, the output data of the shaping means is written into the memory, and the synchronizing signal is provided at the beginning of the first response signal. Is present, and no synchronous signal is present in other response signals.

[0008]

FIG. 1 (b) is a diagram showing an outline of the present invention. The transmission signal transmitted from the transmission side to the reception side is composed of a synchronization signal (SYNC), a header, data, and the like. The receiving side receives the transmission signal and returns a response signal to the transmitting side. The first (first) response signal has a synchronization signal, a header, and a status, but the response signals after the first response signal do not have a synchronization signal and are composed of a header, a status, and the like.

The transmitting side has a PLL circuit. Since the synchronization signal is added to the first response signal, the transmitting side uses the synchronization signal to synchronize its own clock with the response signal, and locks the PLL circuit when a certain amount of the synchronization signal is received. That is, the frequency and phase of the clock output from the PLL circuit are fixed. Although no synchronization signal is added to the second and subsequent response signals, the transmitting side uses the locked clock to capture the header and status of the response signal.

FIG. 2 is a diagram showing an example of a data transmitting circuit and a response signal receiving circuit on the transmitting side. In the figure, 1 is an oscillator, 2 is a timing generator, 3 is a memory,
4 is a PLL circuit, 5 is a SYNC detection circuit, 6 is a shaping circuit, and 7 is a communication control unit of the host CPU.

The clock output from the oscillator 1 is input to the timing generator 2. The timing generator 2 is a frequency divider. The output of the timing generator 2 is called a bit clock bitclk. The memory 3 is read / write accessed in synchronization with the bit clock.

The transmission data is stored in the memory 3 in advance, and is read from the memory 3 in synchronization with the bit clock. The read transmission data is modulated by a modulator (not shown) and sent to the receiving side via a wired or wireless communication path.

The received signal (response signal from the receiving side) is P
The signals are input to the LL circuit 4, the SYNC detection circuit 5, and the shaping circuit 6. The PLL circuit 4 synchronizes the output clock with the received signal in phase. The received signal is a bit string of 1,0.
The frequency of the output clock is equal to the bit rate of the received signal, and the rising point of the output clock coincides with the conversion point of the bit data of the received signal. SYNC detection circuit 5
Represents a received bit string and a synchronization signal pattern (for example, 101
0) and instructs the PLL circuit 4 to lock when a predetermined amount of the received bit string that matches the synchronization signal pattern is received. The lock of the PLL circuit 4 is released when the SYNC is added when the next response is received.

The sample clock is created based on the output clock of the PLL circuit 4. Assuming that the period of the output clock of the PLL circuit 4 is T, the sample clock is generated when 0.5T has elapsed after the output clock rises. The sample clock is input to the shaping circuit 6. The shaping circuit 6 is, for example, a D flip-flop, which samples a received signal with a sample clock,
Keep that value. The output of the shaping circuit 6 is written to the memory 3 when the response signal is received. The shaping circuit 6 has a function of timing adjustment. The communication control unit 7 of the host CPU
Instructs data transmission and response reception, and
, And writing of transmission data to the memory 3.

The line from the timing generator 2 to the PLL circuit 4 also indicates the bit clock bitclk. The difference between the output (sample clock) of the PLL circuit 4 and the bit clock bitclk when the first response signal is received (this difference is 2 (τ1 + τ2 + τ3) as described later)
, The next response will be the bit clock bitc
By simply shifting lk by 2 (τ1 + τ2 + τ3), a sample clock is generated, and the PLL circuit 4 does not need to operate at all. This line is unnecessary if the PLL circuit 4 is operated while being locked.

FIG. 3 is a diagram showing an example of a data receiving circuit and a response signal transmitting circuit on the receiving side. In the figure, 8 is a PLL circuit, 9 is a memory, 10 is a SYNC detection circuit, 1
Reference numeral 1 denotes a shaping circuit, and 12 denotes a communication control unit of the host CPU.

The response signal is stored in the memory 9 in advance, and is read from the memory 9 in synchronization with the bit clock bitclk '. The read response signal is modulated by a modulator (not shown) and sent to the transmission side via a wired or wireless communication path.

The reception signal (transmission signal from the transmission side) is P
LL circuit 8, SYNC detection circuit 10, and shaping circuit 11
Is input to The PLL circuit 8 synchronizes the output clock with the received signal in phase. The SYNC detection circuit 10 is the same as the SYNC detection circuit 5 of FIG. 2, and instructs the PLL circuit 8 to lock when a predetermined amount of a received bit string that matches the synchronization signal pattern is received. PLL
The lock of the circuit 8 is released when the transmission of the response signal ends.

The sample clock is input to the shaping circuit 11. Sample clock and bit clock bitc
lk 'is the same. The shaping circuit 11 samples the received signal with a sample clock and holds the value. The output of the shaping circuit 10 outputs a bit
The data is written to the memory 8 in synchronization with the clock bitclk '.
The shaping circuit 11 has a function of adjusting timing. The communication control unit 12 of the host CPU issues a data reception instruction and a response transmission instruction, and reads received data from the memory 9 and writes response data to the memory 9.

The operation of the transmitting side and the receiving side will be described with reference to FIGS. Transmission data consists of bits
Sent in synchronization with clock bitclk. The receiving side generates a sample clock based on the received signal, samples the received signal using the sample clock, and writes the sampled result to the memory 9. When the response signal is returned after the reception is completed, the response signal is transmitted in synchronization with the bit clock bitclk '. As a result, the transmitting side can transmit the transmission signal and receive the response signal at the same timing every time. Therefore, once the timing of the response signal is known, the response signal does not require a synchronization signal. However, in order to know the timing of the response signal, the first response signal requires a synchronization signal.

FIG. 4 is a diagram for explaining the time from reading of the memory on the transmitting side to writing on the memory of the receiving side. A memory and a modulator exist on the transmission side, and a demodulator and a memory exist on the reception side. On the transmitting side, data to be transmitted is read from the memory in synchronization with the bit clock bitclk, and the read data is modulated by the modulator. The modulated signal is sent to the receiving side via a wired or wireless communication path. On the receiving side, the modulated signal is demodulated by the demodulator into the original data, and the data obtained as a result of the demodulation is written to the memory in synchronization with the bit clock bitclk '.

Assuming that the time required for modulation is τ ₁ , the time required for propagation through the communication path is τ ₂ , and the time required for demodulation is τ ₃ , the data read from the memory on the transmission side is stored in the memory on the reception side. The time to reach is τ ₁ + τ ₂ + τ ₃ . The transmission side bit clock bitclk 'and the reception side bit clock bitclk' have the same shape, but the reception side bit clock bitclk 'is the transmission side bit clock.
It is delayed by τ ₁ + τ ₂ + τ ₃ hours from bitclk.

After receiving the transmission signal, the receiving side sends a response signal to the transmitting side. The time from reception of a transmission signal to transmission of a response signal is nT (T is a bit clock bitc
lk 'period). The time required for the response signal read from the memory on the receiving side to reach the memory on the transmitting side is τ ₁ + τ ₂ + τ ₃ . Therefore, the time from when the transmission data is read out from the transmission side memory until the response data corresponding to the transmission data reaches the transmission side memory is 2 (τ ₁ + τ ₂ + τ ₃ ) + nT.

The clock output from the PLL circuit on the transmitting side has the same form as the bit clock bitclk 'on the receiving side, but the former is delayed by τ ₁ + τ ₂ + τ ₃ hours from the latter. Therefore, the transmission side bit clock bitclk
And the output clock of the PLL circuit on the transmitting side is 2
The remainder is obtained when (τ ₁ + τ ₂ + τ ₃ ) is divided by the period T.

FIG. 5 is a diagram showing operation timings on the transmission side and the reception side. Transmission data is bit clock bitc
read from the memory on the transmission side in synchronization with lk, and τ ₁ + τ
₂ + τ ₃ hours later, the data reaches the entrance of the memory on the receiving side and is written into the memory on the receiving side in synchronization with the bit clock bitclk '. The response data is read from the memory on the receiving side in synchronization with the bit clock bitclk ', and τ ₁ + τ ₂ +
After τ ₃ hours, it reaches the entrance of the memory on the transmission side, is shaped, and is written into the memory on the transmission side in synchronization with the bit clock bitclk.

On the receiving side, the synchronization signal SY is included in the first response signal.
NC is added, and SYNC is not added to other response signals. There are a first method and a second method as described below as a method of distinguishing the first or the second.

The first method is a method of instructing whether or not to add SYNC to a response signal by using one bit in a header in transmission data. The receiving side determines the bit (during data reception) and generates a response signal according to the determination result. In this case, whether or not the receiving side is the first depends on the transmitting side. On the transmitting side, if there is no data for a long time (for example, a period corresponding to 10 frames),
At the next communication, the transmission data having the SYNC addition instruction is transmitted to the receiving side. Or, check the communication error situation and use SYNC
It may be determined according to the use environment, such as whether or not there is an additional instruction.

The second method is that if there is no reception signal for a certain period of time (for example, a fraction of one frame) on the receiving side, the next received data is regarded as the first and the response signal is This is a method of adding SYNC. In the second method, the presence / absence of SYNC needs to match between the transmitting side and the receiving side. If the transmitting side cannot send the next data within a fixed time after receiving the response, it is assumed that the timing relationship with the receiving side has been broken and the next response has SYNC. However, even if the next data can be transmitted within a certain time, the receiving side may determine that the time has been exceeded. In such a case, the transmitting side uses SYNC
Is unnecessary, but SYNC is added on the receiving side. If the setting of the fixed time on the receiving side is increased, the transmitting side requires SYNC, but the receiving side does not have SYNC.

In order to avoid such a phenomenon, if the transmitting side cannot transmit within a certain time (TA period), the transmitting side waits for a while (TB) and then performs the next transmission. The receiving side may be set at an intermediate point between TA and TB.
FIG. 6 is a diagram for explaining the transmission timing of the transmission data and the response signal with SYNC when the second method is adopted. t0 indicates the time at which the transmission side has completed receiving the response signal. The difference between t1 and t0 is TA, and t2 and t0
Is TB, and t3−t0 is, for example, (TA + TB)
/ 2.

If the transmission side cannot transmit the next transmission data within the TA time after the completion of the reception of the response signal, the transmission side transmits the next data after the TB time. That is, the times t1 and t
Between the two, the transmitting side does not start transmitting the transmission data,
Transmission of transmission data is performed before time t1 or after time t2. The receiving side does not add SYNC to the response signal when receiving the transmission data before time t3, and adds SYNC to the next response signal when receiving the transmission data after time t3.

[0031]

As is apparent from the above description, according to the present invention, it is not necessary to add a synchronization signal to all response signals, so that the communication between the transmitting side and the receiving side can be performed efficiently. Become.

[Brief description of the drawings]

FIG. 1 is a diagram showing an outline of the present invention.

FIG. 2 is a diagram illustrating an example of a data transmission circuit and a response signal reception circuit on the transmission side.

FIG. 3 is a diagram illustrating an example of a data receiving circuit and a response signal transmitting circuit on the receiving side.

FIG. 4 is a diagram showing a time from reading of a memory on a transmission side to writing on a memory of a reception side.

FIG. 5 is a diagram showing operation timings on a transmission side and a reception side.

FIG. 6 is a diagram for explaining transmission timing of transmission data and a response signal with SYNC.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Oscillator 2 Timing generator 3 Memory 4 PLL circuit 5 SYNC detection circuit 6 Shaping circuit 7 Communication control unit of host CPU 8 PLL circuit 9 Memory 10 SYNC detection circuit 11 Shaping circuit 12 Communication control unit of host CPU

Claims (2)

[Claims] 1. A transmitting side sends a transmission signal to a receiving side, and the receiving side sends a response signal to the transmitting side when receiving the transmission signal, and the transmitting side sends the next transmission signal on condition that the response signal is received. A transmission method for transmitting transmission data according to an internal reference signal, holding reception timing of a response signal, sampling a response signal according to the reception timing, The result is written in a memory, and the receiving side generates a clock based on the transmission signal transmitted from the transmitting device, and transmits a response signal to the transmitting side in synchronization with the clock. Synchronization method. 2. A transmitting device for reading out a transmission signal from a memory and sending it to a receiving device, and storing a response signal sent from the receiving device in a memory, and storing a transmitting signal sent from the transmitting device in a memory. ,
A data communication system comprising: a receiving device that sends a response signal read from a memory to a transmitting device, wherein the transmitting device synchronizes with a reference clock generator and a bit clock output from the reference clock generator. Memory, a PLL circuit for synchronizing an output clock with a response signal, a synchronization detection circuit for detecting a synchronization signal existing at the head of the response signal, and a sample clock generated from the output clock of the PLL circuit. And a shaping means for sampling the response signal based on the sampling signal and holding the sampled value. When the synchronization detection circuit detects the synchronization signal, the PLL circuit is locked, and the output data of the shaping means is written to the memory. Is a PLL circuit that synchronizes the output clock phase with the transmission signal, and is accessed in synchronization with the output clock of the PLL circuit Memory, a synchronization detection circuit for detecting a synchronization signal existing at the head of the transmission signal, and a shaping means for sampling the transmission signal based on the output clock of the PLL circuit and holding a sample value, and detecting the synchronization. When the circuit detects the synchronizing signal, the PLL circuit is locked, the output data of the shaping means is written into the memory, and the synchronizing signal exists at the head of the first response signal, and the synchronizing signal exists in the other response signals. A data communication system characterized by not performing.