JPS5950645A - Independent synchronizing system - Google Patents

Abstract

PURPOSE:To synchronize with a clock, by comparing a phase between an input data train and a clock signal, and delaying the input data train when the difference is large. CONSTITUTION:The phase difference between the input data train Di1 and the clock signal CK is detected at a phase selecting circuit PSEL. When the phase difference between the input data train Di1 and the clock signal CK is smaller than a half the period of the clock signal, the input data train Di1 is fed to a waveform shaping circuit SHP by controlling a switch SW. When the phase difference of the both is larger than a half the period of the clock signal, the input data train Di1 is fed to the waveform shaping circuit SHP via a delay circuit DLY. The delay circuit DLY delays an input signal by a half the period of the clock signal. The data reproduction and shaping are attained without using an extracted clock from the input data.

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to a data reproducing and shaping device, and by performing special shaping, it is possible to suppress jitter in bit units and reduce the circuit scale by eliminating a clock extraction section. This paper relates to an independent synchronization method that enables

PRIOR ART AND PROBLEMS When looking at an example of a conventional synchronization system for a communication system consisting of multiple communication devices, as shown in Figure 1, a clock supply line Mo is provided separately for the data line LO (!) to synchronize the entire system. As shown in Figure 2, a clock extraction circuit using a tank circuit T performs multi-point sampling in the input data resampling circuit SP for waveform reproduction/shaping and clock extraction, as shown in Figure 4. Another method is to resynchronize a signal reproduced and shaped using a clock extracted from input data to a unique clock by passing it through an elastic buffer Buf.

Note that R is a receiver, S is a transmitter, P is a control circuit, and E(B.

BO2+E11 rElffi yE21 +”22p
Since E31 + E32 does not require a repeater, such as a 0x extraction circuit, and the circuit configuration is simplified, jitter accumulation at the first pitch does not occur in the transmission data DToo-DT02 as shown in FIG. On the other hand, the clock supply aMO must be installed separately, and the entire system lacks flexibility.

In the method shown in FIG. 2, the clock supply line MO is not required, but a timing extraction circuit T is required, and since the extracted clock is affected by the jitter of the received data, (
b) As shown in the figure, jitter accumulation occurs in the transmission data DT, 0 to DTl.

The method shown in Figure 3 samples the received data at multiple points, so
A clock oscillator 0801 with several times the data signal rate is required. In this method, the larger the number of samples, the smaller the jitter accumulation in the transmission data DT 20 to D's' 22, but for this purpose a high frequency clock oscillator must be used.

In the system shown in FIG. 4, the transmitting system of the transmitting device and the receiving system are synchronized by link-by-link, and jitter is absorbed by an elastic buffer Buf within the device. For this reason, jitter accumulation in the transmission data DT30 to DT32 can be prevented, but in addition to the clock extraction circuit T, a clock oscillator, elastic buffer Buf, and its control unit are required, which has the disadvantage of complicating and bulking up the device configuration. .

OBJECT OF THE INVENTION The purpose of the present invention is to solve the above-mentioned drawbacks of the prior art. Only pattern information is obtained from input data, while clock information is obtained from a unique oscillator. The object of the present invention is to provide an independent synchronization method that can suppress jitter and eliminate a clock extraction section.

Structure of the Invention The above object is to provide a delay circuit that delays an input data string by half the clock cycle of the device, and to compare the phase of the rising edge of the input data string with the clock, and to detect the difference between the input data and the clock. If the phase difference is smaller than the phase difference between the clock and the output of the delay circuit, the input data is input to the shaping circuit, and if the opposite is the case, the output of the delay circuit is input to the shaping circuit. A phase selection circuit for controlling the switching 3 and an inhibition circuit for inhibiting switching control of a part of the switching 3 for only one frame of the input data string are provided, and the shaping circuit performs shaping in synchronization with the clock. This is achieved by an independent synchronization method.

Examples of the invention The present invention will be described in detail below based on examples.

FIG. 5 shows an example of a circuit configuration for implementing the present invention.

Further, FIG. 6 shows an outline of the operation of this circuit.

In the figure, SW is a changeover switch, PSEL is a phase selection circuit, FONT is a valid data counter, O20 is a clock oscillator, DLY is a delay circuit, and SHP is a shaping circuit. To explain the operation, the input data from the signal line Dil is a bit string with i invalid data periods as indicated as DTi in FIG.
It has almost the same frequency component as the clock CK generated by the clock CK. For such input data ζ, the phase selection circuit P8E
At L, the rising edge of data during the invalid period is detected, and the phase of this rising edge and the clock CK is compared. As a result, among the data DTs delayed by the duck phase from the 4-bit data, the data whose phase difference is closer to the IA phase with respect to the clock CK is selected by switching the changeover switch SW using the data select signal DSEL.

The shaping circuit SHP samples the selected data DT and S in synchronization with the clock CK, and sends them as output data DTo to the next stage repeater. On the other hand, valid data counter FC
In NT, the data length of the delayed data DTS is counted,
The phase selection is locked during counting, and is controlled by control signal CTL1 to release the lock after counting out, that is, during an invalid data period. Then, as described above, the switch SW is switched during the invalid data period. Note that the invalid data period also contains data of '1' and '0' alternately,
It has no meaning as data.

The specific structure of the phase selection circuit PSEL will be explained with reference to FIGS. 7 and 8.

In the figure ζ, FFI to FF3 are D flip-flops, F
F4 is the clock CK generated by the JK flip-flop, ANDI, AND2 clock oscillator OSC (Figure 5)
A clock 40K having a frequency four times that of 2 is input to the clock terminals CL of the D flip-flops FFI and FF2.

Therefore, input data DinO is delayed by 1 bit and D-4n
Then, Dinl is further delayed by 1 bit and output as Dil from the Q of the D flip-flop FF2.

On the other hand, Djnl and the Q output Di of D flip-flop FF2
l is input to the AND gate AND2, and the AND gate AN
The D2 output EDG is input to the J and J terminals of the JK flip-flop FF4. This Antogame-1-A-ND2 detects the rising edge of data.

Also, the AND gate AND1 has a frame counter F'-C.
Signal CTL which is the inversion of the control output from NT (Figure 5)
1 and clock CK are input, and clock JKCL is output only during the invalid data period and input to the clock terminal of JK flip-flop FF4.

Therefore, the clock CK is output from the JK flip-flop FF4 near the rising edge of the invalid data (1/l of the data length).
If it corresponds, the data select signal DSEL is output, the changeover switch SW is operated, and, for example, the output of the delay circuit is input to the D flip-flop FF3 serving as a shaping circuit.

Effects of the Invention According to the present invention, data can be reproduced and shaped without using an extraction clock from input data, so jitter in bit units can be suppressed, and the circuit can be simplified by eliminating the clock extraction circuit. can be measured.

[Brief explanation of the drawing]

FIGS. 1 to 4 are diagrams illustrating the conventional method and image forming circuits. (α) Sense Cb) Figure 1 < b) ・Figure 2 C (2) Cb) Figure 3 (Bn erase Figure 4

Claims (1)

[Claims] A delay circuit delays an input data string by half the clock cycle of the device, and a phase comparison between the rising edge of the input data string and the clock is performed, and the phase difference between the input data and the clock is determined by the phase difference between the clock and the clock. a phase selection circuit that controls a switching unit so that when the phase difference is smaller than the phase difference between the outputs of the delay circuits, the input data is input to the shaping circuit, and when the opposite is the case, the output of the delay circuit is input to the shaping circuit; An independent synchronization system characterized in that an inhibition circuit is provided for inhibiting switching control of the switching section for only one frame of an input data string, and the shaping circuit performs shaping in synchronization with the clock.