JPH0718194Y2 - Data transceiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is used in a data transmitting / receiving apparatus for transmitting / receiving a data code string.

The present invention relates to a data transmitter / receiver capable of transmitting / receiving a data code string even when a reception timing signal input from the outside is interrupted.

〔Overview〕

The present invention temporarily writes a data code string to a buffer memory circuit at the timing of a reception timing signal, and reads the written data code string at the timing of a transmission timing signal oscillated in synchronization with this reception timing signal. In the data transmitting / receiving device for transmitting, when the reception timing signal is disconnected, the oscillation circuit of the transmission timing signal is converted to free-running, and the received data code string is transmitted without passing through the buffer memory circuit. It is intended to prevent interruption of transmission of the code string.

[Conventional technology]

Conventionally, this type of data transmitter / receiver uses a reception timing signal 16 input to a reception end R2 as shown in FIG.
The data code string 15 input to the buffer memory circuit 11 is written into the buffer memory circuit 11, the reception timing signal 16 is input into the phase circuit oscillation circuit 14, and the transmission timing signal 17 is synchronously oscillated. With this transmission timing signal 17, the buffer memory circuit 11
The data code string written in was read out as indicated by reference numeral 18 and transmitted from the transmission end S1.

[Problems to be solved by the invention]

However, in the above-described conventional data transmitting / receiving apparatus, when the reception timing signal input from the outside is cut off, the data code string received thereafter cannot be transmitted from this apparatus. There is also a drawback that the contents already written in the buffer memory circuit are repeatedly transmitted.

Further, in the conventional example, when used in the system shown in FIG. 3, for example, the following inconvenience occurs.

FIG. 3 shows a system in which the data transmission / reception device 33 is used by switching the other data transmission / reception device 31 and the data terminal device 32 with the signal switch 34.

Generally, when a data transmitter / receiver receives a data code string from another data transmitter / receiver, it is necessary to receive a timing signal from the other data transmitter / receiver. Also, the data terminal device does not generate a timing signal. Therefore, when the signal switch 34 selects the data transmitter / receiver 31 in FIG.
Since 16 is input, the data code string 15 can be received. However, when the signal switch 34 selects the data terminal device 32, since the timing signal 16 is not input, the data transmitting / receiving device 33 cannot write the data code string 15 even if it is input.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above drawbacks and to provide a data transmitter / receiver capable of receiving a data code string and transmitting it to another even when a signal interruption occurs.

[Means for solving problems]

The present invention generates a transmission timing signal in synchronization with a buffer memory circuit in which a reception data string is written in synchronization with an externally input reception timing signal and is read out in synchronization with a transmission timing signal. A phase-locked oscillator circuit for supplying to the buffer memory, and a signal-loss detection circuit for detecting a disconnection of the reception timing signal.The phase-locked oscillator circuit is self-running by the detection output of the signal-loss detection circuit. A data transmission / reception device configured as an oscillation circuit includes a signal selection circuit that selects and outputs a received data string as transmission data instead of the read output from the buffer memory circuit by the detection output of the signal disconnection detection circuit. It is characterized by

[Action]

When the reception timing signal becomes a signal disconnection, the signal disconnection detection circuit detects this and causes the phase-locked oscillator circuit to self-oscillate at a frequency very close to the correct transmission timing signal, and the signal selection circuit receives it from the receiving end. The data code string is switched so as to be directly transmitted without being written in the buffer memory circuit.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. First
FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, a receiving end R1 for receiving the data code string 15,
The receiving end R2 for receiving the reception timing signal 16 coming from the outside, and the data code string 15 by this reception timing signal 16
, The phase-locked oscillator circuit 14 that oscillates the transmission timing signal 17 in synchronization with the reception timing signal 16 and the transmission timing signal 17 and the data read from the buffer memory circuit 11 at this timing signal. Transmitters S1 and S2 for transmitting the code string 19 and respectively
Is equipped with. The transmitting end S3 sends a transmission timing signal to, for example, a data terminal device (not shown).

Here, the feature of the present invention is that a signal break detection circuit 13 for detecting a signal break of the reception timing signal 16 and a data code string 15 received at the receiving end R1 by the output of the signal break detection circuit 13 or A signal selection circuit 14 for selecting which of the data code strings 19 read from the buffer memory circuit 11 is provided, and the phase-locked oscillation circuit 14 is a free-running command sent when the signal disconnection detection circuit 13 detects a signal disconnection. It is to self-oscillate by the signal 20. The oscillation frequency in this case is set to the standard transmission timing frequency.

Further, when the signal is disconnected, the signal selection circuit 12 sends out the data code string 15 as received by the switching command signal 21 sent out by the signal disconnection detection circuit 13 to the transmitting end S1.

When the reception timing signal 16 is disconnected, the signal disconnection detection circuit 13 detects this and the switching command signal 21 is sent to the signal selection circuit 12.
To send a free-running command signal 20 to the phase-locked oscillator circuit 14. In response to this, the signal selection circuit 12 selects the data code string 15 and sends it as the data code string 18 to be transmitted to the transmitting end S1. In the normal case where the first timing signal 16 is not broken, the signal selection circuit 12 selects the read data code string 19. When the phase-locked oscillator circuit 14 receives the free-running command signal 20, it stops the phase-locked operation and gives a fixed voltage to the voltage-controlled oscillator circuit to operate as a simple free-running oscillator circuit. Therefore, when the reception timing signal 16 is cut off and the write clock signal to the buffer memory circuit 11 is cut off, the data code string 15 is selected, so that the data code string synchronized with the transmission timing signal 17 is transmitted.

[Effect of device]

As is apparent from the above description, according to the present invention, in the data transmission / reception device, the data code string can be transmitted without causing the data delay even in the case of the disconnection of the transmission timing signal given from the outside. .

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a block diagram of a conventional example. FIG. 3 is an explanatory diagram of a system using a conventional example. 11 ... Buffer memory circuit, 12 ... Signal selection circuit, 13 ...
… Signal loss detection circuit, 14 …… Phase-locked oscillator circuit, 15 …… Received data code string, 16 …… Reception timing signal, 17
...... Transmission timing signal, 18 …… Sent data code string, 19 …… Read data code string, 20 …… Self-running command signal, 21 …… Switch command signal, 31, 33 …… Data transmission / reception device, 32 …… Data terminal device, 34 …… Signal switch, R1, R2
…… Reception end, S1 to S3 …… Transmission end.

Claims (1)

[Scope of utility model registration request] 1. A buffer memory circuit (11) in which a received data string is written in synchronization with a reception timing signal input from the outside and read out in synchronization with a transmission timing signal, and transmitted in synchronization with the reception timing signal. A phase-locked oscillator circuit (14) that generates a timing signal and supplies it to the buffer memory, and a signal disconnection detection circuit (13) that detects a disconnection of the reception timing signal are provided. In a data transmission / reception device configured to become a free-running oscillation circuit by the detection output of the disconnection detection circuit, the reception data string is selected as transmission data instead of the read output from the buffer memory circuit by the detection output of the signal disconnection detection circuit. A data transmission / reception device comprising a signal selection circuit (12) for outputting the output.