JPH05244451A - Synchronizing signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain a simple and inexpensive synchronizing signal generating circuit for both internal and external clocks by employing a simple and inexpen sive vertical counter and its peripheral circuit. CONSTITUTION:The circuit includes a vertical counter 5' counting internal clocks, a vertical synchronizing signal generating memory 6 addressed by an output of the vertical counter 5' and outputting plural vertical synchronizing signals, and an OR circuit 4 receiving a signal generated based on an external input vertical synchronizing signal and one of specific vertical synchronizing signals outputted from the memory 6 and giving its output to a reset terminal of the vertical counter 5'. Then the vertical counter 5' is devised so as to be reset by both a signal based on the external input vertical synchronizing signal and the specific vertical synchronizing signal outputted from the memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit for use in a CRT video device or the like, which is characterized by automatically switching between external synchronization operating according to an external control signal and internal synchronization operating according to an internal synchronization signal. The present invention relates to a signal generation circuit.

[0002]

2. Description of the Related Art Conventionally, there is a circuit of this type as shown in FIG. In FIG. 2, reference numeral 3 is a mono-multivibrator for inputting an externally input vertical synchronizing signal to the input terminal 1, and 2 is a mono-multiplexer 3 for a logic input.
The flip-flop 5 which inputs the output of the flip-flop and inverts the output state by the clock signal received by the clock input is generally composed of a plurality of stages, and is counted by the clock signal received by the clock input , A vertical counter capable of outputting a parallel signal of a plurality of bits, a desired value is preset by the output signal of the flip-flop 2 received at the load input, and 8 is an output terminal for outputting various vertical synchronizing signals from the synchronizing signal generating circuit Reference numeral 17 denotes a logic circuit that receives a parallel output signal from the vertical counter 5 and outputs various vertical synchronizing signals corresponding thereto and a reset signal (a specific one of the vertical synchronizing signals) to the vertical counter 5, and 18 various types. Is a horizontal synchronization unit that outputs the horizontal synchronization signal of.

In the synchronizing signal generating circuit thus constructed, the vertical counter 5 normally receives and counts the clock signal from the horizontal synchronizing section 18, and generates parallel count outputs from the respective stages of the counter. The count output is processed by the logic circuit 17, and various necessary vertical synchronizing signals are selectively output. When the logic circuit 17 receives a specific count output, it outputs a reset signal and sends it to the reset input of the vertical counter 5 to reset the vertical counter 5.

On the other hand, when the external input vertical synchronizing signal is received from the terminal 1, the mono-multivibrator 3 is turned on, its output becomes active (hereinafter referred to as "high"), and the input of the flip-flop 2 becomes "high". Therefore, the flip-flop 2 is inverted (turned on) by the next clock.
The "high" output of flip-flop 2 is the vertical counter 5
Sent to the load input of, and suspends the counting of the vertical counter 5. After stopping the count, the vertical counter 5 immediately presets a new count value from the outside,
The count starts immediately from the next clock. In this way, the vertical counter 5 is instantaneously switched from internal synchronization to external synchronization.

That is, when switching and using as the external synchronization, it is necessary to suspend the vertical counter 5 based on the external input vertical synchronization signal and preset a new value, thereby generating various vertical synchronization signals. Therefore, the signal formed by the external input vertical synchronizing signal is transmitted to the load input of the vertical counter 5. Then, the vertical counter 5 temporarily stops its function, presets a new count value, and restarts counting from the preset value by the next clock applied to the vertical counter.

[0006]

However, in the conventional synchronizing signal generating circuit for both internal and external purposes, the vertical synchronizing signal for external synchronization is generated based on the reception of the externally input vertical synchronizing signal. Therefore, it was necessary to use a presettable vertical counter that has a load input in addition to a reset input. Since such a counter with a preset has a complicated function, a considerably expensive one is required and a counter circuit is complicated.

The present invention has been made to solve the above problems, and by using a simple and inexpensive vertical counter and its peripheral circuits, a simple and inexpensive internal / external synchronizing signal generating circuit is provided. The purpose is to provide.

[0008]

In order to solve the above problems, the present invention is directed to a vertical counter which counts by an internal clock and a vertical sync signal generator which outputs a plurality of vertical sync signals addressed by the output of the vertical counter. A memory, and an off circuit for inputting a signal formed based on an external input vertical synchronization signal and one of the specific vertical synchronization signals output from the memory and connecting an output to a reset terminal of the vertical counter, The vertical counter can be reset by either a signal based on the externally input vertical sync signal or a specific vertical sync signal output from the memory.

[0009]

In the present invention, since the vertical counter inputs the internal synchronizing (reset) signal from the vertical synchronizing signal generating memory and the input signal based on the external input vertical synchronizing signal to the reset terminal through a simple OR circuit. , The vertical counter may have a simple function without the preset function,
The synchronizing signal generating circuit can also be simple. Moreover, when using the external synchronization, it is only necessary to input the external input vertical synchronization signal, and it is possible to perform it instantly.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIG. In FIG. 1, the same reference numerals as those in FIG. 2 are used for the respective components that are the same as those in FIG.
That is, the input terminal 1, the flip-flop 2 in FIG.
The mono-multivibrator 3, the output terminal 8 and the horizontal synchronizing section 18 are the same as those already described with reference to FIG. 2, so further description will be omitted.

Further, the input terminal 9, the PLL 10, the VCO 11, the signal switch 12, which is arranged in the horizontal synchronizing section 18,
The reference signal generator 13, the horizontal counter 14, the horizontal synchronizing signal generating memory 15, and the output terminal 16 are not directly related to the present invention, and therefore their explanations are omitted. Next, important elements directly related to the present invention will be described with reference to FIG. 5
′ Is a vertical counter having a clock input for synchronization on the input side and a reset input for resetting and a parallel output of a plurality of bits on the output side, 6 is a vertical counter 5
A vertical sync signal generating memory for receiving a parallel output signal from the address signal as an address signal, reading a memory content from an addressed memory location as a parallel data signal composed of a plurality of bits, and outputting as a vertical sync signal, 4 is a vertical sync signal An external synchronization signal input from one of the vertical synchronization signals read from the memory for generation to one input terminal and input via the flip-flop 2 and the mono-multivibrator 3 based on the received external input vertical synchronization signal. Is input to the other input terminal and the output is output to the reset input of the vertical counter 5 '.

In the above structure, the horizontal synchronizing section 1
The synchronizing clock signal obtained from 8 is the vertical counter 5 '.
Counting, the vertical counter 5'outputs an address signal of a plurality of parallel bits to address the vertical synchronizing signal generating memory 6. A desired vertical synchronizing signal is output from the addressed storage location of the vertical synchronizing signal generating memory 6 and used for a predetermined purpose.

When a specific address location of the vertical synchronizing signal generating memory is addressed, the specific vertical synchronizing signal is read from the address and transmitted to one input terminal of the OR circuit 4. When the specific signal is input, the OR circuit 4 sends the output signal as a reset signal to the reset input of the vertical counter 5 ', resets the vertical counter 5', and synchronizes the counter 5 '(internal synchronization). To take.

When an external input vertical synchronizing signal is received at the input terminal 1, it is connected to the input of the flip-flop 2 and the flip-flop 2 is driven by the next clock signal (identical to that which clocks the vertical counter 5 '). Invert (turn on). When the flip-flop 2 is turned "on", its output which becomes "high" activates the mono-multivibrator 3 and from its output to the other input terminal of the OR circuit 4 is "high" for a predetermined period. The signal of is output.
The "high" signal is transmitted to the reset input of the vertical counter 5'through the output of the OR circuit 4 and the vertical counter 5 '
Is reset to synchronize the vertical counter 5 '(external synchronization)
Take

As is apparent from the above description, when the external input vertical synchronizing signal is not input, only the specific vertical synchronizing signal from the vertical synchronizing signal generating memory 6 becomes the reset signal for the vertical counter 5 '. The synchronization signal generation circuit is operated as internal synchronization. On the other hand, input terminal 1
When an externally input vertical synchronizing signal is input to, the signal is formed as a reset signal for the vertical counter 5 ', and the synchronizing signal generating circuit is operated as external synchronizing.

Of course, even in the case of external synchronization, the reset signal from the vertical sync signal generation memory 6 becomes "high" and is input to the vertical counter 5 ', but it is in phase with the external reset signal. There is no particular problem because it goes high. If the reset signal from the outside is generated earlier, the reset signal from the inside is not generated.

[0017]

As described above, the present invention uses an inexpensive vertical counter having no preset function, sends internal and external reset signals to the vertical counter through a simple OR circuit, and Since it is configured to synchronize, switching between internal synchronization and external synchronization can be performed easily and instantaneously, and since a general-purpose memory can be used for the vertical synchronization signal generation memory, it is extremely inexpensive and easy. It is possible to provide a synchronizing signal generating circuit that generates a vertical synchronizing signal of various timings with various circuits.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal / external synchronization signal generation circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing in detail a vertical synchronization portion of a conventional internal / external synchronization signal generation circuit.

[Explanation of symbols]

 1: External input vertical sync signal 2: Flip flop 3: Mono-multivibrator 4: OR circuit 5, 5 ': Vertical counter 6: Vertical sync signal generation memory 8: Vertical sync signal

Claims (1)

[Claims] 1. A vertical counter that counts with an internal clock, a vertical sync signal generating memory that outputs a plurality of vertical sync signals that are addressed by the output of the vertical counter, and a signal that is formed based on an externally input vertical sync signal. An off circuit for inputting one of the specific vertical synchronization signals output from the memory and connecting an output to a reset terminal of the vertical counter, the vertical counter including a signal based on the external input vertical synchronization signal and the memory. An internal / external sync signal generation circuit characterized in that it can be reset by any of the specific vertical sync signals output from the device.