JPH04335412A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To synchronize a reset signal and a system clock by providing a frequency dividing circuit for frequency-dividing a source oscillation clock, and a resetting circuit for resetting the frequency dividing circuit for a prescribed time in response to a fact that the reset signal is varied from an active level to a non-active level. CONSTITUTION:The clock generating circuit is provided with a synchronizing circuit 10 for synchronizing a reset signal RES and a frequency dividing stage clock (c), and a clock selecting circuit 20 for selecting a source oscillation clock CK and the frequency dividing clock (c). Also, the synchronizing circuit 10 consists of a first D-flip-flop 11, for dividing the source oscillation clock CK, and a reset circuit 12 for resetting a first D-flip-flop 11 for a prescribed time or above in response to a fact that the reset signal RES is varied from an L level to an H level. The reset circuit 12 is constituted of a second and a third D-flip-flops 13, 14 and a NAND circuit 15.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit for a microcomputer or the like.

0002

2. Description of the Related Art FIG. 4 shows a conventional clock generation circuit for a system that operates by frequency-dividing a system clock φin from a source clock CK, and FIG. 5 shows its input/output signal waveforms.

A source clock CK is input to the clock input terminal of the D flip-flop 1. A *Q output terminal is connected to the data input terminal of the D flip-flop 1. Then, a system clock φi with a period twice that of the source clock CK is output from the Q output terminal of the D flip-flop 1.
n is output.

0004

[Problem to be Solved by the Invention] In this clock generation circuit, it is unclear whether the state of the system clock φin output from the Q output terminal of the D flip-flop 1 is φin-1 or φin-2 in FIG. . That is, it is unclear whether the level of the system clock φin is H or L with respect to the source clock CK. Therefore, when starting the system by changing the reset signal from L level to H level, there is a problem that synchronization cannot be achieved, and a separate synchronization routine is required during testing, which increases test time. .

[0005] Furthermore, in a CPU system, the CPU
Since it fetches a reset signal in synchronization with φin, it also has the disadvantage that the response to reset is slow depending on the state of the system clock φin.

A first clock generation circuit according to the present invention aims to provide a clock generation circuit that can synchronize a reset signal and a system clock.

A second clock generation circuit according to the present invention aims to provide a clock generation circuit that can synchronize a reset signal with a system clock and has a quick response to a reset.

[0008]

[Means for Solving the Problems] A first clock generating circuit according to the present invention includes a frequency dividing circuit that divides a source clock, and a frequency dividing circuit that divides a source clock in response to a change in a reset signal from an active level to an inactive level. The present invention is characterized by comprising a reset circuit that resets the circuit for a predetermined period of time.

A second clock generating circuit according to the present invention includes a frequency dividing circuit that divides the frequency of the source clock, and a frequency dividing circuit that resets the frequency dividing circuit for a predetermined time in response to a reset signal changing from an active level to an inactive level. A reset circuit that normally outputs a source clock selection signal, outputs a divided clock selection signal in response to the reset signal changing from an active level to an inactive level, and outputs a divided clock selection signal when the reset signal changes from an inactive level to an active level. A switching signal generation circuit that outputs a source clock selection signal in response to a change in the level, and a switching signal generation circuit that outputs a source clock when the source clock selection signal is output from the switching signal generation circuit and generates a switching signal. The present invention is characterized by comprising a data selector that outputs the output of the frequency dividing circuit when the frequency divided clock selection signal is output from the circuit.

0010

[Operation] In the first clock generation circuit according to the present invention,
A system clock is generated by frequency-dividing the source clock by a frequency dividing circuit. When the reset signal changes from an active level to an inactive level, the frequency divider circuit is reset for a predetermined period of time in response.

In the second clock generating circuit according to the present invention, the source clock is frequency-divided by the frequency dividing circuit. When the reset signal changes from active level to inactive level,
In response to this, the frequency dividing circuit is reset for a predetermined period of time. The source clock and the output of the frequency dividing circuit are sent to the data selector. The clock selection circuit is controlled by a selection signal from the switching signal generation circuit.

The switching signal generation circuit normally outputs a source clock selection signal, and in response to the reset signal changing from an active level to an inactive level, a divided clock selection signal is output, and the reset signal is In response to the change from the inactive level to the active level, a source clock selection signal is output. The data selector outputs the source clock when the switching signal generation circuit outputs the source clock selection signal, and outputs the frequency division circuit when the switching signal generation circuit outputs the divided clock selection signal. is output.

[0013]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.

FIG. 1 shows a clock generation circuit in a microcomputer.

[0015] The clock generation circuit generates a reset signal *RE.
Synchronization circuit 1 for synchronizing S and frequency division stage clock c
0, and a clock selection circuit 20 for selecting the source clock CK and the divided clock c.

The synchronization circuit 10 includes a first D flip-flop 11 for dividing the frequency of the source clock CK, and a predetermined operation of the first D flip-flop 11 in response to the change of the reset signal *RES from the L level to the H level. It consists of a reset circuit 12 that resets for more than a time. The reset circuit 12 includes second and third D flip-flops 13 and 14.
and a NAND circuit 15.

The clock selection circuit 20 selects a source clock C
A switching signal generation circuit 21 generates selection signals g and *g between K and frequency-divided clock c, and source clock CK or frequency-divided clock c according to selection signals g and *g from switching signal generation circuit 21. and a data selector 22 that outputs the system clock φin as the system clock φin.

The switching signal generating circuit 21 is composed of the NAND circuit 15, a NOR function circuit 23, an *S*R flip-flop 24, and a fourth D flip-flop 25. The data selector 22 includes two AND gates 26 and 27, a NOR circuit 28, and a NOT circuit 29.

FIG. 2 shows the signals of each part in FIG. 1 when the reset signal *RES rises at the falling timing of the source clock CK. In addition, in FIG. 3, the reset signal *RE is sent at the rising timing of the source clock CK.
It shows the signals of each part in FIG. 1 when S rises.

First, the operation of the synchronous circuit 10 will be explained. In the synchronous circuit 10, regardless of whether the Q output c of the first flip-flop 11 that divides the frequency of the externally sourced clock CK is at H or L level, the first flip-flop 11 is reset (signal d) and is separated from the reset signal *RES so that the Q output c of the first flip-flop 11 always changes from L to H at the next fall timing of the source clock CK after the rise of the reset signal *RES. Synchronization with the stage clock c is achieved.

Referring to FIGS. 1, 2 and 3, at time t
1, when the reset signal *RES rises, the Q output a of the second flip-flop 13 becomes H level at the subsequent rising timing of the first source clock CK (time t2). Also, the first source clock C after time t2
At the falling timing of K (time t3), the *Q output b of the third flip-flop 14 becomes L level.

The output d of the NAND circuit 15 is always at the H level, and between time points t2 and t3 when the Q output a of the second flip-flop 13 and the *Q output b of the third flip-flop 14 are both at the H level. becomes L level.

This signal d is applied to the first flip-flop 11.
As shown in FIG. 2, the Q output c of the first flip-flop 11 at time t2
is at L level, its Q output c is at least at time t
As shown in FIG.
If the Q output c of the first flip-flop 11 is at H level immediately before, the Q output c is inverted to L level at time t2. In the case of FIG. 2, the source clock C at time t3
K falls, but due to this falling, the D input data is not read into the first flip-flop 11, and the first
The Q output c of the flip-flop 11 maintains the L level.

At the falling timing of the first source clock CK after time t3 (time t4), the D input data is read into the first flip-flop 11, and the Q output c of the first flip-flop 11 changes from the L level. Inverted to H level. From then on, every time the source clock CK falls, the Q output c of the first flip-flop 11 is inverted, and a signal with twice the period of the source clock CK becomes the Q output c.
obtained as.

Next, the operation of the clock selection circuit 20 will be explained.

When the reset signal *RES falls at time t5, the Q output a of the second flip-flop 13 becomes L level at the timing of the first rise of the source clock CK (time t6). Also, the falling timing of the first source clock CK after time t6 (time t7
), the *Q output b of the third flip-flop 14 becomes H level.

The output e of the OR function circuit 23 is always at the H level, and from time t6 to t7 when the Q output a of the second flip-flop 13 and the *Q output b of the third flip-flop 14 are both at the L level. It is at L level only during that time.

Therefore, the SR flip-flop 22 is reset at time t2 by the signal d and set at time t6 by the signal e, so the Q output f of the SR flip-flop 24 is at L level from time t2 to t6. .

Until time t2, the SR flip-flop 2
Since the Q output f of the fourth D flip-flop 25 is at H level, the Q output g of the fourth D flip-flop 25 is at H level until time t3.
*Q output *g is at L level until time t3. Therefore, until time t3, one of the AND gates 26 and 27 is
Only the D gate 27 opens, the source clock CK passes through the AND gate 27, and the NOR circuit 28 and NOT circuit 2
It is output as the system clock φin via 9.

At time t2, the Q of the SR flip-flop 24
The output f is inverted to L level, and accordingly, at time t3,
When the Q output g of the fourth D flip-flop 25 is inverted to L level and *Q output*g is inverted to H level,
AND gate 27 is closed and AND gate 26 is opened. Therefore, the Q output c (signal obtained by dividing the frequency of the source clock CK by two) of the first flip-flop 11 passes through the AND gate 26 and is outputted as the system clock φin via the NOR circuit 28 and the NOT circuit 29.

At time t6, the Q of the SR flip-flop 24
When the output f is inverted to H level, the falling timing of the system clock φin after time t6 (time t8)
Then, the Q output f of the SR flip-flop 24 is read into the fourth D flip-flop 25. Therefore, time t
At 8, the Q output g of the fourth D flip-flop 25 is inverted to H level, and the *Q output*g is inverted to L level, AND gate 27 is opened and AND gate 26 is closed. Therefore, the source clock CK passes through the AND gate 27 and is output as the system clock φin via the NOR circuit 28 and the NOT circuit 29.

That is, in this clock selection circuit 20,
Selection signals g and *g, which are the Q and *Q outputs of the fourth D flip-flop 25, are created by the one-pulse signals d and e, and the selection signal g is set to H level (reset signal *RES
=L level), the source clock CK is output as the system clock φin, and the sampling until the reset signal *RES is inverted from the L level to the H level is accelerated, thereby speeding up the response of the CPU.

On the other hand, when the selection signal g is at L level (reset signal *RES=H level), the first flip-flop 1
The divided clock c, which is the Q output of 1, is the system clock φ
It is output as in and normal processing is performed.

The reason why the system clock φin is used as the clock for the fourth D flip-flop 25 instead of the source clock CK is to avoid the situation shown by the broken line A in FIG.

Although the example of frequency division by 2 has been explained, in the case of frequency division by n, an n-ary counter may be used instead of the first flip-flop 11.

Furthermore, although the reset signal *RES is used as the synchronization signal, the same applies to other synchronization signals such as the interrupt signals INTR and SYNC as well as the other reset signals *RES.

[0037]

According to the first clock generation circuit according to the present invention, the reset signal and the system clock can be synchronized.

According to the second clock generation circuit according to the present invention, the reset signal and the system clock can be synchronized, and the response to the reset can be made faster.

[Brief explanation of drawings]

FIG. 1 is an electrical circuit diagram showing a clock generation circuit of a microcomputer.

FIG. 2 is a time chart showing the signals of each part in FIG. 1 when the reset signal *RES rises at the falling timing of the source clock CK.

FIG. 3 is a time chart showing signals of each part in FIG. 1 when the reset signal *RES rises at the rising timing of the source clock CK.

FIG. 4 is an electric circuit diagram showing a conventional example.

FIG. 5 is a time chart showing input and output signals of the circuit in FIG. 4;

[Explanation of symbols]

10 Synchronous circuit 12 Reset circuit 20 Clock selection circuit 21 Switching signal generation circuit 22 Data selector

Claims (2)

[Claims] [Claim 1] A frequency dividing circuit that divides a source clock;
A clock generation circuit comprising: a reset circuit that resets a frequency dividing circuit for a predetermined period of time in response to a change in a reset signal from an active level to an inactive level. [Claim 2] A frequency dividing circuit that divides a source clock;
A reset circuit that resets the frequency divider circuit for a predetermined period of time in response to a change in the reset signal from an active level to an inactive level, and a reset circuit that normally outputs a source clock selection signal and which changes the reset signal from an active level to an inactive level. A switching signal generation circuit that outputs a divided clock selection signal in response to a change in frequency, and outputs a source clock selection signal in response to a change in a reset signal from an inactive level to an active level, and a switching signal generation circuit. and a data selector that outputs the source clock when the source clock selection signal is output from the circuit and outputs the output of the frequency dividing circuit when the switching signal generation circuit outputs the divided clock selection signal. Equipped with a clock generation circuit.