JPH02290322A - Clock signal switching circuit - Google Patents

Abstract

PURPOSE:To switch a clock signal while preventing glitch by providing plural clock signal input sections, an FF receiving a selection signal, a 3-input NAND receiving an FF output, the selection signal and a clock signal and a NAND receiving an output of the 3-input NAND. CONSTITUTION:Signals from clock signal input terminals 8, 9 and a clock of FFs 1, 2 are inputted to 3-input NANDs 3, 4. The clock signal 8 or 9 is selected by using a selection signal 7. For example, to select the signal 8 from the signal 9, the level is set to H from L in a timing. The selection signal 7 is synchronously with the clock signal selected at present as the system clock. The output from the NAND 4 of the signal 9 is inhibited by the selection signal 7 but since the signal 8 is asynchronous, while the FF1 latches one clock, glitch is prevented and the NAND 4 is opened from the succeeding clock to obtain a prescribed timing and even when the selection signal is asynchronous with the clock, the old and new clocks are selected without any glitch. The switching from the signal 8 to 9 is implemented similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock signal switching circuit, and more particularly to a clock signal switching circuit that switches a plurality of asynchronous clock signals using a selection signal.

[Conventional technology]

Conventionally, this type of clock signal switching circuit has had a configuration as shown in FIG. 4, for example. Figure 4A is a circuit diagram,
B is a timing chart.

26 and 28 are clock signal sections, which are asynchronously input to AND21 and AND22. Here, the selection signal 27 for selecting one of the clock signals changes from a high level to a low level in order to switch from clock signal 28 to clock signal 26, for example.
The output of D22 is inhibited and the output of AND21, that is, 26
clock signal is selected.

[Problem to be solved by the invention]

The conventional clock signal switching circuit described above is shown in FIG. 3B.
As can be seen from the timing chart, the clock signal 28 is inhibited in synchronization with the selection signal, but the clock signal 26 is immediately selected, resulting in a glitch in the clock signal that remains asynchronous. It has the disadvantage that it is output as

Since the selection signal is input asynchronously to the clock, the type of glitch that will occur is uncertain, and to prevent this, the selection signal must be input in synchronization with each clock. Requires restrictions on handling and handling. Furthermore, if there is a counter at the next stage, it may or may not count this crunch, which can easily cause malfunctions.

[Means to solve the problem]

The clock signal switching circuit of the present invention includes a plurality of clock signal input sections, a plurality of DF/Fs each having a clock signal as a clock input and a selection signal for switching the clock signal as a data input, and the DF/Fs. It is composed of a 3NAND which inputs the output of , a selection signal, and a clock signal, and a NAND which inputs the output of each of the four 3NANDs.

That is, the present invention prevents the newly selected clock signal from being immediately enabled by inputting the clock signal through the data F/F (DF/F), thereby causing Eliminates glitch when switching.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1A is a circuit diagram of a first embodiment of the present invention, and FIG. 1B is a timing chart of the circuit diagram of FIG. 1A. 8 and 9 are clock signal input sections, DF/Fl and 2
clock and is input to three NANDs 3 and 4.

Reference numeral 7 denotes a selection signal for switching between the clock signal 8 and 9, and is set from low to high at a certain timing, for example, in order to switch from the clock signal 9 to the clock signal 8. This selection signal 7 is synchronized with the clock signal 9 currently selected as the system clock. The clock signal 9 immediately prohibits the output of the NAND4 by the selection signal 7, but since the clock signal 8 is asynchronous, the period during which the DF/Fl latches one clock, that is, the glitch is prevented and the NAND4 is output from the next clock. By allowing this, the timing 5 in FIG. 1B is obtained. The same applies to the case of switching from clock signal 8 to clock signal 9.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

The second embodiment is a clock signal switching circuit with a decoder added when there are first to nth clock input signals. In the first embodiment, one bit was enough for the selection signal to switch between two clock input signals, but if n types of clock input signals 10 are input, the decoder 20 selects any one of the plurality of clock input signals. The configuration is such that a selection signal for selection (setting the data input of the DF/F to high level) is generated and used as the data input of each DF/F.

In this embodiment, it is possible to quickly select any clock signal from a plurality of clock signals.

FIG. 3A is a circuit diagram of a third embodiment of the present invention, and FIG. 3B is a timing chart of FIG. 3B. In the first and second embodiments, there is a restriction that the selection signal must be input in synchronization with the currently selected clock signal. In the third embodiment, for multiple clock signals,
This is an example in which a means for synchronizing a selection signal input asynchronously is added.

The first clock CO is transmitted from the first clock signal input terminal 108 to the second F/F 1 0 2 and the third F/F.
I. 0 3 =,, second clock signal input terminal 1
From 09 onwards, the second clock CI is input to the first F/F] 01 and the fourth F/F 1 0 4.

The asynchronous selection signal 107 is inputted to the first and second F/Fs, and outputted to the next stage third and fourth F/Fs in synchronization with the first and second clocks. (Refer to the timing chart in Figure 3B) In the first and second embodiments, the selection signal 107 was directly input to the 3AND, but it is synchronized with other clocks in the first and second F/Fs. This embodiment makes it possible to switch without glitches even if the selection signal is asynchronous to the clock because a signal is created and the product term is used as a product term.

〔Effect of the invention〕

As explained above, the present invention provides F/Fs in parallel, inputs a clock signal to each clock input, inputs a selection signal to theta input, and receives the F/F output signal, each clock signal and selection signal. 3NAND powered by three people
By adopting a configuration in which switching is performed, the old clock signal can be immediately inhibited, glitches can be prevented, and switching to the new clock signal can be easily performed.

[Brief explanation of the drawing]

1A is a circuit diagram of the first embodiment of the present invention, FIG. 1B is a timing chart of FIG. 1A, FIG. 2 is a circuit diagram of the second embodiment, and FIG. 3A is a timing chart of FIG. 3B is the timing chart of FIG. 3A, FIG. 4A is the circuit diagram of the conventional embodiment, and FIG. 4B is the timing chart of FIG. 4B.
It is a chart. ■・・・Data flip-flop (DF/F),
2...DF/F, 3...3NAND, 4
...3NAND, 5...2N△ND, 6.
. . . Clock signal output section, 7 . . . Selection signal switching section, cursor, mark, black, ku signal input section, 9 . . .
・Clock signal input section, 0... Inverter, 2
1...2AND. 22...2AND,
25... Clock output section, 26... River/clock input section, 27... Selection signal input section, 28...
Group/crossoku input section, l1...DF/F. l
2...3NAND. 13... Clock input section, l4... Clock input section (2), 15...
. . . Clock input section (3), 16 . . . Clock signal (1). 17...Clock signal (2)
, 18... Clock signal (3), 19...
...3 NAND, 10... Tecoder input selection signal (n input), 20... n person decoder. 100...2AND,105,106...
・3AND, 101... No. IDF/F, 1
0 2...2nd DF/F, 103...
・3rd DF/F. 104...4th DF/F, 1
08...First clock input terminal, 109...
. . . second clock input terminal, 107 . . . selection signal input terminal. Agent Patent Attorney Susumu Uchihara 1 Figure Δ Figure 1B

Claims (2)

[Claims] (1) A plurality of clock output control circuits are provided that receive a clock signal and a selection signal and output the clock signal when the selection signal is at an active level, and each clock output control circuit receives a corresponding clock input signal as a clock input. a flip-flop (hereinafter referred to as F/F) that receives a corresponding selection signal as its data input; and a gate circuit that receives the output signal of this F/F, the corresponding clock input signal, and the corresponding selection signal as input. A clock signal switching circuit comprising: (2) As a means for synchronizing the asynchronous input selection signal with the clock input signal, the asynchronous selection signal is used as a data input;
It has a second and first F/F that uses the first and second clock signals as clock inputs, and a third F/F that uses the output of the first F/F as its data input and the first clock signal as its clock input. F
/F, a fourth F/F which uses the output of the second F/F as a data input and the second clock signal as a clock input, and a first F/F.
A gate circuit that inputs the inverted output of /F, the output of the fourth F/F, and the second clock signal, and the inverted output of the second F/F, the output of the third F/F, and the first clock signal. A clock signal switching circuit that has means for selecting the output of one of the gate circuits.