JPH08328687A - Clock changeover circuit - Google Patents

Abstract

PURPOSE: To prevent incorrect clock generated due to dispersion such as manufacture process. CONSTITUTION: The circuit is provided with a register section 11 to 15 latching periodically a selection signal, a selection section 19 to 21 selecting a clock signal A or B based on the selection signal from the register section 11 to 15, output sections 16 to 18, 22 providing the selected clock signal as an output clock signal externally and stopping tentatively the supply of the output clock signal attended with a change in the selection signal obtained from the register section 11 to 15, flip-flop circuits 11 to 15 connected in cascade to form a shift register and latching sequentially the selection signal synchronously with the selected clock signal as a register section and the selections 19 to 21 are connected to receive the selection signal latched by the flip-flop 13 and output sections 16 to 18 and 22 are connected to receive the selection signal latched by the pre-stage flip-flop 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching circuit for switching between two types of clock signals having different frequencies.

[0002]

2. Description of the Related Art In computer systems, it may be necessary to change the clock frequency. FIG. 5 shows a conventional clock switching circuit used in this case. The D-type flip-flops 31-34 form a shift register that periodically latches the clock selection signal C. AND gates 35 and 36 and NOR gate 37 are flip-flops 32.
And a mask signal generator that temporarily generates a mask signal w in accordance with a change in the clock selection signal C obtained from the above. AND gates 38 and 39 and NOR gate 40
Constitutes a selection unit for selecting one of the first clock signal A and the second clock signal B based on the clock selection signal C obtained from the flip-flop 32. NOR gate 4
Reference numeral 1 constitutes an output unit which supplies the clock signal x obtained from the NOR gate 40 to the outside as an output clock signal out and temporarily invalidates the output clock signal out by the mask signal w obtained from the NOR gate 37.

The operation of this clock switching circuit is shown in FIG. Here, it is assumed that the frequency of the output clock signal out is equal to the frequency of the clock signal A. In this state, when the clock selection signal C falls to a low level as shown in FIG. 6, the low level clock selection signal C is flip-flop 31 at the rising edge P1 of the clock signal x.
Are latched by the flip-flop 32 at the rising edge P2 of the clock signal x, are latched by the flip-flop 33 at the rising edge P3 of the clock signal x, and are latched by the flip-flop 34 at the rising edge P4 of the clock signal x. The selection unit uses the rising edge P of the clock signal x.
At 2, the clock signal B is selected based on the clock selection signal C obtained from the flip-flop 32. After this,
The clock signal x is synchronized with the clock signal B.

The contents of the flip-flop 32 do not match the contents of the flip-flop 34 only during the period from the rising edge P2 to P4 of the clock signal x. The mask signal generation unit generates the mask signal w which is maintained at the high level only during the period when the mismatch is detected. That is, the mask signal w invalidates the output clock signal out during this period. The frequency of the output clock signal out becomes equal to the frequency of the clock signal B after the falling of the mask signal w.

[0005]

However, when the flip-flop 32 latches a clock selection signal different from that of the flip-flop 34 at the rising edge of the clock signal x,
The mask signal w rises with a delay depending on variations in the manufacturing process. If the delay time t2 is longer than the pulse duration t1 of the clock signal x as shown in FIG. 7, an incorrect clock will be generated in the output clock signal out.

An object of the present invention is to provide a clock switching circuit capable of preventing an illegal clock generated immediately after clock switching due to variations in manufacturing process.

[0007]

According to the present invention, a register unit for periodically latching a clock selection signal and a first selection unit based on the clock selection signal obtained from the register unit are provided.
And a selection unit for selecting one of the second clock signal and the clock signal selected by the selection unit as an output clock signal to the outside, and the output clock signal of the output clock signal according to the change of the clock selection signal obtained from the register unit The register unit is provided with an output unit for temporarily stopping the external supply, and the register units are connected in series so as to form a shift register. The selection unit is connected to receive a clock selection signal latched by a predetermined flip-flop of the plurality of flip-flops, and the output unit is latched by a flip-flop preceding the predetermined flip-flop. Connected to receive the selected clock select signal Lock switching circuit is provided.

[0008]

In this clock switching circuit, a plurality of flip-flops are connected in cascade so as to form a shift register, and the clock selection signals are sequentially latched in synchronization with the clock signal from the selection unit. The selection unit is connected so as to receive the clock selection signal latched by a predetermined one of these flip-flops, and the output unit is connected so as to receive the clock selection signal latched by a flip-flop preceding the predetermined flip-flop. To be done. As a result, the output unit can respond to the change in the clock selection signal before the selection unit by the step difference between the predetermined flip-flop and the previous-stage flip-flop. Even when the change of the clock selection signal cannot be quickly responded to, the selection unit can switch one of the first and second clock signals to the other after the output unit stops the external supply of the output clock signal. That is, since the clock is not switched during the external supply of the output clock signal,
It is possible to reliably prevent an illegal clock generated immediately after this switching. Therefore, it is possible to reliably improve the reduction in yield due to the variation in the manufacturing process.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock switching circuit according to a first embodiment of the present invention will be described below with reference to FIG.

This clock switching circuit comprises five D-type flip-flops 11-15 and AND gates 16, 17, 1.
9 and 20, and NOR gates 18, 21 and 22. The flip-flops 11-15 are cascaded to form a shift register for sequentially latching the clock selection signal C. That is, the flip-flop 11
Is connected to the input terminal of the clock selection signal C, the D input terminal of the flip-flop 12-15 is connected to the Q output terminal of the flip-flop 11-14, and each clock terminal of the flip-flop 11-15 is a clock. Connected to receive signal x.

The AND gates 16 and 17 and the NOR gate 18 constitute a mask signal generator for temporarily generating the mask signal w in accordance with the change of the clock selection signal C obtained from the shift register. The first and second input terminals of the AND gate 16 are connected to the Q output terminal of the flip-flop 15 and the Q output terminal of the flip-flop 12, respectively. The first and second input terminals of the AND gate 17 are connected to the Q-bar output terminal of the flip-flop 15 and the Q-bar output terminal of the flip-flop 12, respectively. The first and second input terminals of the NOR gate 22 are connected to the output terminal of the AND gate 16 and the output terminal of the AND gate 17, respectively. The AND gate 16 outputs the high-level clock selection signal to the flip-flops 12 and 1
5 produces an output signal that is set high only when latched by both 5, and AND gate 17 is set high only when a low level clock select signal is latched by both flip-flops 12 and 15. Output signal. NOR gate 22 generates an output signal set to a high level except when at least one of the output signal of AND gate 16 and the output signal of AND gate 17 is set to a high level. That is, the output signal of the NOR gate is maintained at the high level as the mask signal w only while the clock selection signal latched by the flip-flop 12 does not match the clock selection signal latched by the flip-flop 15.

The AND gates 19 and 20 and the NOR gate 21 are connected so as to form a selection unit for selecting one of the first clock signal A and the second clock signal B based on the clock selection signal obtained from the shift register. It The first and second input terminals of the AND gate 19 are connected to the Q output terminal of the flip-flop 13 and the input terminal of the first clock signal A, respectively. The first and second input terminals of the AND gate 20 are flip-flops 1
3 is connected to the Q-bar output terminal and the input terminal of the second clock signal B, respectively. The first and second input terminals of the NOR gate 21 are connected to the output terminal of the AND gate 19 and the output terminal of the AND gate 20, respectively. The AND gate 19 supplies the clock signal A to the NOR gate 21 only when the high level clock selection signal is latched by the flip-flop 13. The AND gate 20 supplies the clock signal B to the NOR gate 21 only when the low level clock selection signal is latched by the flip-flop 13. The NOR gate 21 generates an output signal, which is the inverted clock signal A or B supplied from one of the AND gates 19 and 20, as the clock signal x based on the clock selection signal latched by the flip-flop 13. The clock signal x is supplied from the NOR gate 21 to each clock terminal of the flip-flops 11-15.

The NOR gate 22 constitutes an output section together with the mask signal generating section. This output section outputs the clock signal A or B supplied from the NOR gate 21 as the output clock signal o.
The external supply of the output clock signal out is temporarily stopped by masking the output clock signal with the mask signal w supplied from the NOR gate 18 as well as being supplied to the outside as ut.

Next, the operation of the clock switching circuit configured as shown in FIG. 1 will be described. Here, it is assumed that the frequency of the output clock signal out is equal to the frequency of the clock signal A. In this state, the clock selection signal C is shown in FIG.
When it falls to the low level as shown in, the low level clock selection signal C rises P1 of the clock signal x.
Is latched by the flip-flop 11 and the clock signal x
At the rising edge P2 of the clock signal x, at the rising edge P3 of the clock signal x at the rising edge P3 of the clock signal x, and at the rising edge P4 of the clock signal x.
Is latched by the flip-flop 14 by the clock signal x
It is latched by the flip-flop 15 at the rising edge P5. The selection unit selects the clock signal B based on the clock selection signal C latched in the flip-flop 13 at the rising edge P3 of the clock signal x. After that, the clock signal x is synchronized with the clock signal B.

The contents of the flip-flop 12 do not match the contents of the flip-flop 15 only during the period from the rising edge P2 to P5 of the clock signal x. The mask signal generation unit generates the mask signal w which is maintained at the high level only during the period when the mismatch is detected. That is, the mask signal w invalidates the output clock signal out during this period. The frequency of the output clock signal out becomes equal to the frequency of the clock signal B after the falling of the mask signal w.

In the clock switching circuit of the above embodiment,
The flip-flops 11-15 are connected in series so as to form a shift register and sequentially latch the clock selection signal in synchronization with the clock signal from the NOR gate 21. A selection unit composed of AND gates 19 and 20 and a NOR gate 21 is connected to receive the clock selection signal latched by the predetermined flip-flop 13 of the flip-flops 11-15.
A mask signal generating unit composed of 17 and 17 and NOR gate 18 is connected to receive the clock selection signal latched by the flip-flop 12 in the stage preceding the predetermined flip-flop 13. As a result, the mask signal generation unit can respond to the change in the clock selection signal in advance of the selection unit by the step difference between the predetermined flip-flop 13 and the preceding-stage flip-flop 12, so that the mask signal generation unit can perform the manufacturing process. Even if you cannot respond quickly to changes in the clock selection signal due to variations in
After the NOR gate 22 stops the external supply of the output clock signal, the selection unit can switch one of the first and second clock signals to the other. That is, since the clocks are not switched during the external supply of the output clock signal, it is possible to reliably prevent the incorrect clock generated immediately after the switching. Therefore, it is possible to reliably improve the reduction in yield due to the variation in the manufacturing process.

A clock switching circuit according to the second embodiment of the present invention will be described below with reference to FIG.

This clock switching circuit is used when there are relatively few variations in the manufacturing process, and is constructed in the same manner as in the first embodiment except that the flip-flops 11 and 15 shown in FIG. 1 are omitted. In FIG. 3, in order to omit redundant description, the same parts as those in the first embodiment are designated by the same reference numerals.

Next, the operation of the clock switching circuit configured as shown in FIG. 3 will be described. Here, it is assumed that the frequency of the output clock signal out is equal to the frequency of the clock signal A. In this state, the clock selection signal C is shown in FIG.
When it falls to the low level as shown in, the low level clock selection signal C rises P1 of the clock signal x.
Is latched in the flip-flop 12 by the clock signal x
Is latched by the flip-flop 13 at the rising edge P2 of the clock signal x and latched by the flip-flop 14 at the rising edge P3 of the clock signal x. The selection unit selects the clock signal B based on the clock selection signal C latched by the flip-flop 13 at the rising edge P2 of the clock signal x.
After that, the clock signal x is synchronized with the clock signal B.

The contents of the flip-flop 12 do not match the contents of the flip-flop 14 only during the period from the rising edge P1 to P3 of the clock signal x. The mask signal generation unit generates the mask signal w which is maintained at the high level only during the period when the mismatch is detected. That is, the mask signal w invalidates the output clock signal out during this period. The frequency of the output clock signal out becomes equal to the frequency of the clock signal B after the falling of the mask signal w.

In the clock switching circuit of the second embodiment, the flip-flops 12-14 are connected in series so as to form a shift register, and the clock selection signals are sequentially latched in synchronization with the clock signal from the NOR gate 21. A selection unit composed of AND gates 19 and 20 and NOR gate 21 is connected to receive the clock selection signal latched by a predetermined flip-flop 13 of the flip-flops 12-14, and AND gates 16 and 17 and NOR gate 18 are connected. The configured mask signal generator is connected so as to receive the clock selection signal latched by the flip-flop 12 in the stage preceding the predetermined flip-flop 13. As a result, the mask signal generation unit can respond to the change in the clock selection signal in advance of the selection unit by the step difference between the predetermined flip-flop 13 and the preceding-stage flip-flop 12, so that the mask signal generation unit can perform the manufacturing process. Even if the clock selection signal cannot be quickly responded to due to variations in the clock signal, the selection unit switches one of the first and second clock signals to the other after the NOR gate 22 stops the external supply of the output clock signal. Is possible. That is, since the clock is not switched during the external supply of the output clock signal,
It is possible to reliably prevent an illegal clock generated immediately after this switching. Therefore, it is possible to reliably improve the reduction in yield due to the variation in the manufacturing process. In this example,
Further, the total number of flip-flops can be reduced as compared with the first embodiment.

The present invention is not limited to the clock switching circuits of the first and second embodiments, and can be variously modified without departing from the spirit thereof.

[0023]

According to the present invention, it is possible to prevent an illegal clock generated immediately after clock switching due to variations in manufacturing process.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a clock switching circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the clock switching circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a clock switching circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the clock switching circuit shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of a conventional clock switching circuit.

6 is a time chart showing the operation of the clock switching circuit shown in FIG.

FIG. 7 is a time chart for explaining an illegal clock generated due to a variation in manufacturing process in the clock switching circuit shown in FIG.

[Explanation of symbols]

11-15 ... D-type flip-flops 16, 17, 1
9, 20 ... And gate, 18, 21, 22 ... NOR gate.

Claims (2)

[Claims] 1. A register section for periodically latching a clock selection signal, a selection section for selecting one of a first clock signal and a second clock signal based on a clock selection signal obtained from the register section, and a selection section by this selection section. The register unit is provided with an output unit that supplies the selected clock signal to the outside as an output clock signal and temporarily stops the external supply of the output clock signal in response to a change of the clock selection signal obtained from the register unit. It has a plurality of flip-flops connected in series so as to form a register and sequentially latching the clock selection signal in synchronization with the clock signal selected by the selection unit, and the selection unit has a predetermined one of the plurality of flip-flops. Connected to receive a clock select signal latched by a flip-flop, said A clock switching circuit, wherein the output means is connected so as to receive the clock selection signal latched by the flip-flop at a stage preceding the predetermined flip-flop. 2. The output means outputs an output clock signal only during a period when a clock selection signal latched by a flip-flop preceding the predetermined flip-flop does not match a clock selection signal latched by a flip-flop subsequent to the predetermined flip-flop. 2. The clock switching circuit according to claim 1, further comprising a masking unit for invalidating.