JPH02184111A - Signal selection circuit - Google Patents

Abstract

PURPOSE:To prevent production of a pulse narrower than an input signal and selectively switch an asynchronous input signal effectively by blocking an output when the input signal having selected so far goes to an L level and starting a signal output when the input signal outputted newly goes to an L level. CONSTITUTION:When a selection signal S is given asynchronously with plural asynchronous input signals A, B, the selection output is blocked when the input signal having selected so far goes to an L level, and the signal selection output is started from the point of time when the input signal selected newly according to the selection signal S goes to an L level under the condition that the signal output is blocked. Thus, a pulse width of a selected output signal OUT corresponds to the pulse width of the input signal without fail. Thus, the signal output with a narrower width than the pulse width of the input signal is avoided and the design is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a signal selection circuit useful for asynchronously selecting and switching asynchronous input signals of a guard number.

(Prior Art) When realizing various signal processing circuits (systems), for example, as shown in FIG.
The circuit consisting of B) (shared circuit section) is often shared. For example, a memory device is often shared, or a sub-processor with a dedicated processing function is often shared by a plurality of main processors. When constructing such a system, the plurality of circuits (systems A and B) do not necessarily operate synchronously; - in boat fishing, they often operate asynchronously and independently. Furthermore, the frequencies of the clock systems that control their operations are different, and their operating speeds are often different.

For this reason, when the above-mentioned shared circuit section is accessed by a plurality of circuits, the selection signal is used to switch the input signal to the shared circuit section. Conventionally, in boat fishing, a signal selection circuit as shown in FIG. 6 has been used to switch the input signals.

This signal selection circuit gate-controls the gate circuits 1 and 2 which manually input two systems of asynchronous digital input signals A and B, respectively, in accordance with the selection signal S that has been inverted and non-inverted in an inverter circuit 3, thereby controlling each of the above-mentioned signals. A and B are selectively passed through and output via an OR circuit 4.

However, using such a signal selection circuit, the input signals A,
When B is selected and switched, these signals A.

Since B is synchronous and their pulse widths are mutually independent, a signal with a narrow pulse width called a so-called whisker, that is, a signal with a pulse width narrower than the pulse width of the input signals A and B is likely to be output. Such signal output causes malfunction in the shared circuit section, and it is necessary to eliminate such harmful effects.
Various efforts have been made in the past. For example, selection signal S
Adding restrictions such as synchronizing the switching timing with the input signal, or applying the selection signal S to the subsequent circuit section together with the selectively switched output signal, thereby allowing selection over a certain period of time from the switching timing. Countermeasures have been taken, such as logical processing to ignore the output signal.

However, it is very difficult to develop such countermeasures each time, and it is necessary to be familiar with the circuit (system) specifications including the characteristics of the input signal. Therefore, when a system requiring this type of signal switching is integrated into a large-scale integrated circuit, it is undeniable that the development and design thereof becomes extremely difficult.

(Problem to be solved by the invention) In this way, in the past, multiple asynchronous input signals,
In order to selectively switch and use it without causing the so-called whisker problem, various ingenuity is required, and the circuit (system)
There was a problem that made the design extremely difficult.

The present invention has been made in consideration of these circumstances, and its purpose is to asynchronously process the input signals without producing a No. 13 output having a width narrower than the pulse width of a plurality of asynchronous input signals. An object of the present invention is to provide a signal selection circuit that can selectively switch and output signals.

[Structure of the Invention] (Means for Solving the Problems) The present invention relates to a signal selection circuit that selectively outputs a plurality of asynchronous input signals according to a selection signal that is asynchronous to these input signals, When the input signal selected up to that point becomes L level, the output of that input signal is blocked, and on the condition that the output of this input signal is blocked, a new input signal is output according to the selection signal. The system is designed to allow selective output of an input signal from the point at which the selected input signal becomes L level, thereby preventing the output of a signal with a width smaller than the pulse width of each input signal. It is a feature.

Specifically, two flip-flops are provided that detect the fall of the input signal and perform a latching operation, and these flip-flops detect the input of the selection signal and the blocking of the output of the previously selected signal, respectively. The present invention is characterized in that the output of the input signal is controlled by the output of each of these flip-flops.

(Function) According to the present invention, when a selection signal is applied asynchronously to a plurality of asynchronous input signals, the selection output is changed at the point when the input signal selected up to that point becomes L level. On the condition that this signal output is blocked, selective output of the signal starts from the time when the input signal newly selected according to the selection signal becomes L level, so that the signal is selectively output. The pulse width of the signal always corresponds to the pulse width of the input signal.

As a result, a signal with a pulse width narrower than the pulse width of the input signal is no longer output, which effectively eliminates the problems of conventional circuits (systems) and facilitates their design. becomes.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a signal selection circuit according to an embodiment of the present invention. This embodiment circuit selectively outputs two input signals A and B that are asynchronous to each other in accordance with a selection signal S that is asynchronous to these input signals A and B, and generally includes a decoder 6 that identifies the selection signal S. and two gate circuit sections 7.8 which receive the selected outputs S^ and SB of this decoder 6 and gate control the input signals A and B, respectively, and synthesize the respective output signals from these gate circuit sections 7.8. It is constituted by an OR circuit 9 that outputs.

Here, the gate circuit section 7 (8) has a first flip-flop 7a that latches the selected output 5A (SB) from the decoder 6 using the falling edge of the input signal A as a clock.
(8a), and a second flip-flop that latches the output of the first flip-flop 8a (7a) of the other gate circuit section 8 (7) via the inverter circuit 7b (8b) using the fall of the input signal A as a clock input. flip-flop 7c (8c), and these first and second flip-flops 7a, 7
A gate (AND) circuit that gates the input signal A (B) according to each output of c (8a, 8c)? d(ad).

However, according to the circuit configured in this way, upon input of the one selection signal S, the decoder 6 outputs its selection outputs S^, SB.
The selection signals SA, SB are sent to the gate circuit section 7.8 provided corresponding to each input signal A, B to selectively output the input signal A or B.
give each. Specifically, when switching the selection output to input signal A while input signal B is selected, upon receiving the selection signal S instructing this, the selection output SA is switched to H level, and the selection output SR is switched to the H level. Switch to L level.

Then, when the first flip-flop 7a of the gate circuit section 7 detects the fall of the input signal A, it latches the selection output SA at the falling timing and sets the Q output to H.
transition to the level. Further, when the first flip-flop 8a of the gate circuit section 8 detects the fall of the input signal B, it latches the selection output SB at the falling timing and causes the Q output to transition to the L level. The Q output of the first flip-flop 8a closes the gate circuit 8d, and the output of the input signal B is blocked. That is, after the selection signal S is applied, the selection output of the input signal B is blocked from the time when the input signal B falls to the L level.

On the other hand, the above-mentioned gate circuit unit 7 is on standby with the first flip-flop 7a set when the input signal A falls. When the output of the input signal B is blocked by resetting the first flip-flop 8a in the gate circuit section 8, the signal is transferred to the inverter circuit 7b.
The second flip-flop 7C is manually set at the fall timing of the input signal A via the input signal A. By setting the second flip-flop 7C, the gate circuit 7d is opened, and selective output of the input signal A is started.

In other words, the input signal A is generated on the condition that the first flip-flop 7a is set according to the selection output S^, and the output of the input signal B, which has been selectively output so far, is blocked in the other gate circuit section 8. From the time when the second flip-flop 7c is set in synchronization with the fall of the input signal A, the signal is selectively output via the gate circuit 7d.

FIGS. 2 and 3 are diagrams showing the operation timing when switching the output from input signal A to input signal B in the circuit shown in FIG. 1 described above, respectively. As shown in these timing diagrams, input signals A and B are switched from the time when selection signal S is applied asynchronously to these signals. level, and after the output of the input signal B is blocked, the process starts from the time when the input signal A, which is newly selected and outputted on the condition that the output of this input signal B is blocked, becomes the L level. .

As a result, the signal to be selectively output is always reliably switched to the L level state, and a signal with a pulse width corresponding to the pulse width of the input signals A and B always appears at the output. In other words, it is possible to effectively switch the selection of input signals without producing a signal output with a pulse width narrower than the pulse width of the input signal.

Thus, according to this circuit, there is no need to impose restrictions on the switching timing as in the past, or to take measures such as logically making the output signal stable over a predetermined switching period in the subsequent circuit. It disappears.

Therefore, it is possible to greatly simplify the circuit configuration.

Furthermore, when designing a synchronous circuit, it becomes possible to clearly limit and separate circuit parts that are asynchronous from the basic circuit design. This is very convenient for synchronously designing large-scale integrated circuits, and by creating a library of the signal selection circuit part described above, the circuit itself can be made very orderly and the circuit design can be facilitated. It becomes possible to achieve this goal.

Note that the present invention is not limited to the embodiments described above. Although an example of a circuit configuration for selectively switching between two input signals has been described here, it can be similarly implemented in the case of selectively switching between three or more input signals. In this case, for example, as illustrated in FIG. 4, multi-input NOR circuits 7e, 8e, . . . are used instead of the inverter circuits 7b, 8b in the gate circuit section described above, The circuit may be configured such that the second seven lip-flops are set on the condition that each circuit section is in a state where output of the input signal is inhibited. Furthermore, the type of input signal to be switched is not particularly limited, and the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, when an asynchronous input signal is selected and switched according to a selection signal, the output of the input signal that has been selectively output is stopped when it reaches L level. However, under the condition that this output is blocked, the No. 15 output starts when the input signal to be newly output becomes L level, so a pulse (so-called whisker) whose width is narrower than that of the input signal is generated. It has great practical effects, such as being able to effectively select and switch asynchronous input signals and greatly simplifying synchronous circuit membranes including asynchronous circuit parts. It will be done.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a signal selection circuit according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the operation timing of the embodiment circuit, respectively, and FIG. 4 is another embodiment of the present invention. FIG. 5 is a schematic diagram of a circuit (system) requiring signal switching, and FIG. 6 is a diagram showing an example of the configuration of a conventional signal selection circuit. 6... decoder, 7. Death...Gate circuit section, 9...
OR circuit, 7a, 8a... first flip-flop,
7b, 8b... Inverter circuit, 7c, 8c... Second flip-flop, 7d, 8d... Gate (AND) circuit, 7c, 8c... NOR circuit. Figure 1 Applicant's agent Patent attorney Takehiko Suzue Figure 2 Textbook 1 Figure page 5

Claims (1)

[Claims] In a signal selection circuit that selectively outputs a plurality of asynchronous input signals in accordance with a selection signal asynchronous to these input signals, when the selection signal is switched, the input signal selected up to then is When the input signal becomes L level, the output of that input signal is blocked, and on the condition that the output of this input signal is blocked, from the time when the input signal newly selected according to the selection signal becomes L level. A signal selection circuit comprising means for permitting selective output of the input signal, and preventing output of a signal having a pulse width equal to or less than the pulse width of each of the input signals.