JPH0221943U - - Google Patents
Info
- Publication number
- JPH0221943U JPH0221943U JP10105388U JP10105388U JPH0221943U JP H0221943 U JPH0221943 U JP H0221943U JP 10105388 U JP10105388 U JP 10105388U JP 10105388 U JP10105388 U JP 10105388U JP H0221943 U JPH0221943 U JP H0221943U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- timing signal
- oscillation circuit
- phase synchronized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 6
- 230000010355 oscillation Effects 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案一実施例のブロツク構成図。第
２図は従来例のブロツク構成図。第３図は従来例
を用いたシステム説明図。
１１……バツフアメモリ回路、１２……信号選
択回路、１３……信号断検出回路、１４……位相
同期発振回路、１５……受信されたデータ符号列
、１６……受信タイミング信号、１７……送信タ
イミング信号、１８……送信されるデータ符号列
、１９……読出されたデータ符号列、２０……自
走指令信号、２１……切替指令信号、３１，３３
……データ送受信装置、３２……データ端末装置
、３４……信号切替器、Ｒ１，Ｒ２……受信端、
Ｓ１〜Ｓ３……送信端。
FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a block diagram of a conventional example. FIG. 3 is an explanatory diagram of a system using a conventional example. 11... Buffer memory circuit, 12... Signal selection circuit, 13... Signal disconnection detection circuit, 14... Phase synchronized oscillation circuit, 15... Received data code string, 16... Reception timing signal, 17... Transmission Timing signal, 18... Data code string to be transmitted, 19... Data code string read out, 20... Free running command signal, 21... Switching command signal, 31, 33
...Data transmitting and receiving device, 32...Data terminal device, 34...Signal switching device, R1, R2...Receiving end,
S1 to S3...Sending end.
Claims (1)
グ信号に同期して書込まれ、送信タイミング信号
に同期して読出されるバツフアメモリ回路１１と
、 受信タイミング信号に同期して送信タイミング
信号を発生する位相同期発振回路１４と を備えたデータ送受信装置において、 上記受信タイミング信号の断を検出する信号断
検出回路１３と、 この信号断検出回路の検出出力により送信デー
タを上記バツフアメモリ回路の出力に代えて受信
データ列を選択する信号選択回路１２と を備え、 上記位相同期発振回路は、上記信号断検出回路
の検出出力により自走の発振回路となる構成であ
る ことを特徴とするデータ送受信装置。[Claims for Utility Model Registration] A buffer memory circuit 11 in which a received data string is written in synchronization with a reception timing signal inputted from the outside and read out in synchronization with a transmission timing signal; A data transmitting/receiving device including a phase synchronized oscillation circuit 14 that generates a timing signal, a signal disconnection detection circuit 13 that detects disconnection of the reception timing signal, and a detection output of the signal disconnection detection circuit that transfers transmission data to the buffer memory circuit. and a signal selection circuit 12 that selects a received data string in place of the output of the phase synchronized oscillation circuit, and the phase synchronized oscillation circuit is configured to become a free-running oscillation circuit by the detection output of the signal disconnection detection circuit. Data transmitting/receiving device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988101053U JPH0718194Y2 (en) | 1988-07-29 | 1988-07-29 | Data transceiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988101053U JPH0718194Y2 (en) | 1988-07-29 | 1988-07-29 | Data transceiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0221943U true JPH0221943U (en) | 1990-02-14 |
| JPH0718194Y2 JPH0718194Y2 (en) | 1995-04-26 |
Family
ID=31329692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988101053U Expired - Lifetime JPH0718194Y2 (en) | 1988-07-29 | 1988-07-29 | Data transceiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0718194Y2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6069915A (en) * | 1983-09-27 | 1985-04-20 | Fujitsu Ltd | Timing extracting system |
| JPS6266444U (en) * | 1985-10-16 | 1987-04-24 | ||
| JPS6313201A (en) * | 1986-07-03 | 1988-01-20 | 黒井興産株式会社 | Connection holding construction |
-
1988
- 1988-07-29 JP JP1988101053U patent/JPH0718194Y2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6069915A (en) * | 1983-09-27 | 1985-04-20 | Fujitsu Ltd | Timing extracting system |
| JPS6266444U (en) * | 1985-10-16 | 1987-04-24 | ||
| JPS6313201A (en) * | 1986-07-03 | 1988-01-20 | 黒井興産株式会社 | Connection holding construction |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0718194Y2 (en) | 1995-04-26 |
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