JPH0322449U - - Google Patents

Info

Publication number
JPH0322449U
JPH0322449U JP8261689U JP8261689U JPH0322449U JP H0322449 U JPH0322449 U JP H0322449U JP 8261689 U JP8261689 U JP 8261689U JP 8261689 U JP8261689 U JP 8261689U JP H0322449 U JPH0322449 U JP H0322449U
Authority
JP
Japan
Prior art keywords
transmits
clock
data
transmission path
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8261689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8261689U priority Critical patent/JPH0322449U/ja
Publication of JPH0322449U publication Critical patent/JPH0322449U/ja
Pending legal-status Critical Current

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Landscapes

  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Bidirectional Digital Transmission (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係るシリアル伝送回路の一実
施例を示す構成図、第2図はその動作を示すタイ
ムチヤート、第3図は動作のフローチヤート、第
4図は従来のシリアル伝送回路の構成図である。 10……フルキーボード、11,12……伝送
路、13……制御LSI、14〜17,102〜
106……バツフア、18……システム側プロセ
ツサ、101……LSI。
Fig. 1 is a block diagram showing an embodiment of a serial transmission circuit according to the present invention, Fig. 2 is a time chart showing its operation, Fig. 3 is a flow chart of its operation, and Fig. 4 is a diagram of a conventional serial transmission circuit. FIG. 10... Full keyboard, 11, 12... Transmission line, 13... Control LSI, 14-17, 102-
106...Buffer, 18...System side processor, 101...LSI.

Claims (1)

【実用新案登録請求の範囲】 パラレルデジタルデータをシリアル信号に変換
して伝送するシリアル伝送回路において、 データを伝送する送信部と、データを受信する
受信部と、この受信部と前記送信部間を接続しデ
ータを伝送する第1の伝送路と、前記送信部及び
受信部間を接続しクロツクを送信する第2の伝送
路とを有し、 前記受信部が受信したシリアル信号をその内部
バツフアに取り込んだときに発生する受信時ステ
ータス信号によつて前記第2の伝送路で伝送され
るクロツクを停止するようにして、前記送信部は
前記第2の伝送路上のクロツクが停止されたこと
を検出して、データの送信を停止するようにした
ことを特徴とするシリアル伝送回路。
[Claims for Utility Model Registration] A serial transmission circuit that converts parallel digital data into a serial signal and transmits the serial signal, including a transmitter that transmits data, a receiver that receives data, and a connection between the receiver and the transmitter. It has a first transmission path that connects and transmits data, and a second transmission path that connects the transmitting section and the receiving section and transmits a clock, and transmits the serial signal received by the receiving section to its internal buffer. The transmitter detects that the clock on the second transmission path has been stopped by stopping the clock transmitted on the second transmission path based on a reception status signal generated when the clock is captured. A serial transmission circuit characterized in that the transmission of data is stopped.
JP8261689U 1989-07-13 1989-07-13 Pending JPH0322449U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8261689U JPH0322449U (en) 1989-07-13 1989-07-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8261689U JPH0322449U (en) 1989-07-13 1989-07-13

Publications (1)

Publication Number Publication Date
JPH0322449U true JPH0322449U (en) 1991-03-07

Family

ID=31629593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8261689U Pending JPH0322449U (en) 1989-07-13 1989-07-13

Country Status (1)

Country Link
JP (1) JPH0322449U (en)

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