JPS59126335U - Transmission/reception method - Google Patents
Transmission/reception methodInfo
- Publication number
- JPS59126335U JPS59126335U JP1916483U JP1916483U JPS59126335U JP S59126335 U JPS59126335 U JP S59126335U JP 1916483 U JP1916483 U JP 1916483U JP 1916483 U JP1916483 U JP 1916483U JP S59126335 U JPS59126335 U JP S59126335U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- control signal
- transmitting
- transmission
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
- Facsimile Transmission Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例における送受信回路を示す回路図、第２
図は本考案における実施例を示す送受信回路あ回路図、
第３図はそのタイムチャートである。図において、１は
フリップフロップ回路、２はアンド回路、３はオア回路
、４はデユード回路、５は認識回路、６はパリティチェ
ック回路、７は遅延回路、８はパルス発生回路、９は選
択回路、１０はフリップフロップ回路、１１はフリップ
フロップ回路である。Fig. 1 is a circuit diagram showing a transmitting/receiving circuit in a conventional example;
The figure is a circuit diagram of a transmitting/receiving circuit showing an embodiment of the present invention.
Figure 3 is the time chart. In the figure, 1 is a flip-flop circuit, 2 is an AND circuit, 3 is an OR circuit, 4 is a dual circuit, 5 is a recognition circuit, 6 is a parity check circuit, 7 is a delay circuit, 8 is a pulse generation circuit, and 9 is a selection circuit. , 10 is a flip-flop circuit, and 11 is a flip-flop circuit.
Claims (1)
出するためのパリティ信号と該制御信号と該パリティ信
号の取り込みを指示する取り込み信号を有し、送信信号
として、該制御信号と該パリティ信号を取り込んだこと
を示す認識信号を有する信号送受信回路において、該制
御信号のあやまりを検出した場合に該認識信号を送信し
ないことのみにより該制御信号のあやまりを報告するこ
とを特徴とする送受信方式。The received signal includes a control signal, a parity signal for detecting an error in the control signal, and an acquisition signal for instructing the acquisition of the control signal and the parity signal, and the transmission signal includes the control signal and the parity signal. A transmitting/receiving method characterized in that, in a signal transmitting/receiving circuit having a recognition signal indicating that the control signal has been captured, when an error in the control signal is detected, the error in the control signal is reported only by not transmitting the recognition signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1916483U JPS59126335U (en) | 1983-02-10 | 1983-02-10 | Transmission/reception method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1916483U JPS59126335U (en) | 1983-02-10 | 1983-02-10 | Transmission/reception method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59126335U true JPS59126335U (en) | 1984-08-25 |
Family
ID=30150320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1916483U Pending JPS59126335U (en) | 1983-02-10 | 1983-02-10 | Transmission/reception method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59126335U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61103299A (en) * | 1984-10-26 | 1986-05-21 | 富士ゼロックス株式会社 | Data retransmission controller for electronic copying machine |
-
1983
- 1983-02-10 JP JP1916483U patent/JPS59126335U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61103299A (en) * | 1984-10-26 | 1986-05-21 | 富士ゼロックス株式会社 | Data retransmission controller for electronic copying machine |
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